u-boot/board/freescale/t4qds/t4_rcw.cfg

#PBL preamble and RCW header
aa55aa55 010e0100
#serdes protocol  1_27_5_11
1607001b 18101b16 00000000 00000000
04362858 30548c00 ec020000 f5000000
00000000 ee0000ee 00000000 000307fc
00000000 00000000 00000000 00000028
T4240/ramboot: enable PBL tool for T4240 Added a default RCW(1_28_6_12) and PBI configure file for T4240, so it can use PBL tool to produce the ramboot image. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> 2013-03-25 07:40:02 +00:00			`#PBL preamble and RCW header`
			`aa55aa55 010e0100`
powerpc/t4qds: Add alternate serdes protocols to align with A-007186 A-007186: SerDes PLL is calibrated at reset. It is possible for jitter to increase and cause the PLL to unlock when the temperature delta from the time the PLL is calibrated exceeds +56C/-66C when using X VDD of 1.35 V (or +70C/-80C when using XnVDD of 1.5 V). No issues are seen with LC VCO. Only the protocols using Ring VCOs are impacted. Workaround: For all 1.25/2.5/5 GHz protocols, use LC VCO instead of Ring VCO, this need to use alternate serdes protocols. The alternate option has the same functionality as the original option; the only difference being LC VCO rather than Ring VCO. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> 2014-05-16 02:52:33 +00:00			`#serdes protocol 1_27_5_11`
powerpc/t4240qds: Update RCW, defconfig and maintainer 1. board/freescale/t4qds/t4_rcw.cfg 1.8GHz support is requested as default frequency, so update the rcw. 2. remove un-used configs configs/T4160QDS_SPIFLASH_defconfig configs/T4240QDS_SPIFLASH_defconfig SPI boot is not available on T4QDS, so the configs should be removed. 3. board/freescale/t4qds/MAINTAINERS Updated MAINTAINERS accordingly. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> [York Sun: revise subject] Reviewed-by: York Sun <yorksun@freescale.com> 2015-04-27 07:28:17 +00:00			`1607001b 18101b16 00000000 00000000`
powerpc/t4qds: Add alternate serdes protocols to align with A-007186 A-007186: SerDes PLL is calibrated at reset. It is possible for jitter to increase and cause the PLL to unlock when the temperature delta from the time the PLL is calibrated exceeds +56C/-66C when using X VDD of 1.35 V (or +70C/-80C when using XnVDD of 1.5 V). No issues are seen with LC VCO. Only the protocols using Ring VCOs are impacted. Workaround: For all 1.25/2.5/5 GHz protocols, use LC VCO instead of Ring VCO, this need to use alternate serdes protocols. The alternate option has the same functionality as the original option; the only difference being LC VCO rather than Ring VCO. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> 2014-05-16 02:52:33 +00:00			`04362858 30548c00 ec020000 f5000000`
powerpc/t4240: updated rcw_cfg to align with default hardware configuration Default configuration has been changed, the most important one is DDR ref_clock which is changed from 66.67MHz to 133.33MHz. so the ratio need to change from 24x to 12x to keep the DDR frequency. There are also some other optimise to align with default configuration. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> 2013-09-11 04:58:34 +00:00			`00000000 ee0000ee 00000000 000307fc`
powerpc/t4240: updated RCW and PBI for rev2.0 Updated the RCW for rev2.0 which uses new frequency settings as below: Clock Configuration: CPU0:1666.667 MHz, CPU1:1666.667 MHz, CPU2:1666.667 MHz, CPU3:1666.667 MHz, CPU4:1666.667 MHz, CPU5:1666.667 MHz, CPU6:1666.667 MHz, CPU7:1666.667 MHz, CPU8:1666.667 MHz, CPU9:1666.667 MHz, CPU10:1666.667 MHz, CPU11:1666.667MHz, CCB:733.333 MHz, DDR:933.333 MHz (1866.667 MT/s data rate) (Asynchronous), IFC:183.333 MHz FMAN1: 733.333 MHz FMAN2: 733.333 MHz QMAN: 366.667 MHz PME: 533.333 MHz Remove workaround of IFC bus speed and SERDES A-006031 of rev1.0. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> 2014-04-21 03:21:03 +00:00			`00000000 00000000 00000000 00000028`