mirror of
https://github.com/AsahiLinux/u-boot
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214 lines
5.1 KiB
Text
214 lines
5.1 KiB
Text
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/*
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* Device Tree file for Marvell Armada 375 evaluation board
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* (DB-88F6720)
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*
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* Copyright (C) 2014 Marvell
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*
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* Gregory CLEMENT <gregory.clement@free-electrons.com>
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* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
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*
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* This file is dual-licensed: you can use it either under the terms
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* of the GPL or the X11 license, at your option. Note that this dual
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* licensing only applies to this file, and not this project as a
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* whole.
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*
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* a) This file is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of the
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* License, or (at your option) any later version.
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*
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* This file is distributed in the hope that it will be useful
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* Or, alternatively
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*
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* b) Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
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* files (the "Software"), to deal in the Software without
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* restriction, including without limitation the rights to use
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* copy, modify, merge, publish, distribute, sublicense, and/or
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* sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following
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* conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
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* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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/dts-v1/;
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#include <dt-bindings/gpio/gpio.h>
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#include "armada-375.dtsi"
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/ {
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model = "Marvell Armada 375 Development Board";
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compatible = "marvell,a375-db", "marvell,armada375";
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chosen {
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stdout-path = "serial0:115200n8";
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};
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aliases {
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/* So that mvebu u-boot can update the MAC addresses */
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ethernet0 = ð0;
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ethernet1 = ð1;
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spi0 = &spi0;
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};
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memory {
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device_type = "memory";
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reg = <0x00000000 0x40000000>; /* 1 GB */
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};
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soc {
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ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
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MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000
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MBUS_ID(0x09, 0x09) 0 0xf1100000 0x10000
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MBUS_ID(0x09, 0x05) 0 0xf1110000 0x10000>;
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internal-regs {
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spi@10600 {
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pinctrl-0 = <&spi0_pins>;
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pinctrl-names = "default";
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/*
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* SPI conflicts with NAND, so we disable it
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* here, and select NAND as the enabled device
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* by default.
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*/
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status = "okay";
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spi-flash@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "n25q128a13", "jedec,spi-nor";
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reg = <0>; /* Chip select 0 */
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spi-max-frequency = <108000000>;
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};
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};
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i2c@11000 {
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status = "okay";
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clock-frequency = <100000>;
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pinctrl-0 = <&i2c0_pins>;
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pinctrl-names = "default";
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};
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i2c@11100 {
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status = "okay";
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clock-frequency = <100000>;
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pinctrl-0 = <&i2c1_pins>;
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pinctrl-names = "default";
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};
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serial@12000 {
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status = "okay";
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};
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pinctrl {
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sdio_st_pins: sdio-st-pins {
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marvell,pins = "mpp44", "mpp45";
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marvell,function = "gpio";
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};
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};
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sata@a0000 {
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status = "okay";
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nr-ports = <2>;
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};
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nand: nand@d0000 {
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pinctrl-0 = <&nand_pins>;
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pinctrl-names = "default";
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status = "okay";
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num-cs = <1>;
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marvell,nand-keep-config;
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marvell,nand-enable-arbiter;
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nand-on-flash-bbt;
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nand-ecc-strength = <4>;
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nand-ecc-step-size = <512>;
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partition@0 {
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label = "U-Boot";
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reg = <0 0x800000>;
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};
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partition@800000 {
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label = "Linux";
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reg = <0x800000 0x800000>;
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};
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partition@1000000 {
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label = "Filesystem";
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reg = <0x1000000 0x3f000000>;
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};
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};
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usb@54000 {
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status = "okay";
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};
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usb3@58000 {
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status = "okay";
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};
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mvsdio@d4000 {
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pinctrl-0 = <&sdio_pins &sdio_st_pins>;
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pinctrl-names = "default";
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status = "okay";
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cd-gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>;
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wp-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
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};
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mdio {
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phy0: ethernet-phy@0 {
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reg = <0>;
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};
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phy3: ethernet-phy@3 {
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reg = <3>;
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};
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};
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ethernet@f0000 {
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status = "okay";
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eth0@c4000 {
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status = "okay";
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phy = <&phy0>;
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phy-mode = "rgmii-id";
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};
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eth1@c5000 {
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status = "okay";
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phy = <&phy3>;
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phy-mode = "gmii";
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};
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};
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};
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pcie-controller {
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status = "okay";
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/*
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* The two PCIe units are accessible through
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* standard PCIe slots on the board.
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*/
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pcie@1,0 {
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/* Port 0, Lane 0 */
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status = "okay";
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};
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pcie@2,0 {
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/* Port 1, Lane 0 */
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status = "okay";
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};
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};
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};
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};
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