2008-10-30 21:41:01 +00:00
|
|
|
/*
|
|
|
|
* Copyright 2008, Freescale Semiconductor, Inc
|
|
|
|
* Andy Fleming
|
|
|
|
*
|
|
|
|
* Based vaguely on the Linux code
|
|
|
|
*
|
2013-07-08 07:37:19 +00:00
|
|
|
* SPDX-License-Identifier: GPL-2.0+
|
2008-10-30 21:41:01 +00:00
|
|
|
*/
|
|
|
|
|
|
|
|
#include <config.h>
|
|
|
|
#include <common.h>
|
|
|
|
#include <command.h>
|
2014-05-23 18:47:06 +00:00
|
|
|
#include <errno.h>
|
2008-10-30 21:41:01 +00:00
|
|
|
#include <mmc.h>
|
|
|
|
#include <part.h>
|
|
|
|
#include <malloc.h>
|
|
|
|
#include <linux/list.h>
|
2009-04-05 08:00:54 +00:00
|
|
|
#include <div64.h>
|
2013-09-09 14:30:26 +00:00
|
|
|
#include "mmc_private.h"
|
2008-10-30 21:41:01 +00:00
|
|
|
|
|
|
|
static struct list_head mmc_devices;
|
|
|
|
static int cur_dev_num = -1;
|
|
|
|
|
2014-07-12 19:24:08 +00:00
|
|
|
__weak int board_mmc_getwp(struct mmc *mmc)
|
2012-12-03 02:19:46 +00:00
|
|
|
{
|
|
|
|
return -1;
|
|
|
|
}
|
|
|
|
|
|
|
|
int mmc_getwp(struct mmc *mmc)
|
|
|
|
{
|
|
|
|
int wp;
|
|
|
|
|
|
|
|
wp = board_mmc_getwp(mmc);
|
|
|
|
|
2013-03-21 04:00:03 +00:00
|
|
|
if (wp < 0) {
|
2014-03-11 17:34:20 +00:00
|
|
|
if (mmc->cfg->ops->getwp)
|
|
|
|
wp = mmc->cfg->ops->getwp(mmc);
|
2013-03-21 04:00:03 +00:00
|
|
|
else
|
|
|
|
wp = 0;
|
|
|
|
}
|
2012-12-03 02:19:46 +00:00
|
|
|
|
|
|
|
return wp;
|
|
|
|
}
|
|
|
|
|
2014-07-10 20:46:28 +00:00
|
|
|
__weak int board_mmc_getcd(struct mmc *mmc)
|
|
|
|
{
|
2010-02-05 14:04:43 +00:00
|
|
|
return -1;
|
|
|
|
}
|
|
|
|
|
2013-09-09 14:30:26 +00:00
|
|
|
int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
|
2008-10-30 21:41:01 +00:00
|
|
|
{
|
2011-03-11 02:01:14 +00:00
|
|
|
int ret;
|
2012-03-15 18:41:35 +00:00
|
|
|
|
|
|
|
#ifdef CONFIG_MMC_TRACE
|
2011-03-11 02:01:14 +00:00
|
|
|
int i;
|
|
|
|
u8 *ptr;
|
|
|
|
|
|
|
|
printf("CMD_SEND:%d\n", cmd->cmdidx);
|
|
|
|
printf("\t\tARG\t\t\t 0x%08X\n", cmd->cmdarg);
|
2014-03-11 17:34:20 +00:00
|
|
|
ret = mmc->cfg->ops->send_cmd(mmc, cmd, data);
|
2011-03-11 02:01:14 +00:00
|
|
|
switch (cmd->resp_type) {
|
|
|
|
case MMC_RSP_NONE:
|
|
|
|
printf("\t\tMMC_RSP_NONE\n");
|
|
|
|
break;
|
|
|
|
case MMC_RSP_R1:
|
|
|
|
printf("\t\tMMC_RSP_R1,5,6,7 \t 0x%08X \n",
|
|
|
|
cmd->response[0]);
|
|
|
|
break;
|
|
|
|
case MMC_RSP_R1b:
|
|
|
|
printf("\t\tMMC_RSP_R1b\t\t 0x%08X \n",
|
|
|
|
cmd->response[0]);
|
|
|
|
break;
|
|
|
|
case MMC_RSP_R2:
|
|
|
|
printf("\t\tMMC_RSP_R2\t\t 0x%08X \n",
|
|
|
|
cmd->response[0]);
|
|
|
|
printf("\t\t \t\t 0x%08X \n",
|
|
|
|
cmd->response[1]);
|
|
|
|
printf("\t\t \t\t 0x%08X \n",
|
|
|
|
cmd->response[2]);
|
|
|
|
printf("\t\t \t\t 0x%08X \n",
|
|
|
|
cmd->response[3]);
|
|
|
|
printf("\n");
|
|
|
|
printf("\t\t\t\t\tDUMPING DATA\n");
|
|
|
|
for (i = 0; i < 4; i++) {
|
|
|
|
int j;
|
|
|
|
printf("\t\t\t\t\t%03d - ", i*4);
|
2012-03-08 02:35:34 +00:00
|
|
|
ptr = (u8 *)&cmd->response[i];
|
2011-03-11 02:01:14 +00:00
|
|
|
ptr += 3;
|
|
|
|
for (j = 0; j < 4; j++)
|
|
|
|
printf("%02X ", *ptr--);
|
|
|
|
printf("\n");
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
case MMC_RSP_R3:
|
|
|
|
printf("\t\tMMC_RSP_R3,4\t\t 0x%08X \n",
|
|
|
|
cmd->response[0]);
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
printf("\t\tERROR MMC rsp not supported\n");
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
#else
|
2014-03-11 17:34:20 +00:00
|
|
|
ret = mmc->cfg->ops->send_cmd(mmc, cmd, data);
|
2011-03-11 02:01:14 +00:00
|
|
|
#endif
|
2012-03-15 18:41:35 +00:00
|
|
|
return ret;
|
2008-10-30 21:41:01 +00:00
|
|
|
}
|
|
|
|
|
2013-09-09 14:30:26 +00:00
|
|
|
int mmc_send_status(struct mmc *mmc, int timeout)
|
2011-03-11 02:01:12 +00:00
|
|
|
{
|
|
|
|
struct mmc_cmd cmd;
|
2012-02-05 22:29:12 +00:00
|
|
|
int err, retries = 5;
|
2011-03-11 02:01:12 +00:00
|
|
|
#ifdef CONFIG_MMC_TRACE
|
|
|
|
int status;
|
|
|
|
#endif
|
|
|
|
|
|
|
|
cmd.cmdidx = MMC_CMD_SEND_STATUS;
|
|
|
|
cmd.resp_type = MMC_RSP_R1;
|
2011-08-10 07:24:48 +00:00
|
|
|
if (!mmc_host_is_spi(mmc))
|
|
|
|
cmd.cmdarg = mmc->rca << 16;
|
2011-03-11 02:01:12 +00:00
|
|
|
|
|
|
|
do {
|
|
|
|
err = mmc_send_cmd(mmc, &cmd, NULL);
|
2012-02-05 22:29:12 +00:00
|
|
|
if (!err) {
|
|
|
|
if ((cmd.response[0] & MMC_STATUS_RDY_FOR_DATA) &&
|
|
|
|
(cmd.response[0] & MMC_STATUS_CURR_STATE) !=
|
|
|
|
MMC_STATE_PRG)
|
|
|
|
break;
|
|
|
|
else if (cmd.response[0] & MMC_STATUS_MASK) {
|
2013-09-04 15:12:25 +00:00
|
|
|
#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
|
2012-02-05 22:29:12 +00:00
|
|
|
printf("Status Error: 0x%08X\n",
|
|
|
|
cmd.response[0]);
|
2013-09-04 15:12:25 +00:00
|
|
|
#endif
|
2012-02-05 22:29:12 +00:00
|
|
|
return COMM_ERR;
|
|
|
|
}
|
|
|
|
} else if (--retries < 0)
|
2011-03-11 02:01:12 +00:00
|
|
|
return err;
|
|
|
|
|
|
|
|
udelay(1000);
|
|
|
|
|
|
|
|
} while (timeout--);
|
|
|
|
|
2011-03-11 02:01:14 +00:00
|
|
|
#ifdef CONFIG_MMC_TRACE
|
|
|
|
status = (cmd.response[0] & MMC_STATUS_CURR_STATE) >> 9;
|
|
|
|
printf("CURR STATE:%d\n", status);
|
|
|
|
#endif
|
2012-06-03 21:32:13 +00:00
|
|
|
if (timeout <= 0) {
|
2013-09-04 15:12:25 +00:00
|
|
|
#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
|
2011-03-11 02:01:12 +00:00
|
|
|
printf("Timeout waiting card ready\n");
|
2013-09-04 15:12:25 +00:00
|
|
|
#endif
|
2011-03-11 02:01:12 +00:00
|
|
|
return TIMEOUT;
|
|
|
|
}
|
2014-04-03 09:34:32 +00:00
|
|
|
if (cmd.response[0] & MMC_STATUS_SWITCH_ERROR)
|
|
|
|
return SWITCH_ERR;
|
2011-03-11 02:01:12 +00:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2013-09-09 14:30:26 +00:00
|
|
|
int mmc_set_blocklen(struct mmc *mmc, int len)
|
2008-10-30 21:41:01 +00:00
|
|
|
{
|
|
|
|
struct mmc_cmd cmd;
|
|
|
|
|
mmc: Fix handling of bus widths and DDR card capabilities
If the MMC_MODE_DDR_52MHz flag is set in card capabilities bitmask,
it is never cleared, even if switching to DDR mode fails, and if
the controller driver uses this flag to check the DDR mode, it can
take incorrect actions.
Also, DDR related checks in mmc_startup() incorrectly handle the case
when the host controller does not support some bus widths (e.g. can't
support 8 bits), since the host_caps is checked for DDR bit, but not
bus width bits.
This fix clearly separates using of card_caps bitmask, having there
the flags for the capabilities, that the card can support, and actual
operation mode, described outside of card_caps (i.e. bus_width and
ddr_mode fields in mmc structure). Separate host controller drivers
may need to be updated to use the actual flags. Respectively,
the capabilities checks in mmc_startup are made more correct and clear.
Also, some clean up is made with errors handling and code syntax layout.
Signed-off-by: Andrew Gabbasov <andrew_gabbasov@mentor.com>
2014-12-01 12:59:09 +00:00
|
|
|
if (mmc->ddr_mode)
|
2014-05-16 04:59:54 +00:00
|
|
|
return 0;
|
|
|
|
|
2008-10-30 21:41:01 +00:00
|
|
|
cmd.cmdidx = MMC_CMD_SET_BLOCKLEN;
|
|
|
|
cmd.resp_type = MMC_RSP_R1;
|
|
|
|
cmd.cmdarg = len;
|
|
|
|
|
|
|
|
return mmc_send_cmd(mmc, &cmd, NULL);
|
|
|
|
}
|
|
|
|
|
|
|
|
struct mmc *find_mmc_device(int dev_num)
|
|
|
|
{
|
|
|
|
struct mmc *m;
|
|
|
|
struct list_head *entry;
|
|
|
|
|
|
|
|
list_for_each(entry, &mmc_devices) {
|
|
|
|
m = list_entry(entry, struct mmc, link);
|
|
|
|
|
|
|
|
if (m->block_dev.dev == dev_num)
|
|
|
|
return m;
|
|
|
|
}
|
|
|
|
|
2013-09-04 15:12:25 +00:00
|
|
|
#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
|
2008-10-30 21:41:01 +00:00
|
|
|
printf("MMC Device %d not found\n", dev_num);
|
2013-09-04 15:12:25 +00:00
|
|
|
#endif
|
2008-10-30 21:41:01 +00:00
|
|
|
|
|
|
|
return NULL;
|
|
|
|
}
|
|
|
|
|
2013-06-14 11:07:25 +00:00
|
|
|
static int mmc_read_blocks(struct mmc *mmc, void *dst, lbaint_t start,
|
2012-10-29 13:34:43 +00:00
|
|
|
lbaint_t blkcnt)
|
2008-10-30 21:41:01 +00:00
|
|
|
{
|
|
|
|
struct mmc_cmd cmd;
|
|
|
|
struct mmc_data data;
|
|
|
|
|
2010-10-25 14:23:56 +00:00
|
|
|
if (blkcnt > 1)
|
|
|
|
cmd.cmdidx = MMC_CMD_READ_MULTIPLE_BLOCK;
|
|
|
|
else
|
|
|
|
cmd.cmdidx = MMC_CMD_READ_SINGLE_BLOCK;
|
2008-10-30 21:41:01 +00:00
|
|
|
|
|
|
|
if (mmc->high_capacity)
|
2010-10-25 14:23:56 +00:00
|
|
|
cmd.cmdarg = start;
|
2008-10-30 21:41:01 +00:00
|
|
|
else
|
2010-10-25 14:23:56 +00:00
|
|
|
cmd.cmdarg = start * mmc->read_bl_len;
|
2008-10-30 21:41:01 +00:00
|
|
|
|
|
|
|
cmd.resp_type = MMC_RSP_R1;
|
|
|
|
|
|
|
|
data.dest = dst;
|
2010-10-25 14:23:56 +00:00
|
|
|
data.blocks = blkcnt;
|
2008-10-30 21:41:01 +00:00
|
|
|
data.blocksize = mmc->read_bl_len;
|
|
|
|
data.flags = MMC_DATA_READ;
|
|
|
|
|
2010-10-25 14:23:56 +00:00
|
|
|
if (mmc_send_cmd(mmc, &cmd, &data))
|
|
|
|
return 0;
|
2008-10-30 21:41:01 +00:00
|
|
|
|
2010-10-25 14:23:56 +00:00
|
|
|
if (blkcnt > 1) {
|
|
|
|
cmd.cmdidx = MMC_CMD_STOP_TRANSMISSION;
|
|
|
|
cmd.cmdarg = 0;
|
|
|
|
cmd.resp_type = MMC_RSP_R1b;
|
|
|
|
if (mmc_send_cmd(mmc, &cmd, NULL)) {
|
2013-09-04 15:12:25 +00:00
|
|
|
#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
|
2010-10-25 14:23:56 +00:00
|
|
|
printf("mmc fail to send stop cmd\n");
|
2013-09-04 15:12:25 +00:00
|
|
|
#endif
|
2010-10-25 14:23:56 +00:00
|
|
|
return 0;
|
|
|
|
}
|
2008-10-30 21:41:01 +00:00
|
|
|
}
|
|
|
|
|
2010-10-25 14:23:56 +00:00
|
|
|
return blkcnt;
|
2008-10-30 21:41:01 +00:00
|
|
|
}
|
|
|
|
|
2013-06-14 11:07:25 +00:00
|
|
|
static ulong mmc_bread(int dev_num, lbaint_t start, lbaint_t blkcnt, void *dst)
|
2008-10-30 21:41:01 +00:00
|
|
|
{
|
2010-10-25 14:23:56 +00:00
|
|
|
lbaint_t cur, blocks_todo = blkcnt;
|
|
|
|
|
|
|
|
if (blkcnt == 0)
|
|
|
|
return 0;
|
2008-10-30 21:41:01 +00:00
|
|
|
|
2010-10-25 14:23:56 +00:00
|
|
|
struct mmc *mmc = find_mmc_device(dev_num);
|
2008-10-30 21:41:01 +00:00
|
|
|
if (!mmc)
|
|
|
|
return 0;
|
|
|
|
|
2010-09-13 14:07:27 +00:00
|
|
|
if ((start + blkcnt) > mmc->block_dev.lba) {
|
2013-09-04 15:12:25 +00:00
|
|
|
#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
|
2013-06-14 11:07:25 +00:00
|
|
|
printf("MMC: block number 0x" LBAF " exceeds max(0x" LBAF ")\n",
|
2010-09-13 14:07:27 +00:00
|
|
|
start + blkcnt, mmc->block_dev.lba);
|
2013-09-04 15:12:25 +00:00
|
|
|
#endif
|
2010-09-13 14:07:27 +00:00
|
|
|
return 0;
|
|
|
|
}
|
2008-10-30 21:41:01 +00:00
|
|
|
|
2010-10-25 14:23:56 +00:00
|
|
|
if (mmc_set_blocklen(mmc, mmc->read_bl_len))
|
2008-10-30 21:41:01 +00:00
|
|
|
return 0;
|
|
|
|
|
2010-10-25 14:23:56 +00:00
|
|
|
do {
|
2014-03-11 17:34:20 +00:00
|
|
|
cur = (blocks_todo > mmc->cfg->b_max) ?
|
|
|
|
mmc->cfg->b_max : blocks_todo;
|
2010-10-25 14:23:56 +00:00
|
|
|
if(mmc_read_blocks(mmc, dst, start, cur) != cur)
|
|
|
|
return 0;
|
|
|
|
blocks_todo -= cur;
|
|
|
|
start += cur;
|
|
|
|
dst += cur * mmc->read_bl_len;
|
|
|
|
} while (blocks_todo > 0);
|
2008-10-30 21:41:01 +00:00
|
|
|
|
|
|
|
return blkcnt;
|
|
|
|
}
|
|
|
|
|
2012-10-29 13:34:43 +00:00
|
|
|
static int mmc_go_idle(struct mmc *mmc)
|
2008-10-30 21:41:01 +00:00
|
|
|
{
|
|
|
|
struct mmc_cmd cmd;
|
|
|
|
int err;
|
|
|
|
|
|
|
|
udelay(1000);
|
|
|
|
|
|
|
|
cmd.cmdidx = MMC_CMD_GO_IDLE_STATE;
|
|
|
|
cmd.cmdarg = 0;
|
|
|
|
cmd.resp_type = MMC_RSP_NONE;
|
|
|
|
|
|
|
|
err = mmc_send_cmd(mmc, &cmd, NULL);
|
|
|
|
|
|
|
|
if (err)
|
|
|
|
return err;
|
|
|
|
|
|
|
|
udelay(2000);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2012-10-29 13:34:43 +00:00
|
|
|
static int sd_send_op_cond(struct mmc *mmc)
|
2008-10-30 21:41:01 +00:00
|
|
|
{
|
|
|
|
int timeout = 1000;
|
|
|
|
int err;
|
|
|
|
struct mmc_cmd cmd;
|
|
|
|
|
|
|
|
do {
|
|
|
|
cmd.cmdidx = MMC_CMD_APP_CMD;
|
|
|
|
cmd.resp_type = MMC_RSP_R1;
|
|
|
|
cmd.cmdarg = 0;
|
|
|
|
|
|
|
|
err = mmc_send_cmd(mmc, &cmd, NULL);
|
|
|
|
|
|
|
|
if (err)
|
|
|
|
return err;
|
|
|
|
|
|
|
|
cmd.cmdidx = SD_CMD_APP_SEND_OP_COND;
|
|
|
|
cmd.resp_type = MMC_RSP_R3;
|
2010-01-20 17:20:39 +00:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Most cards do not answer if some reserved bits
|
|
|
|
* in the ocr are set. However, Some controller
|
|
|
|
* can set bit 7 (reserved for low voltages), but
|
|
|
|
* how to manage low voltages SD card is not yet
|
|
|
|
* specified.
|
|
|
|
*/
|
2010-12-24 13:12:21 +00:00
|
|
|
cmd.cmdarg = mmc_host_is_spi(mmc) ? 0 :
|
2014-03-11 17:34:20 +00:00
|
|
|
(mmc->cfg->voltages & 0xff8000);
|
2008-10-30 21:41:01 +00:00
|
|
|
|
|
|
|
if (mmc->version == SD_VERSION_2)
|
|
|
|
cmd.cmdarg |= OCR_HCS;
|
|
|
|
|
|
|
|
err = mmc_send_cmd(mmc, &cmd, NULL);
|
|
|
|
|
|
|
|
if (err)
|
|
|
|
return err;
|
|
|
|
|
|
|
|
udelay(1000);
|
|
|
|
} while ((!(cmd.response[0] & OCR_BUSY)) && timeout--);
|
|
|
|
|
|
|
|
if (timeout <= 0)
|
|
|
|
return UNUSABLE_ERR;
|
|
|
|
|
|
|
|
if (mmc->version != SD_VERSION_2)
|
|
|
|
mmc->version = SD_VERSION_1_0;
|
|
|
|
|
2010-12-24 13:12:21 +00:00
|
|
|
if (mmc_host_is_spi(mmc)) { /* read OCR for spi */
|
|
|
|
cmd.cmdidx = MMC_CMD_SPI_READ_OCR;
|
|
|
|
cmd.resp_type = MMC_RSP_R3;
|
|
|
|
cmd.cmdarg = 0;
|
|
|
|
|
|
|
|
err = mmc_send_cmd(mmc, &cmd, NULL);
|
|
|
|
|
|
|
|
if (err)
|
|
|
|
return err;
|
|
|
|
}
|
|
|
|
|
2009-04-05 08:00:56 +00:00
|
|
|
mmc->ocr = cmd.response[0];
|
2008-10-30 21:41:01 +00:00
|
|
|
|
|
|
|
mmc->high_capacity = ((mmc->ocr & OCR_HCS) == OCR_HCS);
|
|
|
|
mmc->rca = 0;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2012-11-28 15:21:13 +00:00
|
|
|
/* We pass in the cmd since otherwise the init seems to fail */
|
|
|
|
static int mmc_send_op_cond_iter(struct mmc *mmc, struct mmc_cmd *cmd,
|
|
|
|
int use_arg)
|
2008-10-30 21:41:01 +00:00
|
|
|
{
|
|
|
|
int err;
|
|
|
|
|
2012-11-28 15:21:13 +00:00
|
|
|
cmd->cmdidx = MMC_CMD_SEND_OP_COND;
|
|
|
|
cmd->resp_type = MMC_RSP_R3;
|
|
|
|
cmd->cmdarg = 0;
|
|
|
|
if (use_arg && !mmc_host_is_spi(mmc)) {
|
|
|
|
cmd->cmdarg =
|
2014-03-11 17:34:20 +00:00
|
|
|
(mmc->cfg->voltages &
|
2012-11-28 15:21:13 +00:00
|
|
|
(mmc->op_cond_response & OCR_VOLTAGE_MASK)) |
|
|
|
|
(mmc->op_cond_response & OCR_ACCESS_MODE);
|
|
|
|
|
2014-03-11 17:34:20 +00:00
|
|
|
if (mmc->cfg->host_caps & MMC_MODE_HC)
|
2012-11-28 15:21:13 +00:00
|
|
|
cmd->cmdarg |= OCR_HCS;
|
|
|
|
}
|
|
|
|
err = mmc_send_cmd(mmc, cmd, NULL);
|
|
|
|
if (err)
|
|
|
|
return err;
|
|
|
|
mmc->op_cond_response = cmd->response[0];
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2014-07-12 19:24:08 +00:00
|
|
|
static int mmc_send_op_cond(struct mmc *mmc)
|
2012-11-28 15:21:13 +00:00
|
|
|
{
|
|
|
|
struct mmc_cmd cmd;
|
|
|
|
int err, i;
|
|
|
|
|
2008-10-30 21:41:01 +00:00
|
|
|
/* Some cards seem to need this */
|
|
|
|
mmc_go_idle(mmc);
|
|
|
|
|
2011-03-11 02:01:13 +00:00
|
|
|
/* Asking to the card its capabilities */
|
2012-11-28 15:21:13 +00:00
|
|
|
mmc->op_cond_pending = 1;
|
|
|
|
for (i = 0; i < 2; i++) {
|
|
|
|
err = mmc_send_op_cond_iter(mmc, &cmd, i != 0);
|
|
|
|
if (err)
|
|
|
|
return err;
|
2011-05-19 20:21:41 +00:00
|
|
|
|
2012-11-28 15:21:13 +00:00
|
|
|
/* exit if not busy (flag seems to be inverted) */
|
|
|
|
if (mmc->op_cond_response & OCR_BUSY)
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
return IN_PROGRESS;
|
|
|
|
}
|
2011-05-19 20:21:41 +00:00
|
|
|
|
2014-07-12 19:24:08 +00:00
|
|
|
static int mmc_complete_op_cond(struct mmc *mmc)
|
2012-11-28 15:21:13 +00:00
|
|
|
{
|
|
|
|
struct mmc_cmd cmd;
|
|
|
|
int timeout = 1000;
|
|
|
|
uint start;
|
|
|
|
int err;
|
2011-05-19 20:21:41 +00:00
|
|
|
|
2012-11-28 15:21:13 +00:00
|
|
|
mmc->op_cond_pending = 0;
|
|
|
|
start = get_timer(0);
|
2008-10-30 21:41:01 +00:00
|
|
|
do {
|
2012-11-28 15:21:13 +00:00
|
|
|
err = mmc_send_op_cond_iter(mmc, &cmd, 1);
|
2008-10-30 21:41:01 +00:00
|
|
|
if (err)
|
|
|
|
return err;
|
2012-11-28 15:21:13 +00:00
|
|
|
if (get_timer(start) > timeout)
|
|
|
|
return UNUSABLE_ERR;
|
|
|
|
udelay(100);
|
|
|
|
} while (!(mmc->op_cond_response & OCR_BUSY));
|
2008-10-30 21:41:01 +00:00
|
|
|
|
2010-12-24 13:12:21 +00:00
|
|
|
if (mmc_host_is_spi(mmc)) { /* read OCR for spi */
|
|
|
|
cmd.cmdidx = MMC_CMD_SPI_READ_OCR;
|
|
|
|
cmd.resp_type = MMC_RSP_R3;
|
|
|
|
cmd.cmdarg = 0;
|
|
|
|
|
|
|
|
err = mmc_send_cmd(mmc, &cmd, NULL);
|
|
|
|
|
|
|
|
if (err)
|
|
|
|
return err;
|
|
|
|
}
|
|
|
|
|
2008-10-30 21:41:01 +00:00
|
|
|
mmc->version = MMC_VERSION_UNKNOWN;
|
2009-04-05 08:00:56 +00:00
|
|
|
mmc->ocr = cmd.response[0];
|
2008-10-30 21:41:01 +00:00
|
|
|
|
|
|
|
mmc->high_capacity = ((mmc->ocr & OCR_HCS) == OCR_HCS);
|
2014-01-30 23:11:12 +00:00
|
|
|
mmc->rca = 1;
|
2008-10-30 21:41:01 +00:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
|
2012-10-29 13:34:43 +00:00
|
|
|
static int mmc_send_ext_csd(struct mmc *mmc, u8 *ext_csd)
|
2008-10-30 21:41:01 +00:00
|
|
|
{
|
|
|
|
struct mmc_cmd cmd;
|
|
|
|
struct mmc_data data;
|
|
|
|
int err;
|
|
|
|
|
|
|
|
/* Get the Card Status Register */
|
|
|
|
cmd.cmdidx = MMC_CMD_SEND_EXT_CSD;
|
|
|
|
cmd.resp_type = MMC_RSP_R1;
|
|
|
|
cmd.cmdarg = 0;
|
|
|
|
|
2012-06-07 19:09:11 +00:00
|
|
|
data.dest = (char *)ext_csd;
|
2008-10-30 21:41:01 +00:00
|
|
|
data.blocks = 1;
|
2013-04-03 08:54:30 +00:00
|
|
|
data.blocksize = MMC_MAX_BLOCK_LEN;
|
2008-10-30 21:41:01 +00:00
|
|
|
data.flags = MMC_DATA_READ;
|
|
|
|
|
|
|
|
err = mmc_send_cmd(mmc, &cmd, &data);
|
|
|
|
|
|
|
|
return err;
|
|
|
|
}
|
|
|
|
|
|
|
|
|
2012-10-29 13:34:43 +00:00
|
|
|
static int mmc_switch(struct mmc *mmc, u8 set, u8 index, u8 value)
|
2008-10-30 21:41:01 +00:00
|
|
|
{
|
|
|
|
struct mmc_cmd cmd;
|
2011-03-11 02:01:12 +00:00
|
|
|
int timeout = 1000;
|
|
|
|
int ret;
|
2008-10-30 21:41:01 +00:00
|
|
|
|
|
|
|
cmd.cmdidx = MMC_CMD_SWITCH;
|
|
|
|
cmd.resp_type = MMC_RSP_R1b;
|
|
|
|
cmd.cmdarg = (MMC_SWITCH_MODE_WRITE_BYTE << 24) |
|
2011-03-11 02:01:12 +00:00
|
|
|
(index << 16) |
|
|
|
|
(value << 8);
|
2008-10-30 21:41:01 +00:00
|
|
|
|
2011-03-11 02:01:12 +00:00
|
|
|
ret = mmc_send_cmd(mmc, &cmd, NULL);
|
|
|
|
|
|
|
|
/* Waiting for the ready status */
|
2012-02-05 22:29:11 +00:00
|
|
|
if (!ret)
|
|
|
|
ret = mmc_send_status(mmc, timeout);
|
2011-03-11 02:01:12 +00:00
|
|
|
|
|
|
|
return ret;
|
|
|
|
|
2008-10-30 21:41:01 +00:00
|
|
|
}
|
|
|
|
|
2012-10-29 13:34:43 +00:00
|
|
|
static int mmc_change_freq(struct mmc *mmc)
|
2008-10-30 21:41:01 +00:00
|
|
|
{
|
2013-04-03 08:54:30 +00:00
|
|
|
ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
|
2008-10-30 21:41:01 +00:00
|
|
|
char cardtype;
|
|
|
|
int err;
|
|
|
|
|
mmc: Fix handling of bus widths and DDR card capabilities
If the MMC_MODE_DDR_52MHz flag is set in card capabilities bitmask,
it is never cleared, even if switching to DDR mode fails, and if
the controller driver uses this flag to check the DDR mode, it can
take incorrect actions.
Also, DDR related checks in mmc_startup() incorrectly handle the case
when the host controller does not support some bus widths (e.g. can't
support 8 bits), since the host_caps is checked for DDR bit, but not
bus width bits.
This fix clearly separates using of card_caps bitmask, having there
the flags for the capabilities, that the card can support, and actual
operation mode, described outside of card_caps (i.e. bus_width and
ddr_mode fields in mmc structure). Separate host controller drivers
may need to be updated to use the actual flags. Respectively,
the capabilities checks in mmc_startup are made more correct and clear.
Also, some clean up is made with errors handling and code syntax layout.
Signed-off-by: Andrew Gabbasov <andrew_gabbasov@mentor.com>
2014-12-01 12:59:09 +00:00
|
|
|
mmc->card_caps = MMC_MODE_4BIT | MMC_MODE_8BIT;
|
2008-10-30 21:41:01 +00:00
|
|
|
|
2010-12-24 13:12:21 +00:00
|
|
|
if (mmc_host_is_spi(mmc))
|
|
|
|
return 0;
|
|
|
|
|
2008-10-30 21:41:01 +00:00
|
|
|
/* Only version 4 supports high-speed */
|
|
|
|
if (mmc->version < MMC_VERSION_4)
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
err = mmc_send_ext_csd(mmc, ext_csd);
|
|
|
|
|
|
|
|
if (err)
|
|
|
|
return err;
|
|
|
|
|
2011-10-03 20:35:10 +00:00
|
|
|
cardtype = ext_csd[EXT_CSD_CARD_TYPE] & 0xf;
|
2008-10-30 21:41:01 +00:00
|
|
|
|
|
|
|
err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_HS_TIMING, 1);
|
|
|
|
|
|
|
|
if (err)
|
2014-04-03 09:34:32 +00:00
|
|
|
return err == SWITCH_ERR ? 0 : err;
|
2008-10-30 21:41:01 +00:00
|
|
|
|
|
|
|
/* Now check to see that it worked */
|
|
|
|
err = mmc_send_ext_csd(mmc, ext_csd);
|
|
|
|
|
|
|
|
if (err)
|
|
|
|
return err;
|
|
|
|
|
|
|
|
/* No high-speed support */
|
2011-10-03 20:35:10 +00:00
|
|
|
if (!ext_csd[EXT_CSD_HS_TIMING])
|
2008-10-30 21:41:01 +00:00
|
|
|
return 0;
|
|
|
|
|
|
|
|
/* High Speed is set, there are two types: 52MHz and 26MHz */
|
2014-05-16 04:59:54 +00:00
|
|
|
if (cardtype & EXT_CSD_CARD_TYPE_52) {
|
2014-12-01 12:59:10 +00:00
|
|
|
if (cardtype & EXT_CSD_CARD_TYPE_DDR_1_8V)
|
2014-05-16 04:59:54 +00:00
|
|
|
mmc->card_caps |= MMC_MODE_DDR_52MHz;
|
2008-10-30 21:41:01 +00:00
|
|
|
mmc->card_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
|
2014-05-16 04:59:54 +00:00
|
|
|
} else {
|
2008-10-30 21:41:01 +00:00
|
|
|
mmc->card_caps |= MMC_MODE_HS;
|
2014-05-16 04:59:54 +00:00
|
|
|
}
|
2008-10-30 21:41:01 +00:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2013-06-11 21:14:01 +00:00
|
|
|
static int mmc_set_capacity(struct mmc *mmc, int part_num)
|
|
|
|
{
|
|
|
|
switch (part_num) {
|
|
|
|
case 0:
|
|
|
|
mmc->capacity = mmc->capacity_user;
|
|
|
|
break;
|
|
|
|
case 1:
|
|
|
|
case 2:
|
|
|
|
mmc->capacity = mmc->capacity_boot;
|
|
|
|
break;
|
|
|
|
case 3:
|
|
|
|
mmc->capacity = mmc->capacity_rpmb;
|
|
|
|
break;
|
|
|
|
case 4:
|
|
|
|
case 5:
|
|
|
|
case 6:
|
|
|
|
case 7:
|
|
|
|
mmc->capacity = mmc->capacity_gp[part_num - 4];
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
return -1;
|
|
|
|
}
|
|
|
|
|
|
|
|
mmc->block_dev.lba = lldiv(mmc->capacity, mmc->read_bl_len);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2014-05-07 18:19:02 +00:00
|
|
|
int mmc_select_hwpart(int dev_num, int hwpart)
|
|
|
|
{
|
|
|
|
struct mmc *mmc = find_mmc_device(dev_num);
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
if (!mmc)
|
2014-05-23 18:47:06 +00:00
|
|
|
return -ENODEV;
|
2014-05-07 18:19:02 +00:00
|
|
|
|
|
|
|
if (mmc->part_num == hwpart)
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
if (mmc->part_config == MMCPART_NOAVAILABLE) {
|
|
|
|
printf("Card doesn't support part_switch\n");
|
2014-05-23 18:47:06 +00:00
|
|
|
return -EMEDIUMTYPE;
|
2014-05-07 18:19:02 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
ret = mmc_switch_part(dev_num, hwpart);
|
|
|
|
if (ret)
|
2014-05-23 18:47:06 +00:00
|
|
|
return ret;
|
2014-05-07 18:19:02 +00:00
|
|
|
|
|
|
|
mmc->part_num = hwpart;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
|
2011-05-02 16:26:26 +00:00
|
|
|
int mmc_switch_part(int dev_num, unsigned int part_num)
|
|
|
|
{
|
|
|
|
struct mmc *mmc = find_mmc_device(dev_num);
|
2013-06-11 21:14:01 +00:00
|
|
|
int ret;
|
2011-05-02 16:26:26 +00:00
|
|
|
|
|
|
|
if (!mmc)
|
|
|
|
return -1;
|
|
|
|
|
2013-06-11 21:14:01 +00:00
|
|
|
ret = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_PART_CONF,
|
|
|
|
(mmc->part_config & ~PART_ACCESS_MASK)
|
|
|
|
| (part_num & PART_ACCESS_MASK));
|
|
|
|
|
2014-09-02 23:31:23 +00:00
|
|
|
/*
|
|
|
|
* Set the capacity if the switch succeeded or was intended
|
|
|
|
* to return to representing the raw device.
|
|
|
|
*/
|
|
|
|
if ((ret == 0) || ((ret == -ENODEV) && (part_num == 0)))
|
|
|
|
ret = mmc_set_capacity(mmc, part_num);
|
|
|
|
|
|
|
|
return ret;
|
2011-05-02 16:26:26 +00:00
|
|
|
}
|
|
|
|
|
2012-01-02 01:15:37 +00:00
|
|
|
int mmc_getcd(struct mmc *mmc)
|
|
|
|
{
|
|
|
|
int cd;
|
|
|
|
|
|
|
|
cd = board_mmc_getcd(mmc);
|
|
|
|
|
2013-03-21 04:00:03 +00:00
|
|
|
if (cd < 0) {
|
2014-03-11 17:34:20 +00:00
|
|
|
if (mmc->cfg->ops->getcd)
|
|
|
|
cd = mmc->cfg->ops->getcd(mmc);
|
2013-03-21 04:00:03 +00:00
|
|
|
else
|
|
|
|
cd = 1;
|
|
|
|
}
|
2012-01-02 01:15:37 +00:00
|
|
|
|
|
|
|
return cd;
|
|
|
|
}
|
|
|
|
|
2012-10-29 13:34:43 +00:00
|
|
|
static int sd_switch(struct mmc *mmc, int mode, int group, u8 value, u8 *resp)
|
2008-10-30 21:41:01 +00:00
|
|
|
{
|
|
|
|
struct mmc_cmd cmd;
|
|
|
|
struct mmc_data data;
|
|
|
|
|
|
|
|
/* Switch the frequency */
|
|
|
|
cmd.cmdidx = SD_CMD_SWITCH_FUNC;
|
|
|
|
cmd.resp_type = MMC_RSP_R1;
|
|
|
|
cmd.cmdarg = (mode << 31) | 0xffffff;
|
|
|
|
cmd.cmdarg &= ~(0xf << (group * 4));
|
|
|
|
cmd.cmdarg |= value << (group * 4);
|
|
|
|
|
|
|
|
data.dest = (char *)resp;
|
|
|
|
data.blocksize = 64;
|
|
|
|
data.blocks = 1;
|
|
|
|
data.flags = MMC_DATA_READ;
|
|
|
|
|
|
|
|
return mmc_send_cmd(mmc, &cmd, &data);
|
|
|
|
}
|
|
|
|
|
|
|
|
|
2012-10-29 13:34:43 +00:00
|
|
|
static int sd_change_freq(struct mmc *mmc)
|
2008-10-30 21:41:01 +00:00
|
|
|
{
|
|
|
|
int err;
|
|
|
|
struct mmc_cmd cmd;
|
2011-10-03 13:54:59 +00:00
|
|
|
ALLOC_CACHE_ALIGN_BUFFER(uint, scr, 2);
|
|
|
|
ALLOC_CACHE_ALIGN_BUFFER(uint, switch_status, 16);
|
2008-10-30 21:41:01 +00:00
|
|
|
struct mmc_data data;
|
|
|
|
int timeout;
|
|
|
|
|
|
|
|
mmc->card_caps = 0;
|
|
|
|
|
2010-12-24 13:12:21 +00:00
|
|
|
if (mmc_host_is_spi(mmc))
|
|
|
|
return 0;
|
|
|
|
|
2008-10-30 21:41:01 +00:00
|
|
|
/* Read the SCR to find out if this card supports higher speeds */
|
|
|
|
cmd.cmdidx = MMC_CMD_APP_CMD;
|
|
|
|
cmd.resp_type = MMC_RSP_R1;
|
|
|
|
cmd.cmdarg = mmc->rca << 16;
|
|
|
|
|
|
|
|
err = mmc_send_cmd(mmc, &cmd, NULL);
|
|
|
|
|
|
|
|
if (err)
|
|
|
|
return err;
|
|
|
|
|
|
|
|
cmd.cmdidx = SD_CMD_APP_SEND_SCR;
|
|
|
|
cmd.resp_type = MMC_RSP_R1;
|
|
|
|
cmd.cmdarg = 0;
|
|
|
|
|
|
|
|
timeout = 3;
|
|
|
|
|
|
|
|
retry_scr:
|
2011-10-03 13:54:59 +00:00
|
|
|
data.dest = (char *)scr;
|
2008-10-30 21:41:01 +00:00
|
|
|
data.blocksize = 8;
|
|
|
|
data.blocks = 1;
|
|
|
|
data.flags = MMC_DATA_READ;
|
|
|
|
|
|
|
|
err = mmc_send_cmd(mmc, &cmd, &data);
|
|
|
|
|
|
|
|
if (err) {
|
|
|
|
if (timeout--)
|
|
|
|
goto retry_scr;
|
|
|
|
|
|
|
|
return err;
|
|
|
|
}
|
|
|
|
|
2009-05-06 21:43:30 +00:00
|
|
|
mmc->scr[0] = __be32_to_cpu(scr[0]);
|
|
|
|
mmc->scr[1] = __be32_to_cpu(scr[1]);
|
2008-10-30 21:41:01 +00:00
|
|
|
|
|
|
|
switch ((mmc->scr[0] >> 24) & 0xf) {
|
|
|
|
case 0:
|
|
|
|
mmc->version = SD_VERSION_1_0;
|
|
|
|
break;
|
|
|
|
case 1:
|
|
|
|
mmc->version = SD_VERSION_1_10;
|
|
|
|
break;
|
|
|
|
case 2:
|
|
|
|
mmc->version = SD_VERSION_2;
|
2013-01-29 22:58:16 +00:00
|
|
|
if ((mmc->scr[0] >> 15) & 0x1)
|
|
|
|
mmc->version = SD_VERSION_3;
|
2008-10-30 21:41:01 +00:00
|
|
|
break;
|
|
|
|
default:
|
|
|
|
mmc->version = SD_VERSION_1_0;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
2010-05-12 09:38:24 +00:00
|
|
|
if (mmc->scr[0] & SD_DATA_4BIT)
|
|
|
|
mmc->card_caps |= MMC_MODE_4BIT;
|
|
|
|
|
2008-10-30 21:41:01 +00:00
|
|
|
/* Version 1.0 doesn't support switching */
|
|
|
|
if (mmc->version == SD_VERSION_1_0)
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
timeout = 4;
|
|
|
|
while (timeout--) {
|
|
|
|
err = sd_switch(mmc, SD_SWITCH_CHECK, 0, 1,
|
2011-10-03 13:54:59 +00:00
|
|
|
(u8 *)switch_status);
|
2008-10-30 21:41:01 +00:00
|
|
|
|
|
|
|
if (err)
|
|
|
|
return err;
|
|
|
|
|
|
|
|
/* The high-speed function is busy. Try again */
|
2009-05-06 21:43:30 +00:00
|
|
|
if (!(__be32_to_cpu(switch_status[7]) & SD_HIGHSPEED_BUSY))
|
2008-10-30 21:41:01 +00:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* If high-speed isn't supported, we return */
|
2009-05-06 21:43:30 +00:00
|
|
|
if (!(__be32_to_cpu(switch_status[3]) & SD_HIGHSPEED_SUPPORTED))
|
2008-10-30 21:41:01 +00:00
|
|
|
return 0;
|
|
|
|
|
2011-11-28 16:31:09 +00:00
|
|
|
/*
|
|
|
|
* If the host doesn't support SD_HIGHSPEED, do not switch card to
|
|
|
|
* HIGHSPEED mode even if the card support SD_HIGHSPPED.
|
|
|
|
* This can avoid furthur problem when the card runs in different
|
|
|
|
* mode between the host.
|
|
|
|
*/
|
2014-03-11 17:34:20 +00:00
|
|
|
if (!((mmc->cfg->host_caps & MMC_MODE_HS_52MHz) &&
|
|
|
|
(mmc->cfg->host_caps & MMC_MODE_HS)))
|
2011-11-28 16:31:09 +00:00
|
|
|
return 0;
|
|
|
|
|
2011-10-03 13:54:59 +00:00
|
|
|
err = sd_switch(mmc, SD_SWITCH_SWITCH, 0, 1, (u8 *)switch_status);
|
2008-10-30 21:41:01 +00:00
|
|
|
|
|
|
|
if (err)
|
|
|
|
return err;
|
|
|
|
|
2009-05-06 21:43:30 +00:00
|
|
|
if ((__be32_to_cpu(switch_status[4]) & 0x0f000000) == 0x01000000)
|
2008-10-30 21:41:01 +00:00
|
|
|
mmc->card_caps |= MMC_MODE_HS;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* frequency bases */
|
|
|
|
/* divided by 10 to be nice to platforms without floating point */
|
2010-10-20 01:15:53 +00:00
|
|
|
static const int fbase[] = {
|
2008-10-30 21:41:01 +00:00
|
|
|
10000,
|
|
|
|
100000,
|
|
|
|
1000000,
|
|
|
|
10000000,
|
|
|
|
};
|
|
|
|
|
|
|
|
/* Multiplier values for TRAN_SPEED. Multiplied by 10 to be nice
|
|
|
|
* to platforms without floating point.
|
|
|
|
*/
|
2010-10-20 01:15:53 +00:00
|
|
|
static const int multipliers[] = {
|
2008-10-30 21:41:01 +00:00
|
|
|
0, /* reserved */
|
|
|
|
10,
|
|
|
|
12,
|
|
|
|
13,
|
|
|
|
15,
|
|
|
|
20,
|
|
|
|
25,
|
|
|
|
30,
|
|
|
|
35,
|
|
|
|
40,
|
|
|
|
45,
|
|
|
|
50,
|
|
|
|
55,
|
|
|
|
60,
|
|
|
|
70,
|
|
|
|
80,
|
|
|
|
};
|
|
|
|
|
2012-10-29 13:34:43 +00:00
|
|
|
static void mmc_set_ios(struct mmc *mmc)
|
2008-10-30 21:41:01 +00:00
|
|
|
{
|
2014-03-11 17:34:20 +00:00
|
|
|
if (mmc->cfg->ops->set_ios)
|
|
|
|
mmc->cfg->ops->set_ios(mmc);
|
2008-10-30 21:41:01 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
void mmc_set_clock(struct mmc *mmc, uint clock)
|
|
|
|
{
|
2014-03-11 17:34:20 +00:00
|
|
|
if (clock > mmc->cfg->f_max)
|
|
|
|
clock = mmc->cfg->f_max;
|
2008-10-30 21:41:01 +00:00
|
|
|
|
2014-03-11 17:34:20 +00:00
|
|
|
if (clock < mmc->cfg->f_min)
|
|
|
|
clock = mmc->cfg->f_min;
|
2008-10-30 21:41:01 +00:00
|
|
|
|
|
|
|
mmc->clock = clock;
|
|
|
|
|
|
|
|
mmc_set_ios(mmc);
|
|
|
|
}
|
|
|
|
|
2012-10-29 13:34:43 +00:00
|
|
|
static void mmc_set_bus_width(struct mmc *mmc, uint width)
|
2008-10-30 21:41:01 +00:00
|
|
|
{
|
|
|
|
mmc->bus_width = width;
|
|
|
|
|
|
|
|
mmc_set_ios(mmc);
|
|
|
|
}
|
|
|
|
|
2012-10-29 13:34:43 +00:00
|
|
|
static int mmc_startup(struct mmc *mmc)
|
2008-10-30 21:41:01 +00:00
|
|
|
{
|
2013-06-11 21:14:01 +00:00
|
|
|
int err, i;
|
2008-10-30 21:41:01 +00:00
|
|
|
uint mult, freq;
|
2011-07-04 22:13:26 +00:00
|
|
|
u64 cmult, csize, capacity;
|
2008-10-30 21:41:01 +00:00
|
|
|
struct mmc_cmd cmd;
|
2013-04-03 08:54:30 +00:00
|
|
|
ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
|
|
|
|
ALLOC_CACHE_ALIGN_BUFFER(u8, test_csd, MMC_MAX_BLOCK_LEN);
|
2011-03-11 02:01:12 +00:00
|
|
|
int timeout = 1000;
|
2008-10-30 21:41:01 +00:00
|
|
|
|
2010-12-24 13:12:21 +00:00
|
|
|
#ifdef CONFIG_MMC_SPI_CRC_ON
|
|
|
|
if (mmc_host_is_spi(mmc)) { /* enable CRC check for spi */
|
|
|
|
cmd.cmdidx = MMC_CMD_SPI_CRC_ON_OFF;
|
|
|
|
cmd.resp_type = MMC_RSP_R1;
|
|
|
|
cmd.cmdarg = 1;
|
|
|
|
err = mmc_send_cmd(mmc, &cmd, NULL);
|
|
|
|
|
|
|
|
if (err)
|
|
|
|
return err;
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
2008-10-30 21:41:01 +00:00
|
|
|
/* Put the Card in Identify Mode */
|
2010-12-24 13:12:21 +00:00
|
|
|
cmd.cmdidx = mmc_host_is_spi(mmc) ? MMC_CMD_SEND_CID :
|
|
|
|
MMC_CMD_ALL_SEND_CID; /* cmd not supported in spi */
|
2008-10-30 21:41:01 +00:00
|
|
|
cmd.resp_type = MMC_RSP_R2;
|
|
|
|
cmd.cmdarg = 0;
|
|
|
|
|
|
|
|
err = mmc_send_cmd(mmc, &cmd, NULL);
|
|
|
|
|
|
|
|
if (err)
|
|
|
|
return err;
|
|
|
|
|
|
|
|
memcpy(mmc->cid, cmd.response, 16);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* For MMC cards, set the Relative Address.
|
|
|
|
* For SD cards, get the Relatvie Address.
|
|
|
|
* This also puts the cards into Standby State
|
|
|
|
*/
|
2010-12-24 13:12:21 +00:00
|
|
|
if (!mmc_host_is_spi(mmc)) { /* cmd not supported in spi */
|
|
|
|
cmd.cmdidx = SD_CMD_SEND_RELATIVE_ADDR;
|
|
|
|
cmd.cmdarg = mmc->rca << 16;
|
|
|
|
cmd.resp_type = MMC_RSP_R6;
|
2008-10-30 21:41:01 +00:00
|
|
|
|
2010-12-24 13:12:21 +00:00
|
|
|
err = mmc_send_cmd(mmc, &cmd, NULL);
|
2008-10-30 21:41:01 +00:00
|
|
|
|
2010-12-24 13:12:21 +00:00
|
|
|
if (err)
|
|
|
|
return err;
|
2008-10-30 21:41:01 +00:00
|
|
|
|
2010-12-24 13:12:21 +00:00
|
|
|
if (IS_SD(mmc))
|
|
|
|
mmc->rca = (cmd.response[0] >> 16) & 0xffff;
|
|
|
|
}
|
2008-10-30 21:41:01 +00:00
|
|
|
|
|
|
|
/* Get the Card-Specific Data */
|
|
|
|
cmd.cmdidx = MMC_CMD_SEND_CSD;
|
|
|
|
cmd.resp_type = MMC_RSP_R2;
|
|
|
|
cmd.cmdarg = mmc->rca << 16;
|
|
|
|
|
|
|
|
err = mmc_send_cmd(mmc, &cmd, NULL);
|
|
|
|
|
2011-03-11 02:01:12 +00:00
|
|
|
/* Waiting for the ready status */
|
|
|
|
mmc_send_status(mmc, timeout);
|
|
|
|
|
2008-10-30 21:41:01 +00:00
|
|
|
if (err)
|
|
|
|
return err;
|
|
|
|
|
2009-04-05 08:00:56 +00:00
|
|
|
mmc->csd[0] = cmd.response[0];
|
|
|
|
mmc->csd[1] = cmd.response[1];
|
|
|
|
mmc->csd[2] = cmd.response[2];
|
|
|
|
mmc->csd[3] = cmd.response[3];
|
2008-10-30 21:41:01 +00:00
|
|
|
|
|
|
|
if (mmc->version == MMC_VERSION_UNKNOWN) {
|
2009-04-05 08:00:55 +00:00
|
|
|
int version = (cmd.response[0] >> 26) & 0xf;
|
2008-10-30 21:41:01 +00:00
|
|
|
|
|
|
|
switch (version) {
|
|
|
|
case 0:
|
|
|
|
mmc->version = MMC_VERSION_1_2;
|
|
|
|
break;
|
|
|
|
case 1:
|
|
|
|
mmc->version = MMC_VERSION_1_4;
|
|
|
|
break;
|
|
|
|
case 2:
|
|
|
|
mmc->version = MMC_VERSION_2_2;
|
|
|
|
break;
|
|
|
|
case 3:
|
|
|
|
mmc->version = MMC_VERSION_3;
|
|
|
|
break;
|
|
|
|
case 4:
|
|
|
|
mmc->version = MMC_VERSION_4;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
mmc->version = MMC_VERSION_1_2;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/* divide frequency by 10, since the mults are 10x bigger */
|
2009-04-05 08:00:55 +00:00
|
|
|
freq = fbase[(cmd.response[0] & 0x7)];
|
|
|
|
mult = multipliers[((cmd.response[0] >> 3) & 0xf)];
|
2008-10-30 21:41:01 +00:00
|
|
|
|
|
|
|
mmc->tran_speed = freq * mult;
|
|
|
|
|
2013-12-16 12:40:46 +00:00
|
|
|
mmc->dsr_imp = ((cmd.response[1] >> 12) & 0x1);
|
2009-04-05 08:00:56 +00:00
|
|
|
mmc->read_bl_len = 1 << ((cmd.response[1] >> 16) & 0xf);
|
2008-10-30 21:41:01 +00:00
|
|
|
|
|
|
|
if (IS_SD(mmc))
|
|
|
|
mmc->write_bl_len = mmc->read_bl_len;
|
|
|
|
else
|
2009-04-05 08:00:56 +00:00
|
|
|
mmc->write_bl_len = 1 << ((cmd.response[3] >> 22) & 0xf);
|
2008-10-30 21:41:01 +00:00
|
|
|
|
|
|
|
if (mmc->high_capacity) {
|
|
|
|
csize = (mmc->csd[1] & 0x3f) << 16
|
|
|
|
| (mmc->csd[2] & 0xffff0000) >> 16;
|
|
|
|
cmult = 8;
|
|
|
|
} else {
|
|
|
|
csize = (mmc->csd[1] & 0x3ff) << 2
|
|
|
|
| (mmc->csd[2] & 0xc0000000) >> 30;
|
|
|
|
cmult = (mmc->csd[2] & 0x00038000) >> 15;
|
|
|
|
}
|
|
|
|
|
2013-06-11 21:14:01 +00:00
|
|
|
mmc->capacity_user = (csize + 1) << (cmult + 2);
|
|
|
|
mmc->capacity_user *= mmc->read_bl_len;
|
|
|
|
mmc->capacity_boot = 0;
|
|
|
|
mmc->capacity_rpmb = 0;
|
|
|
|
for (i = 0; i < 4; i++)
|
|
|
|
mmc->capacity_gp[i] = 0;
|
2008-10-30 21:41:01 +00:00
|
|
|
|
2013-04-03 08:54:30 +00:00
|
|
|
if (mmc->read_bl_len > MMC_MAX_BLOCK_LEN)
|
|
|
|
mmc->read_bl_len = MMC_MAX_BLOCK_LEN;
|
2008-10-30 21:41:01 +00:00
|
|
|
|
2013-04-03 08:54:30 +00:00
|
|
|
if (mmc->write_bl_len > MMC_MAX_BLOCK_LEN)
|
|
|
|
mmc->write_bl_len = MMC_MAX_BLOCK_LEN;
|
2008-10-30 21:41:01 +00:00
|
|
|
|
2013-12-16 12:40:46 +00:00
|
|
|
if ((mmc->dsr_imp) && (0xffffffff != mmc->dsr)) {
|
|
|
|
cmd.cmdidx = MMC_CMD_SET_DSR;
|
|
|
|
cmd.cmdarg = (mmc->dsr & 0xffff) << 16;
|
|
|
|
cmd.resp_type = MMC_RSP_NONE;
|
|
|
|
if (mmc_send_cmd(mmc, &cmd, NULL))
|
|
|
|
printf("MMC: SET_DSR failed\n");
|
|
|
|
}
|
|
|
|
|
2008-10-30 21:41:01 +00:00
|
|
|
/* Select the card, and put it into Transfer Mode */
|
2010-12-24 13:12:21 +00:00
|
|
|
if (!mmc_host_is_spi(mmc)) { /* cmd not supported in spi */
|
|
|
|
cmd.cmdidx = MMC_CMD_SELECT_CARD;
|
2011-10-05 03:13:23 +00:00
|
|
|
cmd.resp_type = MMC_RSP_R1;
|
2010-12-24 13:12:21 +00:00
|
|
|
cmd.cmdarg = mmc->rca << 16;
|
|
|
|
err = mmc_send_cmd(mmc, &cmd, NULL);
|
2008-10-30 21:41:01 +00:00
|
|
|
|
2010-12-24 13:12:21 +00:00
|
|
|
if (err)
|
|
|
|
return err;
|
|
|
|
}
|
2008-10-30 21:41:01 +00:00
|
|
|
|
2011-06-22 17:03:31 +00:00
|
|
|
/*
|
|
|
|
* For SD, its erase group is always one sector
|
|
|
|
*/
|
|
|
|
mmc->erase_grp_size = 1;
|
2011-05-02 16:26:26 +00:00
|
|
|
mmc->part_config = MMCPART_NOAVAILABLE;
|
2010-09-20 12:59:29 +00:00
|
|
|
if (!IS_SD(mmc) && (mmc->version >= MMC_VERSION_4)) {
|
|
|
|
/* check ext_csd version and capacity */
|
|
|
|
err = mmc_send_ext_csd(mmc, ext_csd);
|
2012-10-29 13:34:43 +00:00
|
|
|
if (!err && (ext_csd[EXT_CSD_REV] >= 2)) {
|
2011-07-04 22:13:26 +00:00
|
|
|
/*
|
|
|
|
* According to the JEDEC Standard, the value of
|
|
|
|
* ext_csd's capacity is valid if the value is more
|
|
|
|
* than 2GB
|
|
|
|
*/
|
2011-10-03 20:35:10 +00:00
|
|
|
capacity = ext_csd[EXT_CSD_SEC_CNT] << 0
|
|
|
|
| ext_csd[EXT_CSD_SEC_CNT + 1] << 8
|
|
|
|
| ext_csd[EXT_CSD_SEC_CNT + 2] << 16
|
|
|
|
| ext_csd[EXT_CSD_SEC_CNT + 3] << 24;
|
2013-04-03 08:54:30 +00:00
|
|
|
capacity *= MMC_MAX_BLOCK_LEN;
|
2011-07-05 02:19:44 +00:00
|
|
|
if ((capacity >> 20) > 2 * 1024)
|
2013-06-11 21:14:01 +00:00
|
|
|
mmc->capacity_user = capacity;
|
2010-09-20 12:59:29 +00:00
|
|
|
}
|
2011-05-02 16:26:26 +00:00
|
|
|
|
2013-01-29 19:31:16 +00:00
|
|
|
switch (ext_csd[EXT_CSD_REV]) {
|
|
|
|
case 1:
|
|
|
|
mmc->version = MMC_VERSION_4_1;
|
|
|
|
break;
|
|
|
|
case 2:
|
|
|
|
mmc->version = MMC_VERSION_4_2;
|
|
|
|
break;
|
|
|
|
case 3:
|
|
|
|
mmc->version = MMC_VERSION_4_3;
|
|
|
|
break;
|
|
|
|
case 5:
|
|
|
|
mmc->version = MMC_VERSION_4_41;
|
|
|
|
break;
|
|
|
|
case 6:
|
|
|
|
mmc->version = MMC_VERSION_4_5;
|
|
|
|
break;
|
2014-11-18 14:13:53 +00:00
|
|
|
case 7:
|
|
|
|
mmc->version = MMC_VERSION_5_0;
|
|
|
|
break;
|
2013-01-29 19:31:16 +00:00
|
|
|
}
|
|
|
|
|
2011-06-22 17:03:31 +00:00
|
|
|
/*
|
2013-10-01 18:32:07 +00:00
|
|
|
* Host needs to enable ERASE_GRP_DEF bit if device is
|
|
|
|
* partitioned. This bit will be lost every time after a reset
|
|
|
|
* or power off. This will affect erase size.
|
2011-06-22 17:03:31 +00:00
|
|
|
*/
|
2013-10-01 18:32:07 +00:00
|
|
|
if ((ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & PART_SUPPORT) &&
|
|
|
|
(ext_csd[EXT_CSD_PARTITIONS_ATTRIBUTE] & PART_ENH_ATTRIB)) {
|
|
|
|
err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
|
|
|
|
EXT_CSD_ERASE_GROUP_DEF, 1);
|
|
|
|
|
|
|
|
if (err)
|
|
|
|
return err;
|
2014-08-08 07:47:22 +00:00
|
|
|
else
|
|
|
|
ext_csd[EXT_CSD_ERASE_GROUP_DEF] = 1;
|
2013-10-01 18:32:07 +00:00
|
|
|
|
|
|
|
/* Read out group size from ext_csd */
|
2011-10-03 20:35:10 +00:00
|
|
|
mmc->erase_grp_size =
|
2013-04-03 08:54:30 +00:00
|
|
|
ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] *
|
|
|
|
MMC_MAX_BLOCK_LEN * 1024;
|
2014-11-18 14:11:42 +00:00
|
|
|
/*
|
|
|
|
* if high capacity and partition setting completed
|
|
|
|
* SEC_COUNT is valid even if it is smaller than 2 GiB
|
|
|
|
* JEDEC Standard JESD84-B45, 6.2.4
|
|
|
|
*/
|
|
|
|
if (mmc->high_capacity &&
|
|
|
|
(ext_csd[EXT_CSD_PARTITION_SETTING] &
|
|
|
|
EXT_CSD_PARTITION_SETTING_COMPLETED)) {
|
|
|
|
capacity = (ext_csd[EXT_CSD_SEC_CNT]) |
|
|
|
|
(ext_csd[EXT_CSD_SEC_CNT + 1] << 8) |
|
|
|
|
(ext_csd[EXT_CSD_SEC_CNT + 2] << 16) |
|
|
|
|
(ext_csd[EXT_CSD_SEC_CNT + 3] << 24);
|
|
|
|
capacity *= MMC_MAX_BLOCK_LEN;
|
|
|
|
mmc->capacity_user = capacity;
|
|
|
|
}
|
2013-04-03 08:54:30 +00:00
|
|
|
} else {
|
2013-10-01 18:32:07 +00:00
|
|
|
/* Calculate the group size from the csd value. */
|
2011-06-22 17:03:31 +00:00
|
|
|
int erase_gsz, erase_gmul;
|
|
|
|
erase_gsz = (mmc->csd[2] & 0x00007c00) >> 10;
|
|
|
|
erase_gmul = (mmc->csd[2] & 0x000003e0) >> 5;
|
|
|
|
mmc->erase_grp_size = (erase_gsz + 1)
|
|
|
|
* (erase_gmul + 1);
|
|
|
|
}
|
|
|
|
|
2011-05-02 16:26:26 +00:00
|
|
|
/* store the partition info of emmc */
|
2012-07-30 10:55:43 +00:00
|
|
|
if ((ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & PART_SUPPORT) ||
|
|
|
|
ext_csd[EXT_CSD_BOOT_MULT])
|
2011-10-03 20:35:10 +00:00
|
|
|
mmc->part_config = ext_csd[EXT_CSD_PART_CONF];
|
2013-06-11 21:14:01 +00:00
|
|
|
|
|
|
|
mmc->capacity_boot = ext_csd[EXT_CSD_BOOT_MULT] << 17;
|
|
|
|
|
|
|
|
mmc->capacity_rpmb = ext_csd[EXT_CSD_RPMB_MULT] << 17;
|
|
|
|
|
|
|
|
for (i = 0; i < 4; i++) {
|
|
|
|
int idx = EXT_CSD_GP_SIZE_MULT + i * 3;
|
|
|
|
mmc->capacity_gp[i] = (ext_csd[idx + 2] << 16) +
|
|
|
|
(ext_csd[idx + 1] << 8) + ext_csd[idx];
|
|
|
|
mmc->capacity_gp[i] *=
|
|
|
|
ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE];
|
|
|
|
mmc->capacity_gp[i] *= ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
|
|
|
|
}
|
2010-09-20 12:59:29 +00:00
|
|
|
}
|
|
|
|
|
2013-06-11 21:14:01 +00:00
|
|
|
err = mmc_set_capacity(mmc, mmc->part_num);
|
|
|
|
if (err)
|
|
|
|
return err;
|
|
|
|
|
2008-10-30 21:41:01 +00:00
|
|
|
if (IS_SD(mmc))
|
|
|
|
err = sd_change_freq(mmc);
|
|
|
|
else
|
|
|
|
err = mmc_change_freq(mmc);
|
|
|
|
|
|
|
|
if (err)
|
|
|
|
return err;
|
|
|
|
|
|
|
|
/* Restrict card's capabilities by what the host can do */
|
2014-03-11 17:34:20 +00:00
|
|
|
mmc->card_caps &= mmc->cfg->host_caps;
|
2008-10-30 21:41:01 +00:00
|
|
|
|
|
|
|
if (IS_SD(mmc)) {
|
|
|
|
if (mmc->card_caps & MMC_MODE_4BIT) {
|
|
|
|
cmd.cmdidx = MMC_CMD_APP_CMD;
|
|
|
|
cmd.resp_type = MMC_RSP_R1;
|
|
|
|
cmd.cmdarg = mmc->rca << 16;
|
|
|
|
|
|
|
|
err = mmc_send_cmd(mmc, &cmd, NULL);
|
|
|
|
if (err)
|
|
|
|
return err;
|
|
|
|
|
|
|
|
cmd.cmdidx = SD_CMD_APP_SET_BUS_WIDTH;
|
|
|
|
cmd.resp_type = MMC_RSP_R1;
|
|
|
|
cmd.cmdarg = 2;
|
|
|
|
err = mmc_send_cmd(mmc, &cmd, NULL);
|
|
|
|
if (err)
|
|
|
|
return err;
|
|
|
|
|
|
|
|
mmc_set_bus_width(mmc, 4);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (mmc->card_caps & MMC_MODE_HS)
|
2012-03-26 21:16:03 +00:00
|
|
|
mmc->tran_speed = 50000000;
|
2008-10-30 21:41:01 +00:00
|
|
|
else
|
2012-03-26 21:16:03 +00:00
|
|
|
mmc->tran_speed = 25000000;
|
2008-10-30 21:41:01 +00:00
|
|
|
} else {
|
mmc: Properly determine maximum supported bus width
At some point, a confusion arose about the use of the bit
definitions in host_caps for bus widths, and the value
in ext_csd. By coincidence, a simple shift could convert
between one and the other:
MMC_MODE_1BIT = 0, EXT_CSD_BUS_WIDTH_1 = 0
MMC_MODE_4BIT = 0x100, EXT_CSD_BUS_WIDTH_4 = 1
MMC_MODE_8BIT = 0x200, EXT_CSD_BUS_WIDTH_8 = 2
However, as host_caps is a bitmask of supported things,
there is not, in fact, a one-to-one correspondence. host_caps
is capable of containing MODE_4BIT | MODE_8BIT, so nonsensical
things were happening where we would try to set the bus width
to 12.
The new code clarifies the very different namespaces:
host_caps/card_caps = bitmask (MMC_MODE_*)
ext CSD fields are just an index (EXT_CSD_BUS_WIDTH_*)
mmc->bus_width integer number of bits (1, 4, 8)
We create arrays to map between the namespaces, like in Linux.
Signed-off-by: Andy Fleming <afleming@freescale.com>
Tested-by: Jaehoon Chung <jh80.chung@samsung.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
2012-10-31 19:02:38 +00:00
|
|
|
int idx;
|
|
|
|
|
|
|
|
/* An array of possible bus widths in order of preference */
|
|
|
|
static unsigned ext_csd_bits[] = {
|
2014-05-16 04:59:54 +00:00
|
|
|
EXT_CSD_DDR_BUS_WIDTH_8,
|
|
|
|
EXT_CSD_DDR_BUS_WIDTH_4,
|
mmc: Properly determine maximum supported bus width
At some point, a confusion arose about the use of the bit
definitions in host_caps for bus widths, and the value
in ext_csd. By coincidence, a simple shift could convert
between one and the other:
MMC_MODE_1BIT = 0, EXT_CSD_BUS_WIDTH_1 = 0
MMC_MODE_4BIT = 0x100, EXT_CSD_BUS_WIDTH_4 = 1
MMC_MODE_8BIT = 0x200, EXT_CSD_BUS_WIDTH_8 = 2
However, as host_caps is a bitmask of supported things,
there is not, in fact, a one-to-one correspondence. host_caps
is capable of containing MODE_4BIT | MODE_8BIT, so nonsensical
things were happening where we would try to set the bus width
to 12.
The new code clarifies the very different namespaces:
host_caps/card_caps = bitmask (MMC_MODE_*)
ext CSD fields are just an index (EXT_CSD_BUS_WIDTH_*)
mmc->bus_width integer number of bits (1, 4, 8)
We create arrays to map between the namespaces, like in Linux.
Signed-off-by: Andy Fleming <afleming@freescale.com>
Tested-by: Jaehoon Chung <jh80.chung@samsung.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
2012-10-31 19:02:38 +00:00
|
|
|
EXT_CSD_BUS_WIDTH_8,
|
|
|
|
EXT_CSD_BUS_WIDTH_4,
|
|
|
|
EXT_CSD_BUS_WIDTH_1,
|
|
|
|
};
|
|
|
|
|
|
|
|
/* An array to map CSD bus widths to host cap bits */
|
|
|
|
static unsigned ext_to_hostcaps[] = {
|
mmc: Fix handling of bus widths and DDR card capabilities
If the MMC_MODE_DDR_52MHz flag is set in card capabilities bitmask,
it is never cleared, even if switching to DDR mode fails, and if
the controller driver uses this flag to check the DDR mode, it can
take incorrect actions.
Also, DDR related checks in mmc_startup() incorrectly handle the case
when the host controller does not support some bus widths (e.g. can't
support 8 bits), since the host_caps is checked for DDR bit, but not
bus width bits.
This fix clearly separates using of card_caps bitmask, having there
the flags for the capabilities, that the card can support, and actual
operation mode, described outside of card_caps (i.e. bus_width and
ddr_mode fields in mmc structure). Separate host controller drivers
may need to be updated to use the actual flags. Respectively,
the capabilities checks in mmc_startup are made more correct and clear.
Also, some clean up is made with errors handling and code syntax layout.
Signed-off-by: Andrew Gabbasov <andrew_gabbasov@mentor.com>
2014-12-01 12:59:09 +00:00
|
|
|
[EXT_CSD_DDR_BUS_WIDTH_4] =
|
|
|
|
MMC_MODE_DDR_52MHz | MMC_MODE_4BIT,
|
|
|
|
[EXT_CSD_DDR_BUS_WIDTH_8] =
|
|
|
|
MMC_MODE_DDR_52MHz | MMC_MODE_8BIT,
|
mmc: Properly determine maximum supported bus width
At some point, a confusion arose about the use of the bit
definitions in host_caps for bus widths, and the value
in ext_csd. By coincidence, a simple shift could convert
between one and the other:
MMC_MODE_1BIT = 0, EXT_CSD_BUS_WIDTH_1 = 0
MMC_MODE_4BIT = 0x100, EXT_CSD_BUS_WIDTH_4 = 1
MMC_MODE_8BIT = 0x200, EXT_CSD_BUS_WIDTH_8 = 2
However, as host_caps is a bitmask of supported things,
there is not, in fact, a one-to-one correspondence. host_caps
is capable of containing MODE_4BIT | MODE_8BIT, so nonsensical
things were happening where we would try to set the bus width
to 12.
The new code clarifies the very different namespaces:
host_caps/card_caps = bitmask (MMC_MODE_*)
ext CSD fields are just an index (EXT_CSD_BUS_WIDTH_*)
mmc->bus_width integer number of bits (1, 4, 8)
We create arrays to map between the namespaces, like in Linux.
Signed-off-by: Andy Fleming <afleming@freescale.com>
Tested-by: Jaehoon Chung <jh80.chung@samsung.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
2012-10-31 19:02:38 +00:00
|
|
|
[EXT_CSD_BUS_WIDTH_4] = MMC_MODE_4BIT,
|
|
|
|
[EXT_CSD_BUS_WIDTH_8] = MMC_MODE_8BIT,
|
|
|
|
};
|
|
|
|
|
|
|
|
/* An array to map chosen bus width to an integer */
|
|
|
|
static unsigned widths[] = {
|
2014-05-16 04:59:54 +00:00
|
|
|
8, 4, 8, 4, 1,
|
mmc: Properly determine maximum supported bus width
At some point, a confusion arose about the use of the bit
definitions in host_caps for bus widths, and the value
in ext_csd. By coincidence, a simple shift could convert
between one and the other:
MMC_MODE_1BIT = 0, EXT_CSD_BUS_WIDTH_1 = 0
MMC_MODE_4BIT = 0x100, EXT_CSD_BUS_WIDTH_4 = 1
MMC_MODE_8BIT = 0x200, EXT_CSD_BUS_WIDTH_8 = 2
However, as host_caps is a bitmask of supported things,
there is not, in fact, a one-to-one correspondence. host_caps
is capable of containing MODE_4BIT | MODE_8BIT, so nonsensical
things were happening where we would try to set the bus width
to 12.
The new code clarifies the very different namespaces:
host_caps/card_caps = bitmask (MMC_MODE_*)
ext CSD fields are just an index (EXT_CSD_BUS_WIDTH_*)
mmc->bus_width integer number of bits (1, 4, 8)
We create arrays to map between the namespaces, like in Linux.
Signed-off-by: Andy Fleming <afleming@freescale.com>
Tested-by: Jaehoon Chung <jh80.chung@samsung.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
2012-10-31 19:02:38 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
for (idx=0; idx < ARRAY_SIZE(ext_csd_bits); idx++) {
|
|
|
|
unsigned int extw = ext_csd_bits[idx];
|
mmc: Fix handling of bus widths and DDR card capabilities
If the MMC_MODE_DDR_52MHz flag is set in card capabilities bitmask,
it is never cleared, even if switching to DDR mode fails, and if
the controller driver uses this flag to check the DDR mode, it can
take incorrect actions.
Also, DDR related checks in mmc_startup() incorrectly handle the case
when the host controller does not support some bus widths (e.g. can't
support 8 bits), since the host_caps is checked for DDR bit, but not
bus width bits.
This fix clearly separates using of card_caps bitmask, having there
the flags for the capabilities, that the card can support, and actual
operation mode, described outside of card_caps (i.e. bus_width and
ddr_mode fields in mmc structure). Separate host controller drivers
may need to be updated to use the actual flags. Respectively,
the capabilities checks in mmc_startup are made more correct and clear.
Also, some clean up is made with errors handling and code syntax layout.
Signed-off-by: Andrew Gabbasov <andrew_gabbasov@mentor.com>
2014-12-01 12:59:09 +00:00
|
|
|
unsigned int caps = ext_to_hostcaps[extw];
|
mmc: Properly determine maximum supported bus width
At some point, a confusion arose about the use of the bit
definitions in host_caps for bus widths, and the value
in ext_csd. By coincidence, a simple shift could convert
between one and the other:
MMC_MODE_1BIT = 0, EXT_CSD_BUS_WIDTH_1 = 0
MMC_MODE_4BIT = 0x100, EXT_CSD_BUS_WIDTH_4 = 1
MMC_MODE_8BIT = 0x200, EXT_CSD_BUS_WIDTH_8 = 2
However, as host_caps is a bitmask of supported things,
there is not, in fact, a one-to-one correspondence. host_caps
is capable of containing MODE_4BIT | MODE_8BIT, so nonsensical
things were happening where we would try to set the bus width
to 12.
The new code clarifies the very different namespaces:
host_caps/card_caps = bitmask (MMC_MODE_*)
ext CSD fields are just an index (EXT_CSD_BUS_WIDTH_*)
mmc->bus_width integer number of bits (1, 4, 8)
We create arrays to map between the namespaces, like in Linux.
Signed-off-by: Andy Fleming <afleming@freescale.com>
Tested-by: Jaehoon Chung <jh80.chung@samsung.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
2012-10-31 19:02:38 +00:00
|
|
|
|
|
|
|
/*
|
mmc: Fix handling of bus widths and DDR card capabilities
If the MMC_MODE_DDR_52MHz flag is set in card capabilities bitmask,
it is never cleared, even if switching to DDR mode fails, and if
the controller driver uses this flag to check the DDR mode, it can
take incorrect actions.
Also, DDR related checks in mmc_startup() incorrectly handle the case
when the host controller does not support some bus widths (e.g. can't
support 8 bits), since the host_caps is checked for DDR bit, but not
bus width bits.
This fix clearly separates using of card_caps bitmask, having there
the flags for the capabilities, that the card can support, and actual
operation mode, described outside of card_caps (i.e. bus_width and
ddr_mode fields in mmc structure). Separate host controller drivers
may need to be updated to use the actual flags. Respectively,
the capabilities checks in mmc_startup are made more correct and clear.
Also, some clean up is made with errors handling and code syntax layout.
Signed-off-by: Andrew Gabbasov <andrew_gabbasov@mentor.com>
2014-12-01 12:59:09 +00:00
|
|
|
* Check to make sure the card and controller support
|
|
|
|
* these capabilities
|
mmc: Properly determine maximum supported bus width
At some point, a confusion arose about the use of the bit
definitions in host_caps for bus widths, and the value
in ext_csd. By coincidence, a simple shift could convert
between one and the other:
MMC_MODE_1BIT = 0, EXT_CSD_BUS_WIDTH_1 = 0
MMC_MODE_4BIT = 0x100, EXT_CSD_BUS_WIDTH_4 = 1
MMC_MODE_8BIT = 0x200, EXT_CSD_BUS_WIDTH_8 = 2
However, as host_caps is a bitmask of supported things,
there is not, in fact, a one-to-one correspondence. host_caps
is capable of containing MODE_4BIT | MODE_8BIT, so nonsensical
things were happening where we would try to set the bus width
to 12.
The new code clarifies the very different namespaces:
host_caps/card_caps = bitmask (MMC_MODE_*)
ext CSD fields are just an index (EXT_CSD_BUS_WIDTH_*)
mmc->bus_width integer number of bits (1, 4, 8)
We create arrays to map between the namespaces, like in Linux.
Signed-off-by: Andy Fleming <afleming@freescale.com>
Tested-by: Jaehoon Chung <jh80.chung@samsung.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
2012-10-31 19:02:38 +00:00
|
|
|
*/
|
mmc: Fix handling of bus widths and DDR card capabilities
If the MMC_MODE_DDR_52MHz flag is set in card capabilities bitmask,
it is never cleared, even if switching to DDR mode fails, and if
the controller driver uses this flag to check the DDR mode, it can
take incorrect actions.
Also, DDR related checks in mmc_startup() incorrectly handle the case
when the host controller does not support some bus widths (e.g. can't
support 8 bits), since the host_caps is checked for DDR bit, but not
bus width bits.
This fix clearly separates using of card_caps bitmask, having there
the flags for the capabilities, that the card can support, and actual
operation mode, described outside of card_caps (i.e. bus_width and
ddr_mode fields in mmc structure). Separate host controller drivers
may need to be updated to use the actual flags. Respectively,
the capabilities checks in mmc_startup are made more correct and clear.
Also, some clean up is made with errors handling and code syntax layout.
Signed-off-by: Andrew Gabbasov <andrew_gabbasov@mentor.com>
2014-12-01 12:59:09 +00:00
|
|
|
if ((mmc->card_caps & caps) != caps)
|
mmc: Properly determine maximum supported bus width
At some point, a confusion arose about the use of the bit
definitions in host_caps for bus widths, and the value
in ext_csd. By coincidence, a simple shift could convert
between one and the other:
MMC_MODE_1BIT = 0, EXT_CSD_BUS_WIDTH_1 = 0
MMC_MODE_4BIT = 0x100, EXT_CSD_BUS_WIDTH_4 = 1
MMC_MODE_8BIT = 0x200, EXT_CSD_BUS_WIDTH_8 = 2
However, as host_caps is a bitmask of supported things,
there is not, in fact, a one-to-one correspondence. host_caps
is capable of containing MODE_4BIT | MODE_8BIT, so nonsensical
things were happening where we would try to set the bus width
to 12.
The new code clarifies the very different namespaces:
host_caps/card_caps = bitmask (MMC_MODE_*)
ext CSD fields are just an index (EXT_CSD_BUS_WIDTH_*)
mmc->bus_width integer number of bits (1, 4, 8)
We create arrays to map between the namespaces, like in Linux.
Signed-off-by: Andy Fleming <afleming@freescale.com>
Tested-by: Jaehoon Chung <jh80.chung@samsung.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
2012-10-31 19:02:38 +00:00
|
|
|
continue;
|
|
|
|
|
2008-10-30 21:41:01 +00:00
|
|
|
err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
|
mmc: Properly determine maximum supported bus width
At some point, a confusion arose about the use of the bit
definitions in host_caps for bus widths, and the value
in ext_csd. By coincidence, a simple shift could convert
between one and the other:
MMC_MODE_1BIT = 0, EXT_CSD_BUS_WIDTH_1 = 0
MMC_MODE_4BIT = 0x100, EXT_CSD_BUS_WIDTH_4 = 1
MMC_MODE_8BIT = 0x200, EXT_CSD_BUS_WIDTH_8 = 2
However, as host_caps is a bitmask of supported things,
there is not, in fact, a one-to-one correspondence. host_caps
is capable of containing MODE_4BIT | MODE_8BIT, so nonsensical
things were happening where we would try to set the bus width
to 12.
The new code clarifies the very different namespaces:
host_caps/card_caps = bitmask (MMC_MODE_*)
ext CSD fields are just an index (EXT_CSD_BUS_WIDTH_*)
mmc->bus_width integer number of bits (1, 4, 8)
We create arrays to map between the namespaces, like in Linux.
Signed-off-by: Andy Fleming <afleming@freescale.com>
Tested-by: Jaehoon Chung <jh80.chung@samsung.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
2012-10-31 19:02:38 +00:00
|
|
|
EXT_CSD_BUS_WIDTH, extw);
|
2008-10-30 21:41:01 +00:00
|
|
|
|
|
|
|
if (err)
|
2011-10-03 20:35:11 +00:00
|
|
|
continue;
|
2008-10-30 21:41:01 +00:00
|
|
|
|
mmc: Fix handling of bus widths and DDR card capabilities
If the MMC_MODE_DDR_52MHz flag is set in card capabilities bitmask,
it is never cleared, even if switching to DDR mode fails, and if
the controller driver uses this flag to check the DDR mode, it can
take incorrect actions.
Also, DDR related checks in mmc_startup() incorrectly handle the case
when the host controller does not support some bus widths (e.g. can't
support 8 bits), since the host_caps is checked for DDR bit, but not
bus width bits.
This fix clearly separates using of card_caps bitmask, having there
the flags for the capabilities, that the card can support, and actual
operation mode, described outside of card_caps (i.e. bus_width and
ddr_mode fields in mmc structure). Separate host controller drivers
may need to be updated to use the actual flags. Respectively,
the capabilities checks in mmc_startup are made more correct and clear.
Also, some clean up is made with errors handling and code syntax layout.
Signed-off-by: Andrew Gabbasov <andrew_gabbasov@mentor.com>
2014-12-01 12:59:09 +00:00
|
|
|
mmc->ddr_mode = (caps & MMC_MODE_DDR_52MHz) ? 1 : 0;
|
mmc: Properly determine maximum supported bus width
At some point, a confusion arose about the use of the bit
definitions in host_caps for bus widths, and the value
in ext_csd. By coincidence, a simple shift could convert
between one and the other:
MMC_MODE_1BIT = 0, EXT_CSD_BUS_WIDTH_1 = 0
MMC_MODE_4BIT = 0x100, EXT_CSD_BUS_WIDTH_4 = 1
MMC_MODE_8BIT = 0x200, EXT_CSD_BUS_WIDTH_8 = 2
However, as host_caps is a bitmask of supported things,
there is not, in fact, a one-to-one correspondence. host_caps
is capable of containing MODE_4BIT | MODE_8BIT, so nonsensical
things were happening where we would try to set the bus width
to 12.
The new code clarifies the very different namespaces:
host_caps/card_caps = bitmask (MMC_MODE_*)
ext CSD fields are just an index (EXT_CSD_BUS_WIDTH_*)
mmc->bus_width integer number of bits (1, 4, 8)
We create arrays to map between the namespaces, like in Linux.
Signed-off-by: Andy Fleming <afleming@freescale.com>
Tested-by: Jaehoon Chung <jh80.chung@samsung.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
2012-10-31 19:02:38 +00:00
|
|
|
mmc_set_bus_width(mmc, widths[idx]);
|
2011-10-03 20:35:11 +00:00
|
|
|
|
|
|
|
err = mmc_send_ext_csd(mmc, test_csd);
|
mmc: Fix handling of bus widths and DDR card capabilities
If the MMC_MODE_DDR_52MHz flag is set in card capabilities bitmask,
it is never cleared, even if switching to DDR mode fails, and if
the controller driver uses this flag to check the DDR mode, it can
take incorrect actions.
Also, DDR related checks in mmc_startup() incorrectly handle the case
when the host controller does not support some bus widths (e.g. can't
support 8 bits), since the host_caps is checked for DDR bit, but not
bus width bits.
This fix clearly separates using of card_caps bitmask, having there
the flags for the capabilities, that the card can support, and actual
operation mode, described outside of card_caps (i.e. bus_width and
ddr_mode fields in mmc structure). Separate host controller drivers
may need to be updated to use the actual flags. Respectively,
the capabilities checks in mmc_startup are made more correct and clear.
Also, some clean up is made with errors handling and code syntax layout.
Signed-off-by: Andrew Gabbasov <andrew_gabbasov@mentor.com>
2014-12-01 12:59:09 +00:00
|
|
|
|
|
|
|
if (err)
|
|
|
|
continue;
|
|
|
|
|
2014-09-30 15:04:42 +00:00
|
|
|
/* Only compare read only fields */
|
mmc: Fix handling of bus widths and DDR card capabilities
If the MMC_MODE_DDR_52MHz flag is set in card capabilities bitmask,
it is never cleared, even if switching to DDR mode fails, and if
the controller driver uses this flag to check the DDR mode, it can
take incorrect actions.
Also, DDR related checks in mmc_startup() incorrectly handle the case
when the host controller does not support some bus widths (e.g. can't
support 8 bits), since the host_caps is checked for DDR bit, but not
bus width bits.
This fix clearly separates using of card_caps bitmask, having there
the flags for the capabilities, that the card can support, and actual
operation mode, described outside of card_caps (i.e. bus_width and
ddr_mode fields in mmc structure). Separate host controller drivers
may need to be updated to use the actual flags. Respectively,
the capabilities checks in mmc_startup are made more correct and clear.
Also, some clean up is made with errors handling and code syntax layout.
Signed-off-by: Andrew Gabbasov <andrew_gabbasov@mentor.com>
2014-12-01 12:59:09 +00:00
|
|
|
if (ext_csd[EXT_CSD_PARTITIONING_SUPPORT]
|
|
|
|
== test_csd[EXT_CSD_PARTITIONING_SUPPORT] &&
|
|
|
|
ext_csd[EXT_CSD_HC_WP_GRP_SIZE]
|
|
|
|
== test_csd[EXT_CSD_HC_WP_GRP_SIZE] &&
|
|
|
|
ext_csd[EXT_CSD_REV]
|
|
|
|
== test_csd[EXT_CSD_REV] &&
|
|
|
|
ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE]
|
|
|
|
== test_csd[EXT_CSD_HC_ERASE_GRP_SIZE] &&
|
|
|
|
memcmp(&ext_csd[EXT_CSD_SEC_CNT],
|
|
|
|
&test_csd[EXT_CSD_SEC_CNT], 4) == 0)
|
2011-10-03 20:35:11 +00:00
|
|
|
break;
|
mmc: Fix handling of bus widths and DDR card capabilities
If the MMC_MODE_DDR_52MHz flag is set in card capabilities bitmask,
it is never cleared, even if switching to DDR mode fails, and if
the controller driver uses this flag to check the DDR mode, it can
take incorrect actions.
Also, DDR related checks in mmc_startup() incorrectly handle the case
when the host controller does not support some bus widths (e.g. can't
support 8 bits), since the host_caps is checked for DDR bit, but not
bus width bits.
This fix clearly separates using of card_caps bitmask, having there
the flags for the capabilities, that the card can support, and actual
operation mode, described outside of card_caps (i.e. bus_width and
ddr_mode fields in mmc structure). Separate host controller drivers
may need to be updated to use the actual flags. Respectively,
the capabilities checks in mmc_startup are made more correct and clear.
Also, some clean up is made with errors handling and code syntax layout.
Signed-off-by: Andrew Gabbasov <andrew_gabbasov@mentor.com>
2014-12-01 12:59:09 +00:00
|
|
|
else
|
|
|
|
err = SWITCH_ERR;
|
2008-10-30 21:41:01 +00:00
|
|
|
}
|
|
|
|
|
mmc: Fix handling of bus widths and DDR card capabilities
If the MMC_MODE_DDR_52MHz flag is set in card capabilities bitmask,
it is never cleared, even if switching to DDR mode fails, and if
the controller driver uses this flag to check the DDR mode, it can
take incorrect actions.
Also, DDR related checks in mmc_startup() incorrectly handle the case
when the host controller does not support some bus widths (e.g. can't
support 8 bits), since the host_caps is checked for DDR bit, but not
bus width bits.
This fix clearly separates using of card_caps bitmask, having there
the flags for the capabilities, that the card can support, and actual
operation mode, described outside of card_caps (i.e. bus_width and
ddr_mode fields in mmc structure). Separate host controller drivers
may need to be updated to use the actual flags. Respectively,
the capabilities checks in mmc_startup are made more correct and clear.
Also, some clean up is made with errors handling and code syntax layout.
Signed-off-by: Andrew Gabbasov <andrew_gabbasov@mentor.com>
2014-12-01 12:59:09 +00:00
|
|
|
if (err)
|
|
|
|
return err;
|
|
|
|
|
2008-10-30 21:41:01 +00:00
|
|
|
if (mmc->card_caps & MMC_MODE_HS) {
|
|
|
|
if (mmc->card_caps & MMC_MODE_HS_52MHz)
|
2012-03-26 21:16:03 +00:00
|
|
|
mmc->tran_speed = 52000000;
|
2008-10-30 21:41:01 +00:00
|
|
|
else
|
2012-03-26 21:16:03 +00:00
|
|
|
mmc->tran_speed = 26000000;
|
|
|
|
}
|
2008-10-30 21:41:01 +00:00
|
|
|
}
|
|
|
|
|
2012-03-26 21:16:03 +00:00
|
|
|
mmc_set_clock(mmc, mmc->tran_speed);
|
|
|
|
|
2014-12-01 12:59:11 +00:00
|
|
|
/* Fix the block length for DDR mode */
|
|
|
|
if (mmc->ddr_mode) {
|
|
|
|
mmc->read_bl_len = MMC_MAX_BLOCK_LEN;
|
|
|
|
mmc->write_bl_len = MMC_MAX_BLOCK_LEN;
|
|
|
|
}
|
|
|
|
|
2008-10-30 21:41:01 +00:00
|
|
|
/* fill in device description */
|
|
|
|
mmc->block_dev.lun = 0;
|
|
|
|
mmc->block_dev.type = 0;
|
|
|
|
mmc->block_dev.blksz = mmc->read_bl_len;
|
2013-04-09 21:11:56 +00:00
|
|
|
mmc->block_dev.log2blksz = LOG2(mmc->block_dev.blksz);
|
2009-04-05 08:00:54 +00:00
|
|
|
mmc->block_dev.lba = lldiv(mmc->capacity, mmc->read_bl_len);
|
2013-09-04 15:12:25 +00:00
|
|
|
#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
|
2012-10-20 17:15:59 +00:00
|
|
|
sprintf(mmc->block_dev.vendor, "Man %06x Snr %04x%04x",
|
|
|
|
mmc->cid[0] >> 24, (mmc->cid[2] & 0xffff),
|
|
|
|
(mmc->cid[3] >> 16) & 0xffff);
|
|
|
|
sprintf(mmc->block_dev.product, "%c%c%c%c%c%c", mmc->cid[0] & 0xff,
|
|
|
|
(mmc->cid[1] >> 24), (mmc->cid[1] >> 16) & 0xff,
|
|
|
|
(mmc->cid[1] >> 8) & 0xff, mmc->cid[1] & 0xff,
|
|
|
|
(mmc->cid[2] >> 24) & 0xff);
|
|
|
|
sprintf(mmc->block_dev.revision, "%d.%d", (mmc->cid[2] >> 20) & 0xf,
|
|
|
|
(mmc->cid[2] >> 16) & 0xf);
|
2013-09-04 15:12:25 +00:00
|
|
|
#else
|
|
|
|
mmc->block_dev.vendor[0] = 0;
|
|
|
|
mmc->block_dev.product[0] = 0;
|
|
|
|
mmc->block_dev.revision[0] = 0;
|
|
|
|
#endif
|
2012-07-09 08:53:38 +00:00
|
|
|
#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBDISK_SUPPORT)
|
2008-10-30 21:41:01 +00:00
|
|
|
init_part(&mmc->block_dev);
|
2012-07-09 08:53:38 +00:00
|
|
|
#endif
|
2008-10-30 21:41:01 +00:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2012-10-29 13:34:43 +00:00
|
|
|
static int mmc_send_if_cond(struct mmc *mmc)
|
2008-10-30 21:41:01 +00:00
|
|
|
{
|
|
|
|
struct mmc_cmd cmd;
|
|
|
|
int err;
|
|
|
|
|
|
|
|
cmd.cmdidx = SD_CMD_SEND_IF_COND;
|
|
|
|
/* We set the bit if the host supports voltages between 2.7 and 3.6 V */
|
2014-03-11 17:34:20 +00:00
|
|
|
cmd.cmdarg = ((mmc->cfg->voltages & 0xff8000) != 0) << 8 | 0xaa;
|
2008-10-30 21:41:01 +00:00
|
|
|
cmd.resp_type = MMC_RSP_R7;
|
|
|
|
|
|
|
|
err = mmc_send_cmd(mmc, &cmd, NULL);
|
|
|
|
|
|
|
|
if (err)
|
|
|
|
return err;
|
|
|
|
|
2009-04-05 08:00:56 +00:00
|
|
|
if ((cmd.response[0] & 0xff) != 0xaa)
|
2008-10-30 21:41:01 +00:00
|
|
|
return UNUSABLE_ERR;
|
|
|
|
else
|
|
|
|
mmc->version = SD_VERSION_2;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2014-03-11 17:34:20 +00:00
|
|
|
/* not used any more */
|
|
|
|
int __deprecated mmc_register(struct mmc *mmc)
|
|
|
|
{
|
|
|
|
#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
|
|
|
|
printf("%s is deprecated! use mmc_create() instead.\n", __func__);
|
|
|
|
#endif
|
|
|
|
return -1;
|
|
|
|
}
|
|
|
|
|
|
|
|
struct mmc *mmc_create(const struct mmc_config *cfg, void *priv)
|
2008-10-30 21:41:01 +00:00
|
|
|
{
|
2014-03-11 17:34:20 +00:00
|
|
|
struct mmc *mmc;
|
|
|
|
|
|
|
|
/* quick validation */
|
|
|
|
if (cfg == NULL || cfg->ops == NULL || cfg->ops->send_cmd == NULL ||
|
|
|
|
cfg->f_min == 0 || cfg->f_max == 0 || cfg->b_max == 0)
|
|
|
|
return NULL;
|
|
|
|
|
|
|
|
mmc = calloc(1, sizeof(*mmc));
|
|
|
|
if (mmc == NULL)
|
|
|
|
return NULL;
|
|
|
|
|
|
|
|
mmc->cfg = cfg;
|
|
|
|
mmc->priv = priv;
|
|
|
|
|
|
|
|
/* the following chunk was mmc_register() */
|
|
|
|
|
2013-12-16 12:40:46 +00:00
|
|
|
/* Setup dsr related values */
|
|
|
|
mmc->dsr_imp = 0;
|
|
|
|
mmc->dsr = 0xffffffff;
|
2008-10-30 21:41:01 +00:00
|
|
|
/* Setup the universal parts of the block interface just once */
|
|
|
|
mmc->block_dev.if_type = IF_TYPE_MMC;
|
|
|
|
mmc->block_dev.dev = cur_dev_num++;
|
|
|
|
mmc->block_dev.removable = 1;
|
|
|
|
mmc->block_dev.block_read = mmc_bread;
|
|
|
|
mmc->block_dev.block_write = mmc_bwrite;
|
2011-06-22 17:03:31 +00:00
|
|
|
mmc->block_dev.block_erase = mmc_berase;
|
2008-10-30 21:41:01 +00:00
|
|
|
|
2014-03-11 17:34:20 +00:00
|
|
|
/* setup initial part type */
|
|
|
|
mmc->block_dev.part_type = mmc->cfg->part_type;
|
2008-10-30 21:41:01 +00:00
|
|
|
|
2014-03-11 17:34:20 +00:00
|
|
|
INIT_LIST_HEAD(&mmc->link);
|
2008-10-30 21:41:01 +00:00
|
|
|
|
2014-03-11 17:34:20 +00:00
|
|
|
list_add_tail(&mmc->link, &mmc_devices);
|
|
|
|
|
|
|
|
return mmc;
|
|
|
|
}
|
|
|
|
|
|
|
|
void mmc_destroy(struct mmc *mmc)
|
|
|
|
{
|
|
|
|
/* only freeing memory for now */
|
|
|
|
free(mmc);
|
2008-10-30 21:41:01 +00:00
|
|
|
}
|
|
|
|
|
2011-05-24 05:31:19 +00:00
|
|
|
#ifdef CONFIG_PARTITIONS
|
2008-10-30 21:41:01 +00:00
|
|
|
block_dev_desc_t *mmc_get_dev(int dev)
|
|
|
|
{
|
|
|
|
struct mmc *mmc = find_mmc_device(dev);
|
2012-08-10 08:59:12 +00:00
|
|
|
if (!mmc || mmc_init(mmc))
|
2012-04-19 02:39:18 +00:00
|
|
|
return NULL;
|
2008-10-30 21:41:01 +00:00
|
|
|
|
2012-04-19 02:39:18 +00:00
|
|
|
return &mmc->block_dev;
|
2008-10-30 21:41:01 +00:00
|
|
|
}
|
2011-05-24 05:31:19 +00:00
|
|
|
#endif
|
2008-10-30 21:41:01 +00:00
|
|
|
|
2014-11-08 19:55:45 +00:00
|
|
|
/* board-specific MMC power initializations. */
|
|
|
|
__weak void board_mmc_power_init(void)
|
|
|
|
{
|
|
|
|
}
|
|
|
|
|
2012-11-28 15:21:13 +00:00
|
|
|
int mmc_start_init(struct mmc *mmc)
|
2008-10-30 21:41:01 +00:00
|
|
|
{
|
2011-11-14 23:35:39 +00:00
|
|
|
int err;
|
2008-10-30 21:41:01 +00:00
|
|
|
|
2014-02-26 17:28:45 +00:00
|
|
|
/* we pretend there's no card when init is NULL */
|
2014-03-11 17:34:20 +00:00
|
|
|
if (mmc_getcd(mmc) == 0 || mmc->cfg->ops->init == NULL) {
|
2012-01-02 01:15:37 +00:00
|
|
|
mmc->has_init = 0;
|
2013-09-04 15:12:25 +00:00
|
|
|
#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
|
2012-01-02 01:15:37 +00:00
|
|
|
printf("MMC: no card present\n");
|
2013-09-04 15:12:25 +00:00
|
|
|
#endif
|
2012-01-02 01:15:37 +00:00
|
|
|
return NO_CARD_ERR;
|
|
|
|
}
|
|
|
|
|
2011-05-02 16:26:26 +00:00
|
|
|
if (mmc->has_init)
|
|
|
|
return 0;
|
|
|
|
|
2014-11-08 19:55:45 +00:00
|
|
|
board_mmc_power_init();
|
|
|
|
|
2014-02-26 17:28:45 +00:00
|
|
|
/* made sure it's not NULL earlier */
|
2014-03-11 17:34:20 +00:00
|
|
|
err = mmc->cfg->ops->init(mmc);
|
2008-10-30 21:41:01 +00:00
|
|
|
|
|
|
|
if (err)
|
|
|
|
return err;
|
|
|
|
|
mmc: Fix handling of bus widths and DDR card capabilities
If the MMC_MODE_DDR_52MHz flag is set in card capabilities bitmask,
it is never cleared, even if switching to DDR mode fails, and if
the controller driver uses this flag to check the DDR mode, it can
take incorrect actions.
Also, DDR related checks in mmc_startup() incorrectly handle the case
when the host controller does not support some bus widths (e.g. can't
support 8 bits), since the host_caps is checked for DDR bit, but not
bus width bits.
This fix clearly separates using of card_caps bitmask, having there
the flags for the capabilities, that the card can support, and actual
operation mode, described outside of card_caps (i.e. bus_width and
ddr_mode fields in mmc structure). Separate host controller drivers
may need to be updated to use the actual flags. Respectively,
the capabilities checks in mmc_startup are made more correct and clear.
Also, some clean up is made with errors handling and code syntax layout.
Signed-off-by: Andrew Gabbasov <andrew_gabbasov@mentor.com>
2014-12-01 12:59:09 +00:00
|
|
|
mmc->ddr_mode = 0;
|
2009-06-29 13:53:16 +00:00
|
|
|
mmc_set_bus_width(mmc, 1);
|
|
|
|
mmc_set_clock(mmc, 1);
|
|
|
|
|
2008-10-30 21:41:01 +00:00
|
|
|
/* Reset the Card */
|
|
|
|
err = mmc_go_idle(mmc);
|
|
|
|
|
|
|
|
if (err)
|
|
|
|
return err;
|
|
|
|
|
2011-05-02 16:26:26 +00:00
|
|
|
/* The internal partition reset to user partition(0) at every CMD0*/
|
|
|
|
mmc->part_num = 0;
|
|
|
|
|
2008-10-30 21:41:01 +00:00
|
|
|
/* Test for SD version 2 */
|
2011-11-14 23:35:39 +00:00
|
|
|
err = mmc_send_if_cond(mmc);
|
2008-10-30 21:41:01 +00:00
|
|
|
|
|
|
|
/* Now try to get the SD card's operating condition */
|
|
|
|
err = sd_send_op_cond(mmc);
|
|
|
|
|
|
|
|
/* If the command timed out, we check for an MMC card */
|
|
|
|
if (err == TIMEOUT) {
|
|
|
|
err = mmc_send_op_cond(mmc);
|
|
|
|
|
2012-11-28 15:21:13 +00:00
|
|
|
if (err && err != IN_PROGRESS) {
|
2013-09-04 15:12:25 +00:00
|
|
|
#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
|
2008-10-30 21:41:01 +00:00
|
|
|
printf("Card did not respond to voltage select!\n");
|
2013-09-04 15:12:25 +00:00
|
|
|
#endif
|
2008-10-30 21:41:01 +00:00
|
|
|
return UNUSABLE_ERR;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2012-11-28 15:21:13 +00:00
|
|
|
if (err == IN_PROGRESS)
|
|
|
|
mmc->init_in_progress = 1;
|
|
|
|
|
|
|
|
return err;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int mmc_complete_init(struct mmc *mmc)
|
|
|
|
{
|
|
|
|
int err = 0;
|
|
|
|
|
|
|
|
if (mmc->op_cond_pending)
|
|
|
|
err = mmc_complete_op_cond(mmc);
|
|
|
|
|
|
|
|
if (!err)
|
|
|
|
err = mmc_startup(mmc);
|
2011-05-02 16:26:26 +00:00
|
|
|
if (err)
|
|
|
|
mmc->has_init = 0;
|
|
|
|
else
|
|
|
|
mmc->has_init = 1;
|
2012-11-28 15:21:13 +00:00
|
|
|
mmc->init_in_progress = 0;
|
|
|
|
return err;
|
|
|
|
}
|
|
|
|
|
|
|
|
int mmc_init(struct mmc *mmc)
|
|
|
|
{
|
|
|
|
int err = IN_PROGRESS;
|
2014-04-29 18:15:30 +00:00
|
|
|
unsigned start;
|
2012-11-28 15:21:13 +00:00
|
|
|
|
|
|
|
if (mmc->has_init)
|
|
|
|
return 0;
|
2014-04-29 18:15:30 +00:00
|
|
|
|
|
|
|
start = get_timer(0);
|
|
|
|
|
2012-11-28 15:21:13 +00:00
|
|
|
if (!mmc->init_in_progress)
|
|
|
|
err = mmc_start_init(mmc);
|
|
|
|
|
|
|
|
if (!err || err == IN_PROGRESS)
|
|
|
|
err = mmc_complete_init(mmc);
|
|
|
|
debug("%s: %d, time %lu\n", __func__, err, get_timer(start));
|
2011-05-02 16:26:26 +00:00
|
|
|
return err;
|
2008-10-30 21:41:01 +00:00
|
|
|
}
|
|
|
|
|
2013-12-16 12:40:46 +00:00
|
|
|
int mmc_set_dsr(struct mmc *mmc, u16 val)
|
|
|
|
{
|
|
|
|
mmc->dsr = val;
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2014-07-10 20:46:28 +00:00
|
|
|
/* CPU-specific MMC initializations */
|
|
|
|
__weak int cpu_mmc_init(bd_t *bis)
|
2008-10-30 21:41:01 +00:00
|
|
|
{
|
|
|
|
return -1;
|
|
|
|
}
|
|
|
|
|
2014-07-10 20:46:28 +00:00
|
|
|
/* board-specific MMC initializations. */
|
|
|
|
__weak int board_mmc_init(bd_t *bis)
|
|
|
|
{
|
|
|
|
return -1;
|
|
|
|
}
|
2008-10-30 21:41:01 +00:00
|
|
|
|
2013-09-04 15:12:25 +00:00
|
|
|
#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
|
|
|
|
|
2008-10-30 21:41:01 +00:00
|
|
|
void print_mmc_devices(char separator)
|
|
|
|
{
|
|
|
|
struct mmc *m;
|
|
|
|
struct list_head *entry;
|
|
|
|
|
|
|
|
list_for_each(entry, &mmc_devices) {
|
|
|
|
m = list_entry(entry, struct mmc, link);
|
|
|
|
|
2014-03-11 17:34:20 +00:00
|
|
|
printf("%s: %d", m->cfg->name, m->block_dev.dev);
|
2008-10-30 21:41:01 +00:00
|
|
|
|
2014-11-11 10:25:42 +00:00
|
|
|
if (entry->next != &mmc_devices) {
|
|
|
|
printf("%c", separator);
|
|
|
|
if (separator != '\n')
|
|
|
|
puts (" ");
|
|
|
|
}
|
2008-10-30 21:41:01 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
printf("\n");
|
|
|
|
}
|
|
|
|
|
2013-09-04 15:12:25 +00:00
|
|
|
#else
|
|
|
|
void print_mmc_devices(char separator) { }
|
|
|
|
#endif
|
|
|
|
|
2011-05-02 16:26:25 +00:00
|
|
|
int get_mmc_num(void)
|
|
|
|
{
|
|
|
|
return cur_dev_num;
|
|
|
|
}
|
|
|
|
|
2012-11-28 15:21:13 +00:00
|
|
|
void mmc_set_preinit(struct mmc *mmc, int preinit)
|
|
|
|
{
|
|
|
|
mmc->preinit = preinit;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void do_preinit(void)
|
|
|
|
{
|
|
|
|
struct mmc *m;
|
|
|
|
struct list_head *entry;
|
|
|
|
|
|
|
|
list_for_each(entry, &mmc_devices) {
|
|
|
|
m = list_entry(entry, struct mmc, link);
|
|
|
|
|
|
|
|
if (m->preinit)
|
|
|
|
mmc_start_init(m);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
|
2008-10-30 21:41:01 +00:00
|
|
|
int mmc_initialize(bd_t *bis)
|
|
|
|
{
|
|
|
|
INIT_LIST_HEAD (&mmc_devices);
|
|
|
|
cur_dev_num = 0;
|
|
|
|
|
|
|
|
if (board_mmc_init(bis) < 0)
|
|
|
|
cpu_mmc_init(bis);
|
|
|
|
|
2013-08-16 07:16:11 +00:00
|
|
|
#ifndef CONFIG_SPL_BUILD
|
2008-10-30 21:41:01 +00:00
|
|
|
print_mmc_devices(',');
|
2013-08-16 07:16:11 +00:00
|
|
|
#endif
|
2008-10-30 21:41:01 +00:00
|
|
|
|
2012-11-28 15:21:13 +00:00
|
|
|
do_preinit();
|
2008-10-30 21:41:01 +00:00
|
|
|
return 0;
|
|
|
|
}
|
2013-04-27 06:12:58 +00:00
|
|
|
|
|
|
|
#ifdef CONFIG_SUPPORT_EMMC_BOOT
|
|
|
|
/*
|
|
|
|
* This function changes the size of boot partition and the size of rpmb
|
|
|
|
* partition present on EMMC devices.
|
|
|
|
*
|
|
|
|
* Input Parameters:
|
|
|
|
* struct *mmc: pointer for the mmc device strcuture
|
|
|
|
* bootsize: size of boot partition
|
|
|
|
* rpmbsize: size of rpmb partition
|
|
|
|
*
|
|
|
|
* Returns 0 on success.
|
|
|
|
*/
|
|
|
|
|
|
|
|
int mmc_boot_partition_size_change(struct mmc *mmc, unsigned long bootsize,
|
|
|
|
unsigned long rpmbsize)
|
|
|
|
{
|
|
|
|
int err;
|
|
|
|
struct mmc_cmd cmd;
|
|
|
|
|
|
|
|
/* Only use this command for raw EMMC moviNAND. Enter backdoor mode */
|
|
|
|
cmd.cmdidx = MMC_CMD_RES_MAN;
|
|
|
|
cmd.resp_type = MMC_RSP_R1b;
|
|
|
|
cmd.cmdarg = MMC_CMD62_ARG1;
|
|
|
|
|
|
|
|
err = mmc_send_cmd(mmc, &cmd, NULL);
|
|
|
|
if (err) {
|
|
|
|
debug("mmc_boot_partition_size_change: Error1 = %d\n", err);
|
|
|
|
return err;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Boot partition changing mode */
|
|
|
|
cmd.cmdidx = MMC_CMD_RES_MAN;
|
|
|
|
cmd.resp_type = MMC_RSP_R1b;
|
|
|
|
cmd.cmdarg = MMC_CMD62_ARG2;
|
|
|
|
|
|
|
|
err = mmc_send_cmd(mmc, &cmd, NULL);
|
|
|
|
if (err) {
|
|
|
|
debug("mmc_boot_partition_size_change: Error2 = %d\n", err);
|
|
|
|
return err;
|
|
|
|
}
|
|
|
|
/* boot partition size is multiple of 128KB */
|
|
|
|
bootsize = (bootsize * 1024) / 128;
|
|
|
|
|
|
|
|
/* Arg: boot partition size */
|
|
|
|
cmd.cmdidx = MMC_CMD_RES_MAN;
|
|
|
|
cmd.resp_type = MMC_RSP_R1b;
|
|
|
|
cmd.cmdarg = bootsize;
|
|
|
|
|
|
|
|
err = mmc_send_cmd(mmc, &cmd, NULL);
|
|
|
|
if (err) {
|
|
|
|
debug("mmc_boot_partition_size_change: Error3 = %d\n", err);
|
|
|
|
return err;
|
|
|
|
}
|
|
|
|
/* RPMB partition size is multiple of 128KB */
|
|
|
|
rpmbsize = (rpmbsize * 1024) / 128;
|
|
|
|
/* Arg: RPMB partition size */
|
|
|
|
cmd.cmdidx = MMC_CMD_RES_MAN;
|
|
|
|
cmd.resp_type = MMC_RSP_R1b;
|
|
|
|
cmd.cmdarg = rpmbsize;
|
|
|
|
|
|
|
|
err = mmc_send_cmd(mmc, &cmd, NULL);
|
|
|
|
if (err) {
|
|
|
|
debug("mmc_boot_partition_size_change: Error4 = %d\n", err);
|
|
|
|
return err;
|
|
|
|
}
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2014-02-05 15:24:22 +00:00
|
|
|
/*
|
|
|
|
* Modify EXT_CSD[177] which is BOOT_BUS_WIDTH
|
|
|
|
* based on the passed in values for BOOT_BUS_WIDTH, RESET_BOOT_BUS_WIDTH
|
|
|
|
* and BOOT_MODE.
|
|
|
|
*
|
|
|
|
* Returns 0 on success.
|
|
|
|
*/
|
|
|
|
int mmc_set_boot_bus_width(struct mmc *mmc, u8 width, u8 reset, u8 mode)
|
|
|
|
{
|
|
|
|
int err;
|
|
|
|
|
|
|
|
err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_BOOT_BUS_WIDTH,
|
|
|
|
EXT_CSD_BOOT_BUS_WIDTH_MODE(mode) |
|
|
|
|
EXT_CSD_BOOT_BUS_WIDTH_RESET(reset) |
|
|
|
|
EXT_CSD_BOOT_BUS_WIDTH_WIDTH(width));
|
|
|
|
|
|
|
|
if (err)
|
|
|
|
return err;
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2014-02-05 15:24:21 +00:00
|
|
|
/*
|
|
|
|
* Modify EXT_CSD[179] which is PARTITION_CONFIG (formerly BOOT_CONFIG)
|
|
|
|
* based on the passed in values for BOOT_ACK, BOOT_PARTITION_ENABLE and
|
|
|
|
* PARTITION_ACCESS.
|
|
|
|
*
|
|
|
|
* Returns 0 on success.
|
|
|
|
*/
|
|
|
|
int mmc_set_part_conf(struct mmc *mmc, u8 ack, u8 part_num, u8 access)
|
|
|
|
{
|
|
|
|
int err;
|
|
|
|
|
|
|
|
err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_PART_CONF,
|
|
|
|
EXT_CSD_BOOT_ACK(ack) |
|
|
|
|
EXT_CSD_BOOT_PART_NUM(part_num) |
|
|
|
|
EXT_CSD_PARTITION_ACCESS(access));
|
|
|
|
|
|
|
|
if (err)
|
|
|
|
return err;
|
|
|
|
return 0;
|
|
|
|
}
|
2014-02-07 19:15:20 +00:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Modify EXT_CSD[162] which is RST_n_FUNCTION based on the given value
|
|
|
|
* for enable. Note that this is a write-once field for non-zero values.
|
|
|
|
*
|
|
|
|
* Returns 0 on success.
|
|
|
|
*/
|
|
|
|
int mmc_set_rst_n_function(struct mmc *mmc, u8 enable)
|
|
|
|
{
|
|
|
|
return mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_RST_N_FUNCTION,
|
|
|
|
enable);
|
|
|
|
}
|
2013-04-27 06:12:58 +00:00
|
|
|
#endif
|