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https://github.com/AsahiLinux/u-boot
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129 lines
4.9 KiB
C
129 lines
4.9 KiB
C
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/*
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* Copyright Altera Corporation (C) 2012-2015
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#define RW_MGR_READ_B2B_WAIT2 0x6A
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#define RW_MGR_LFSR_WR_RD_BANK_0_WAIT 0x31
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#define RW_MGR_REFRESH_ALL 0x14
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#define RW_MGR_ZQCL 0x06
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#define RW_MGR_LFSR_WR_RD_BANK_0_NOP 0x22
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#define RW_MGR_LFSR_WR_RD_BANK_0_DQS 0x23
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#define RW_MGR_ACTIVATE_0_AND_1 0x0D
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#define RW_MGR_MRS2_MIRR 0x0A
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#define RW_MGR_INIT_RESET_0_CKE_0 0x6E
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#define RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT 0x45
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#define RW_MGR_ACTIVATE_1 0x0F
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#define RW_MGR_MRS2 0x04
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#define RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1 0x34
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#define RW_MGR_MRS1 0x03
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#ifdef CONFIG_SOCFPGA_ARRIA5
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/* The if..else... is not required if generated by tools */
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#define RW_MGR_IDLE_LOOP1 0x7A
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#else
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#define RW_MGR_IDLE_LOOP1 0x7C
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#endif /* CONFIG_SOCFPGA_ARRIA5 */
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#define RW_MGR_GUARANTEED_WRITE_WAIT2 0x18
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#define RW_MGR_MRS3 0x05
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#ifdef CONFIG_SOCFPGA_ARRIA5
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/* The if..else... is not required if generated by tools */
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#define RW_MGR_IDLE_LOOP2 0x79
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#else
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#define RW_MGR_IDLE_LOOP2 0x7B
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#endif /* CONFIG_SOCFPGA_ARRIA5 */
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#define RW_MGR_GUARANTEED_WRITE_WAIT1 0x1E
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#define RW_MGR_LFSR_WR_RD_BANK_0_DATA 0x24
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#define RW_MGR_GUARANTEED_WRITE_WAIT3 0x1C
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#ifdef CONFIG_SOCFPGA_ARRIA5
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/* The if..else... is not required if generated by tools */
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#define RW_MGR_RDIMM_CMD 0x78
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#else
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#define RW_MGR_RDIMM_CMD 0x7A
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#endif /* CONFIG_SOCFPGA_ARRIA5 */
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#define RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP 0x36
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#define RW_MGR_GUARANTEED_WRITE_WAIT0 0x1A
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#define RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA 0x38
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#define RW_MGR_GUARANTEED_READ_CONT 0x53
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#define RW_MGR_MRS3_MIRR 0x0B
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#define RW_MGR_IDLE 0x00
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#define RW_MGR_READ_B2B 0x58
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#define RW_MGR_INIT_RESET_0_CKE_0_inloop 0x6F
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#define RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS 0x37
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#define RW_MGR_GUARANTEED_WRITE 0x17
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#define RW_MGR_PRECHARGE_ALL 0x12
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#define RW_MGR_INIT_RESET_1_CKE_0_inloop_1 0x74
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#ifdef CONFIG_SOCFPGA_ARRIA5
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/* The if..else... is not required if generated by tools */
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#define RW_MGR_SGLE_READ 0x7C
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#else
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#define RW_MGR_SGLE_READ 0x7E
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#endif /* CONFIG_SOCFPGA_ARRIA5 */
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#define RW_MGR_MRS0_USER_MIRR 0x0C
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#define RW_MGR_RETURN 0x01
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#define RW_MGR_LFSR_WR_RD_DM_BANK_0 0x35
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#define RW_MGR_MRS0_USER 0x07
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#define RW_MGR_GUARANTEED_READ 0x4B
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#define RW_MGR_MRS0_DLL_RESET_MIRR 0x08
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#define RW_MGR_INIT_RESET_1_CKE_0 0x73
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#define RW_MGR_ACTIVATE_0_AND_1_WAIT2 0x10
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#define RW_MGR_LFSR_WR_RD_BANK_0_WL_1 0x20
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#define RW_MGR_MRS0_DLL_RESET 0x02
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#define RW_MGR_ACTIVATE_0_AND_1_WAIT1 0x0E
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#define RW_MGR_LFSR_WR_RD_BANK_0 0x21
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#define RW_MGR_CLEAR_DQS_ENABLE 0x48
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#define RW_MGR_MRS1_MIRR 0x09
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#define RW_MGR_READ_B2B_WAIT1 0x60
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#define RW_MGR_CONTENT_READ_B2B_WAIT2 0x00C680
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#define RW_MGR_CONTENT_LFSR_WR_RD_BANK_0_WAIT 0x00A680
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#define RW_MGR_CONTENT_REFRESH_ALL 0x000980
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#define RW_MGR_CONTENT_ZQCL 0x008380
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#define RW_MGR_CONTENT_LFSR_WR_RD_BANK_0_NOP 0x00E700
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#define RW_MGR_CONTENT_LFSR_WR_RD_BANK_0_DQS 0x000C00
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#define RW_MGR_CONTENT_ACTIVATE_0_AND_1 0x000800
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#define RW_MGR_CONTENT_MRS2_MIRR 0x008580
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#define RW_MGR_CONTENT_INIT_RESET_0_CKE_0 0x000000
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#define RW_MGR_CONTENT_LFSR_WR_RD_DM_BANK_0_WAIT 0x00A680
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#define RW_MGR_CONTENT_ACTIVATE_1 0x000880
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#define RW_MGR_CONTENT_MRS2 0x008280
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#define RW_MGR_CONTENT_LFSR_WR_RD_DM_BANK_0_WL_1 0x00CE00
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#define RW_MGR_CONTENT_MRS1 0x008200
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#define RW_MGR_CONTENT_IDLE_LOOP1 0x00A680
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#define RW_MGR_CONTENT_GUARANTEED_WRITE_WAIT2 0x00CCE8
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#define RW_MGR_CONTENT_MRS3 0x008300
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#define RW_MGR_CONTENT_IDLE_LOOP2 0x008680
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#define RW_MGR_CONTENT_GUARANTEED_WRITE_WAIT1 0x00AC88
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#define RW_MGR_CONTENT_LFSR_WR_RD_BANK_0_DATA 0x020CE0
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#define RW_MGR_CONTENT_GUARANTEED_WRITE_WAIT3 0x00EC88
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#define RW_MGR_CONTENT_RDIMM_CMD 0x009180
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#define RW_MGR_CONTENT_LFSR_WR_RD_DM_BANK_0_NOP 0x00E700
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#define RW_MGR_CONTENT_GUARANTEED_WRITE_WAIT0 0x008CE8
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#define RW_MGR_CONTENT_LFSR_WR_RD_DM_BANK_0_DATA 0x030CE0
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#define RW_MGR_CONTENT_GUARANTEED_READ_CONT 0x001168
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#define RW_MGR_CONTENT_MRS3_MIRR 0x008600
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#define RW_MGR_CONTENT_IDLE 0x080000
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#define RW_MGR_CONTENT_READ_B2B 0x040E88
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#define RW_MGR_CONTENT_INIT_RESET_0_CKE_0_inloop 0x000000
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#define RW_MGR_CONTENT_LFSR_WR_RD_DM_BANK_0_DQS 0x000C00
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#define RW_MGR_CONTENT_GUARANTEED_WRITE 0x000B68
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#define RW_MGR_CONTENT_PRECHARGE_ALL 0x000900
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#define RW_MGR_CONTENT_INIT_RESET_1_CKE_0_inloop_1 0x000080
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#define RW_MGR_CONTENT_SGLE_READ 0x040F08
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#define RW_MGR_CONTENT_MRS0_USER_MIRR 0x008400
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#define RW_MGR_CONTENT_RETURN 0x080680
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#define RW_MGR_CONTENT_LFSR_WR_RD_DM_BANK_0 0x00CD80
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#define RW_MGR_CONTENT_MRS0_USER 0x008100
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#define RW_MGR_CONTENT_GUARANTEED_READ 0x001168
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#define RW_MGR_CONTENT_MRS0_DLL_RESET_MIRR 0x008480
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#define RW_MGR_CONTENT_INIT_RESET_1_CKE_0 0x000080
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#define RW_MGR_CONTENT_ACTIVATE_0_AND_1_WAIT2 0x00A680
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#define RW_MGR_CONTENT_LFSR_WR_RD_BANK_0_WL_1 0x00CE00
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#define RW_MGR_CONTENT_MRS0_DLL_RESET 0x008180
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#define RW_MGR_CONTENT_ACTIVATE_0_AND_1_WAIT1 0x008680
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#define RW_MGR_CONTENT_LFSR_WR_RD_BANK_0 0x00CD80
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#define RW_MGR_CONTENT_CLEAR_DQS_ENABLE 0x001158
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#define RW_MGR_CONTENT_MRS1_MIRR 0x008500
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#define RW_MGR_CONTENT_READ_B2B_WAIT1 0x00A680
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