2015-10-09 20:58:28 +00:00
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if ARCH_RMOBILE
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2014-08-30 22:10:57 +00:00
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2023-02-28 06:28:56 +00:00
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# Renesas ARM SoCs R-Car Gen3/Gen4 (64bit)
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config RCAR_64
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bool
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2016-03-31 18:51:34 +00:00
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select ARM64
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2018-09-26 05:32:13 +00:00
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select CMD_CACHE
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2021-04-03 14:58:49 +00:00
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select OF_BOARD_SETUP
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2023-02-28 06:28:54 +00:00
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select PHY
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2019-04-21 20:14:11 +00:00
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select PINCONF
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2023-02-28 06:28:54 +00:00
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select PINCTRL
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2019-04-21 20:14:11 +00:00
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select PINCTRL_PFC
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2021-06-13 20:40:45 +00:00
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select POSITION_INDEPENDENT
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2018-12-03 22:46:11 +00:00
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imply CMD_FS_UUID
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imply CMD_GPT
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imply CMD_MMC_SWRITE if MMC
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2023-02-28 06:28:54 +00:00
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imply CMD_UUID
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2023-02-28 06:28:56 +00:00
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imply SUPPORT_EMMC_RPMB if MMC
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choice
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prompt "Target Renesas SoC select"
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default RCAR_32
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config RCAR_32
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bool "Renesas ARM SoCs R-Car Gen1/Gen2 (32bit)"
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select CPU_V7A
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config RCAR_GEN3
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bool "Renesas ARM SoCs R-Car Gen3 (64bit)"
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select RCAR_64
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select SUPPORT_SPL
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ARM: rmobile: Add recovery SPL for R-Car Gen3
Build an SPL which can be started via SCIF download mode on R-Car Gen3
and allows loading and executing U-Boot uImage with the next stage code.
This is also useful for starting e.g. ATF BL2, which inits the hardware
and returns to the U-Boot SPL, which can then load e.g. U-Boot proper.
The H3, M3-W, M3-N SoCs have plenty of SRAM for storing the U-Boot SPL
while the payload, e.g. ATF BL2, executes, so there is no problem here.
However, E3 and D3 have much less SRAM, hence the loader uses a trick
where it copies itself beyond the area used by BL2 and executes from
there. That area is 32kiB large and not enough to hold U-Boot SPL, BSS,
stack and malloc area, so the later two are placed at +0x4000 offset
from start of SRAM, another area not used by ATF BL2. To make things
even more complicated, the SCIF loader cannot load to the upper 32kiB
of the SRAM directly, hence the copying approach.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-10-03 10:44:13 +00:00
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imply SPL
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imply SPL_BOARD_INIT
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imply SPL_GZIP
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imply SPL_LIBCOMMON_SUPPORT
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imply SPL_LIBGENERIC_SUPPORT
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2021-08-08 18:20:12 +00:00
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imply SPL_SERIAL
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ARM: rmobile: Add recovery SPL for R-Car Gen3
Build an SPL which can be started via SCIF download mode on R-Car Gen3
and allows loading and executing U-Boot uImage with the next stage code.
This is also useful for starting e.g. ATF BL2, which inits the hardware
and returns to the U-Boot SPL, which can then load e.g. U-Boot proper.
The H3, M3-W, M3-N SoCs have plenty of SRAM for storing the U-Boot SPL
while the payload, e.g. ATF BL2, executes, so there is no problem here.
However, E3 and D3 have much less SRAM, hence the loader uses a trick
where it copies itself beyond the area used by BL2 and executes from
there. That area is 32kiB large and not enough to hold U-Boot SPL, BSS,
stack and malloc area, so the later two are placed at +0x4000 offset
from start of SRAM, another area not used by ATF BL2. To make things
even more complicated, the SCIF loader cannot load to the upper 32kiB
of the SRAM directly, hence the copying approach.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-10-03 10:44:13 +00:00
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imply SPL_SYS_MALLOC_SIMPLE
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imply SPL_TINY_MEMSET
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2019-09-25 14:56:27 +00:00
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imply SPL_USE_TINY_PRINTF
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2023-02-28 06:28:54 +00:00
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imply SPL_YMODEM_SUPPORT
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2016-03-31 18:51:34 +00:00
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2023-02-28 21:22:03 +00:00
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config RCAR_GEN4
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bool "Renesas ARM SoCs R-Car Gen4 (64bit)"
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select RCAR_64
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2017-08-23 19:53:59 +00:00
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config RZA1
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prompt "Renesas ARM SoCs RZ/A1 (32bit)"
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select CPU_V7A
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ARM: rmobile: Add support for Renesas RZ/N1 SoC
The RZ/N1 is a family of SoC devices from Renesas, featuring:
* ARM Cortex-A7 CPU (single/dual core) and/or Cortex-M3
* Integrated SRAM up to 6MB
* Integrated gigabit ethernet switch
* Optional DDR2/3 controller
* I2C, SPI, UART, NAND, QSPI, SDIO, USB, CAN, RTC, LCD
Add basic support for this family, modeled on the existing RZA1.
Signed-off-by: Ralph Siemsen <ralph.siemsen@linaro.org>
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-05-13 01:36:55 +00:00
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config RZN1
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prompt "Renesas ARM SoCs RZ/N1 (32bit)"
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select CPU_V7A
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select ARMV7_SET_CORTEX_SMPEN if !SPL
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select SPL_ARMV7_SET_CORTEX_SMPEN if SPL
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select CLK
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select CLK_RENESAS
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select CLK_R9A06G032
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select DM
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select DM_ETH
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select DM_SERIAL
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select PINCTRL
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select PINCONF
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select REGMAP
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select SYSRESET
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select SYSRESET_SYSCON
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imply CMD_DM
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2023-10-16 09:25:27 +00:00
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config RZG2L
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prompt "Renesas RZ/G2L Family ARM SoCs"
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select GICV3
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select RCAR_64
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2023-10-16 09:25:29 +00:00
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imply CLK_RZG2L
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2023-10-16 09:25:27 +00:00
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imply MULTI_DTB_FIT
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imply MULTI_DTB_FIT_USER_DEFINED_AREA
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imply RENESAS_SDHI
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imply SYS_MALLOC_F
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help
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Enable support for the Renesas RZ/G2L family of SoCs. Currently
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support is only included for the RZ/G2L itself (based on the R9A07G044
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SoC). Support for additional SoCs in this family (RZ/G2LC, RZ/G2UL,
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RZ/V2L & RZ/Five) is not yet available.
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2015-03-04 23:30:37 +00:00
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endchoice
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2023-02-28 06:28:55 +00:00
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config SYS_SOC
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default "rmobile" if ARCH_RMOBILE
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2016-06-17 04:52:13 +00:00
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source "arch/arm/mach-rmobile/Kconfig.32"
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2016-03-31 18:51:34 +00:00
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source "arch/arm/mach-rmobile/Kconfig.64"
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2017-08-23 19:53:59 +00:00
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source "arch/arm/mach-rmobile/Kconfig.rza1"
|
ARM: rmobile: Add support for Renesas RZ/N1 SoC
The RZ/N1 is a family of SoC devices from Renesas, featuring:
* ARM Cortex-A7 CPU (single/dual core) and/or Cortex-M3
* Integrated SRAM up to 6MB
* Integrated gigabit ethernet switch
* Optional DDR2/3 controller
* I2C, SPI, UART, NAND, QSPI, SDIO, USB, CAN, RTC, LCD
Add basic support for this family, modeled on the existing RZA1.
Signed-off-by: Ralph Siemsen <ralph.siemsen@linaro.org>
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-05-13 01:36:55 +00:00
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source "arch/arm/mach-rmobile/Kconfig.rzn1"
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2023-10-16 09:25:27 +00:00
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source "arch/arm/mach-rmobile/Kconfig.rzg2l"
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2014-08-30 22:10:57 +00:00
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endif
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