2019-04-10 12:09:27 +00:00
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// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
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/*
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* Copyright (C) 2019, STMicroelectronics - All Rights Reserved
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*/
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2020-11-06 18:01:36 +00:00
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#define LOG_CATEGORY UCLASS_RAM
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2019-04-10 12:09:27 +00:00
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#include <common.h>
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2020-05-10 17:40:03 +00:00
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#include <command.h>
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2019-04-10 12:09:27 +00:00
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#include <console.h>
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#include <cli.h>
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#include <clk.h>
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2020-05-10 17:40:05 +00:00
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#include <log.h>
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2019-04-10 12:09:27 +00:00
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#include <malloc.h>
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#include <ram.h>
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#include <reset.h>
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#include "stm32mp1_ddr.h"
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2019-04-10 12:09:28 +00:00
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#include "stm32mp1_tests.h"
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2019-04-10 12:09:27 +00:00
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DECLARE_GLOBAL_DATA_PTR;
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enum ddr_command {
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DDR_CMD_HELP,
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DDR_CMD_INFO,
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DDR_CMD_FREQ,
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DDR_CMD_RESET,
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DDR_CMD_PARAM,
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DDR_CMD_PRINT,
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DDR_CMD_EDIT,
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DDR_CMD_STEP,
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DDR_CMD_NEXT,
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DDR_CMD_GO,
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DDR_CMD_TEST,
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DDR_CMD_TUNING,
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DDR_CMD_UNKNOWN,
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};
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const char *step_str[] = {
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[STEP_DDR_RESET] = "DDR_RESET",
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[STEP_CTL_INIT] = "DDR_CTRL_INIT_DONE",
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[STEP_PHY_INIT] = "DDR PHY_INIT_DONE",
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[STEP_DDR_READY] = "DDR_READY",
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[STEP_RUN] = "RUN"
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};
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enum ddr_command stm32mp1_get_command(char *cmd, int argc)
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{
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const char *cmd_string[DDR_CMD_UNKNOWN] = {
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[DDR_CMD_HELP] = "help",
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[DDR_CMD_INFO] = "info",
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[DDR_CMD_FREQ] = "freq",
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[DDR_CMD_RESET] = "reset",
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[DDR_CMD_PARAM] = "param",
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[DDR_CMD_PRINT] = "print",
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[DDR_CMD_EDIT] = "edit",
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[DDR_CMD_STEP] = "step",
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[DDR_CMD_NEXT] = "next",
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[DDR_CMD_GO] = "go",
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2019-04-10 12:09:28 +00:00
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#ifdef CONFIG_STM32MP1_DDR_TESTS
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[DDR_CMD_TEST] = "test",
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2019-04-10 12:09:29 +00:00
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#endif
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#ifdef CONFIG_STM32MP1_DDR_TUNING
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[DDR_CMD_TUNING] = "tuning",
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2019-04-10 12:09:28 +00:00
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#endif
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2019-04-10 12:09:27 +00:00
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};
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/* min and max number of argument */
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const char cmd_arg[DDR_CMD_UNKNOWN][2] = {
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[DDR_CMD_HELP] = { 0, 0 },
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[DDR_CMD_INFO] = { 0, 255 },
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[DDR_CMD_FREQ] = { 0, 1 },
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[DDR_CMD_RESET] = { 0, 0 },
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[DDR_CMD_PARAM] = { 0, 2 },
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[DDR_CMD_PRINT] = { 0, 1 },
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[DDR_CMD_EDIT] = { 2, 2 },
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[DDR_CMD_STEP] = { 0, 1 },
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[DDR_CMD_NEXT] = { 0, 0 },
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[DDR_CMD_GO] = { 0, 0 },
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2019-04-10 12:09:28 +00:00
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#ifdef CONFIG_STM32MP1_DDR_TESTS
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[DDR_CMD_TEST] = { 0, 255 },
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2019-04-10 12:09:29 +00:00
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#endif
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#ifdef CONFIG_STM32MP1_DDR_TUNING
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[DDR_CMD_TUNING] = { 0, 255 },
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2019-04-10 12:09:28 +00:00
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#endif
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2019-04-10 12:09:27 +00:00
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};
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int i;
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for (i = 0; i < DDR_CMD_UNKNOWN; i++)
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if (!strcmp(cmd, cmd_string[i])) {
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if (argc - 1 < cmd_arg[i][0]) {
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printf("no enought argument (min=%d)\n",
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cmd_arg[i][0]);
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return DDR_CMD_UNKNOWN;
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} else if (argc - 1 > cmd_arg[i][1]) {
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printf("too many argument (max=%d)\n",
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cmd_arg[i][1]);
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return DDR_CMD_UNKNOWN;
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} else {
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return i;
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}
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}
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printf("unknown command %s\n", cmd);
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return DDR_CMD_UNKNOWN;
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}
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static void stm32mp1_do_usage(void)
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{
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const char *usage = {
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"commands:\n\n"
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"help displays help\n"
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"info displays DDR information\n"
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"info <param> <val> changes DDR information\n"
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2020-03-06 10:14:11 +00:00
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" with <param> = step, name, size, speed or cal\n"
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2019-04-10 12:09:27 +00:00
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"freq displays the DDR PHY frequency in kHz\n"
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"freq <freq> changes the DDR PHY frequency\n"
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"param [type|reg] prints input parameters\n"
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"param <reg> <val> edits parameters in step 0\n"
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"print [type|reg] dumps registers\n"
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"edit <reg> <val> modifies one register\n"
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"step lists the available step\n"
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"step <n> go to the step <n>\n"
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"next goes to the next step\n"
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"go continues the U-Boot SPL execution\n"
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"reset reboots machine\n"
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2019-04-10 12:09:28 +00:00
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#ifdef CONFIG_STM32MP1_DDR_TESTS
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"test [help] | <n> [...] lists (with help) or executes test <n>\n"
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2019-04-10 12:09:29 +00:00
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#endif
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#ifdef CONFIG_STM32MP1_DDR_TUNING
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"tuning [help] | <n> [...] lists (with help) or execute tuning <n>\n"
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2019-04-10 12:09:28 +00:00
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#endif
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2019-04-10 12:09:27 +00:00
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"\nwith for [type|reg]:\n"
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" all registers if absent\n"
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" <type> = ctl, phy\n"
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" or one category (static, timing, map, perf, cal, dyn)\n"
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" <reg> = name of the register\n"
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};
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puts(usage);
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}
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static bool stm32mp1_check_step(enum stm32mp1_ddr_interact_step step,
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enum stm32mp1_ddr_interact_step expected)
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{
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if (step != expected) {
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printf("invalid step %d:%s expecting %d:%s\n",
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step, step_str[step],
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expected,
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step_str[expected]);
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return false;
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}
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return true;
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}
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static void stm32mp1_do_info(struct ddr_info *priv,
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struct stm32mp1_ddr_config *config,
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enum stm32mp1_ddr_interact_step step,
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2020-05-10 17:40:03 +00:00
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int argc, char *const argv[])
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2019-04-10 12:09:27 +00:00
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{
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unsigned long value;
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static char *ddr_name;
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if (argc == 1) {
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printf("step = %d : %s\n", step, step_str[step]);
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printf("name = %s\n", config->info.name);
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printf("size = 0x%x\n", config->info.size);
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printf("speed = %d kHz\n", config->info.speed);
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2020-03-06 10:14:11 +00:00
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printf("cal = %d\n", config->p_cal_present);
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2019-04-10 12:09:27 +00:00
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return;
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}
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if (argc < 3) {
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printf("no enought parameter\n");
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return;
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}
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if (!strcmp(argv[1], "name")) {
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u32 i, name_len = 0;
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for (i = 2; i < argc; i++)
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name_len += strlen(argv[i]) + 1;
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if (ddr_name)
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free(ddr_name);
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ddr_name = malloc(name_len);
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config->info.name = ddr_name;
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if (!ddr_name) {
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printf("alloc error, length %d\n", name_len);
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return;
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}
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strcpy(ddr_name, argv[2]);
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for (i = 3; i < argc; i++) {
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strcat(ddr_name, " ");
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strcat(ddr_name, argv[i]);
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}
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printf("name = %s\n", ddr_name);
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return;
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}
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if (!strcmp(argv[1], "size")) {
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if (strict_strtoul(argv[2], 16, &value) < 0) {
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printf("invalid value %s\n", argv[2]);
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} else {
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config->info.size = value;
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printf("size = 0x%x\n", config->info.size);
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}
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return;
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}
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if (!strcmp(argv[1], "speed")) {
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if (strict_strtoul(argv[2], 10, &value) < 0) {
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printf("invalid value %s\n", argv[2]);
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} else {
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config->info.speed = value;
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printf("speed = %d kHz\n", config->info.speed);
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value = clk_get_rate(&priv->clk);
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printf("DDRPHY = %ld kHz\n", value / 1000);
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}
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return;
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}
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2020-03-06 10:14:11 +00:00
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if (!strcmp(argv[1], "cal")) {
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if (strict_strtoul(argv[2], 10, &value) < 0 ||
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(value != 0 && value != 1)) {
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printf("invalid value %s\n", argv[2]);
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} else {
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config->p_cal_present = value;
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printf("cal = %d\n", config->p_cal_present);
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}
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return;
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}
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2019-04-10 12:09:27 +00:00
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printf("argument %s invalid\n", argv[1]);
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}
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static bool stm32mp1_do_freq(struct ddr_info *priv,
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2020-05-10 17:40:03 +00:00
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int argc, char *const argv[])
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2019-04-10 12:09:27 +00:00
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{
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unsigned long ddrphy_clk;
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if (argc == 2) {
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if (strict_strtoul(argv[1], 0, &ddrphy_clk) < 0) {
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printf("invalid argument %s", argv[1]);
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return false;
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}
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if (clk_set_rate(&priv->clk, ddrphy_clk * 1000)) {
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printf("ERROR: update failed!\n");
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return false;
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}
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}
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ddrphy_clk = clk_get_rate(&priv->clk);
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printf("DDRPHY = %ld kHz\n", ddrphy_clk / 1000);
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if (argc == 2)
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return true;
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return false;
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}
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static void stm32mp1_do_param(enum stm32mp1_ddr_interact_step step,
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const struct stm32mp1_ddr_config *config,
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2020-05-10 17:40:03 +00:00
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int argc, char *const argv[])
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2019-04-10 12:09:27 +00:00
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{
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switch (argc) {
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case 1:
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stm32mp1_dump_param(config, NULL);
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break;
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case 2:
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if (stm32mp1_dump_param(config, argv[1]))
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printf("invalid argument %s\n",
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argv[1]);
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break;
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case 3:
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if (!stm32mp1_check_step(step, STEP_DDR_RESET))
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return;
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stm32mp1_edit_param(config, argv[1], argv[2]);
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break;
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}
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}
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static void stm32mp1_do_print(struct ddr_info *priv,
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2020-05-10 17:40:03 +00:00
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int argc, char *const argv[])
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2019-04-10 12:09:27 +00:00
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{
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switch (argc) {
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case 1:
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stm32mp1_dump_reg(priv, NULL);
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break;
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case 2:
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if (stm32mp1_dump_reg(priv, argv[1]))
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printf("invalid argument %s\n",
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argv[1]);
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break;
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}
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}
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static int stm32mp1_do_step(enum stm32mp1_ddr_interact_step step,
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2020-05-10 17:40:03 +00:00
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int argc, char *const argv[])
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2019-04-10 12:09:27 +00:00
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{
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int i;
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unsigned long value;
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switch (argc) {
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case 1:
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for (i = 0; i < ARRAY_SIZE(step_str); i++)
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printf("%d:%s\n", i, step_str[i]);
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break;
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case 2:
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if ((strict_strtoul(argv[1], 0,
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&value) < 0) ||
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value >= ARRAY_SIZE(step_str)) {
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printf("invalid argument %s\n",
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argv[1]);
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goto end;
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}
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if (value != STEP_DDR_RESET &&
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value <= step) {
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printf("invalid target %d:%s, current step is %d:%s\n",
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(int)value, step_str[value],
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step, step_str[step]);
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goto end;
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}
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printf("step to %d:%s\n",
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(int)value, step_str[value]);
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return (int)value;
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};
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end:
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return step;
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}
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2019-04-10 12:09:29 +00:00
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#if defined(CONFIG_STM32MP1_DDR_TESTS) || defined(CONFIG_STM32MP1_DDR_TUNING)
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2019-04-10 12:09:28 +00:00
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static const char * const s_result[] = {
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[TEST_PASSED] = "Pass",
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[TEST_FAILED] = "Failed",
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[TEST_ERROR] = "Error"
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};
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static void stm32mp1_ddr_subcmd(struct ddr_info *priv,
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int argc, char *argv[],
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const struct test_desc array[],
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const int array_nb)
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{
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int i;
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unsigned long value;
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int result;
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char string[50] = "";
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|
|
|
|
|
|
|
if (argc == 1) {
|
|
|
|
printf("%s:%d\n", argv[0], array_nb);
|
|
|
|
for (i = 0; i < array_nb; i++)
|
|
|
|
printf("%d:%s:%s\n",
|
|
|
|
i, array[i].name, array[i].usage);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
if (argc > 1 && !strcmp(argv[1], "help")) {
|
|
|
|
printf("%s:%d\n", argv[0], array_nb);
|
|
|
|
for (i = 0; i < array_nb; i++)
|
|
|
|
printf("%d:%s:%s:%s\n", i,
|
|
|
|
array[i].name, array[i].usage, array[i].help);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
if ((strict_strtoul(argv[1], 0, &value) < 0) ||
|
|
|
|
value >= array_nb) {
|
|
|
|
sprintf(string, "invalid argument %s",
|
|
|
|
argv[1]);
|
|
|
|
result = TEST_FAILED;
|
|
|
|
goto end;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (argc > (array[value].max_args + 2)) {
|
|
|
|
sprintf(string, "invalid nb of args %d, max %d",
|
|
|
|
argc - 2, array[value].max_args);
|
|
|
|
result = TEST_FAILED;
|
|
|
|
goto end;
|
|
|
|
}
|
|
|
|
|
|
|
|
printf("execute %d:%s\n", (int)value, array[value].name);
|
|
|
|
clear_ctrlc();
|
|
|
|
result = array[value].fct(priv->ctl, priv->phy,
|
|
|
|
string, argc - 2, &argv[2]);
|
|
|
|
|
|
|
|
end:
|
|
|
|
printf("Result: %s [%s]\n", s_result[result], string);
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
2019-04-10 12:09:27 +00:00
|
|
|
bool stm32mp1_ddr_interactive(void *priv,
|
|
|
|
enum stm32mp1_ddr_interact_step step,
|
|
|
|
const struct stm32mp1_ddr_config *config)
|
|
|
|
{
|
|
|
|
char buffer[CONFIG_SYS_CBSIZE];
|
|
|
|
char *argv[CONFIG_SYS_MAXARGS + 1]; /* NULL terminated */
|
|
|
|
int argc;
|
|
|
|
static int next_step = -1;
|
|
|
|
|
|
|
|
if (next_step < 0 && step == STEP_DDR_RESET) {
|
|
|
|
#ifdef CONFIG_STM32MP1_DDR_INTERACTIVE_FORCE
|
|
|
|
gd->flags &= ~(GD_FLG_SILENT |
|
|
|
|
GD_FLG_DISABLE_CONSOLE);
|
|
|
|
next_step = STEP_DDR_RESET;
|
|
|
|
#else
|
|
|
|
unsigned long start = get_timer(0);
|
|
|
|
|
|
|
|
while (1) {
|
2020-10-07 16:11:48 +00:00
|
|
|
if (tstc() && (getchar() == 'd')) {
|
2019-04-10 12:09:27 +00:00
|
|
|
next_step = STEP_DDR_RESET;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
if (get_timer(start) > 100)
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
}
|
|
|
|
|
2020-11-06 18:01:36 +00:00
|
|
|
log_debug("** step %d ** %s / %d\n", step, step_str[step], next_step);
|
2019-04-10 12:09:27 +00:00
|
|
|
|
|
|
|
if (next_step < 0)
|
|
|
|
return false;
|
|
|
|
|
|
|
|
if (step < 0 || step > ARRAY_SIZE(step_str)) {
|
|
|
|
printf("** step %d ** INVALID\n", step);
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
printf("%d:%s\n", step, step_str[step]);
|
|
|
|
|
|
|
|
if (next_step > step)
|
|
|
|
return false;
|
|
|
|
|
|
|
|
while (next_step == step) {
|
2020-03-06 10:14:05 +00:00
|
|
|
cli_readline_into_buffer("DDR>", buffer, 0);
|
2019-04-10 12:09:27 +00:00
|
|
|
argc = cli_simple_parse_line(buffer, argv);
|
|
|
|
if (!argc)
|
|
|
|
continue;
|
|
|
|
|
|
|
|
switch (stm32mp1_get_command(argv[0], argc)) {
|
|
|
|
case DDR_CMD_HELP:
|
|
|
|
stm32mp1_do_usage();
|
|
|
|
break;
|
|
|
|
|
|
|
|
case DDR_CMD_INFO:
|
|
|
|
stm32mp1_do_info(priv,
|
|
|
|
(struct stm32mp1_ddr_config *)config,
|
|
|
|
step, argc, argv);
|
|
|
|
break;
|
|
|
|
|
|
|
|
case DDR_CMD_FREQ:
|
|
|
|
if (stm32mp1_do_freq(priv, argc, argv))
|
|
|
|
next_step = STEP_DDR_RESET;
|
|
|
|
break;
|
|
|
|
|
|
|
|
case DDR_CMD_RESET:
|
|
|
|
do_reset(NULL, 0, 0, NULL);
|
|
|
|
break;
|
|
|
|
|
|
|
|
case DDR_CMD_PARAM:
|
|
|
|
stm32mp1_do_param(step, config, argc, argv);
|
|
|
|
break;
|
|
|
|
|
|
|
|
case DDR_CMD_PRINT:
|
|
|
|
stm32mp1_do_print(priv, argc, argv);
|
|
|
|
break;
|
|
|
|
|
|
|
|
case DDR_CMD_EDIT:
|
|
|
|
stm32mp1_edit_reg(priv, argv[1], argv[2]);
|
|
|
|
break;
|
|
|
|
|
|
|
|
case DDR_CMD_GO:
|
|
|
|
next_step = STEP_RUN;
|
|
|
|
break;
|
|
|
|
|
|
|
|
case DDR_CMD_NEXT:
|
|
|
|
next_step = step + 1;
|
|
|
|
break;
|
|
|
|
|
|
|
|
case DDR_CMD_STEP:
|
|
|
|
next_step = stm32mp1_do_step(step, argc, argv);
|
|
|
|
break;
|
|
|
|
|
2019-04-10 12:09:28 +00:00
|
|
|
#ifdef CONFIG_STM32MP1_DDR_TESTS
|
|
|
|
case DDR_CMD_TEST:
|
|
|
|
if (!stm32mp1_check_step(step, STEP_DDR_READY))
|
|
|
|
continue;
|
|
|
|
stm32mp1_ddr_subcmd(priv, argc, argv, test, test_nb);
|
|
|
|
break;
|
|
|
|
#endif
|
|
|
|
|
2019-04-10 12:09:29 +00:00
|
|
|
#ifdef CONFIG_STM32MP1_DDR_TUNING
|
|
|
|
case DDR_CMD_TUNING:
|
|
|
|
if (!stm32mp1_check_step(step, STEP_DDR_READY))
|
|
|
|
continue;
|
|
|
|
stm32mp1_ddr_subcmd(priv, argc, argv,
|
|
|
|
tuning, tuning_nb);
|
|
|
|
break;
|
|
|
|
#endif
|
|
|
|
|
2019-04-10 12:09:27 +00:00
|
|
|
default:
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
return next_step == STEP_DDR_RESET;
|
|
|
|
}
|