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u-boot/drivers/clk/clk-uclass.c

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SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
2018-05-06 21:58:06 +00:00
// SPDX-License-Identifier: GPL-2.0+
dm: Add a clock uclass Clocks are an important feature of platforms and have become increasing complex with time. Most modern SoCs have multiple PLLs and dozens of clock dividers which distribute clocks to on-chip peripherals. Some SoC implementations have a clock API which is private to that SoC family, e.g. Tegra and Exynos. This is useful but it would be better to have a common API that can be understood and used throughout U-Boot. Add a simple clock API as a starting point. It supports querying and setting the rate of a clock. Each clock is a device. To reduce memory and processing overhead the concept of peripheral clocks is provided. These do not need to be explicit devices - it is possible to write a driver that can adjust the I2C clock (for example) without an explicit I2C clock device. This can dramatically reduce the number of devices (and associated overhead) in a complex SoC. Clocks are referenced by a number, and it is expected that SoCs will define that numbering themselves via an enum. Signed-off-by: Simon Glass <sjg@chromium.org>
2015-06-23 21:39:15 +00:00
/*
* Copyright (C) 2015 Google, Inc
* Written by Simon Glass <sjg@chromium.org>
clk: convert API to match reset/mailbox style The following changes are made to the clock API: * The concept of "clocks" and "peripheral clocks" are unified; each clock provider now implements a single set of clocks. This provides a simpler conceptual interface to clients, and better aligns with device tree clock bindings. * Clocks are now identified with a single "struct clk", rather than requiring clients to store the clock provider device and clock identity values separately. For simple clock consumers, this isolates clients from internal details of the clock API. * clk.h is split so it only contains the client/consumer API, whereas clk-uclass.h contains the provider API. This aligns with the recently added reset and mailbox APIs. * clk_ops .of_xlate(), .request(), and .free() are added so providers can customize these operations if needed. This also aligns with the recently added reset and mailbox APIs. * clk_disable() is added. * All users of the current clock APIs are updated. * Sandbox clock tests are updated to exercise clock lookup via DT, and clock enable/disable. * rkclk_get_clk() is removed and replaced with standard APIs. Buildman shows no clock-related errors for any board for which buildman can download a toolchain. test/py passes for sandbox (which invokes the dm clk test amongst others). Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org>
2016-06-17 15:44:00 +00:00
* Copyright (c) 2016, NVIDIA CORPORATION.
clk: implement clk_set_defaults() Linux uses the properties 'assigned-clocks', 'assigned-clock-parents' and 'assigned-clock-rates' to configure the clock subsystem for use with various peripheral nodes. This implements clk_set_defaults() and hooks it up with the general device probibin in drivers/core/device.c: when a new device is probed, clk_set_defaults() will be called for it and will process the properties mentioned above. Note that this functionality is designed to fail gracefully (i.e. if a clock-driver does not implement set_parent(), we simply accept this and ignore the error) as not to break existing board-support. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Tested-by: David Wu <david.wu@rock-chips.com> Series-changes: 2 - Fixed David's email address. Series-version: 2 Cover-letter: clk: support assigned-clock, assigned-clock-parents, assigned-clock-rates For various peripherals on Rockchip SoCs (e.g. for the Ethernet GMAC), the parent-clock needs to be set via the DTS. This adds the required plumbing and implements the GMAC case for the RK3399. END
2018-01-08 12:59:18 +00:00
* Copyright (c) 2018, Theobroma Systems Design und Consulting GmbH
dm: Add a clock uclass Clocks are an important feature of platforms and have become increasing complex with time. Most modern SoCs have multiple PLLs and dozens of clock dividers which distribute clocks to on-chip peripherals. Some SoC implementations have a clock API which is private to that SoC family, e.g. Tegra and Exynos. This is useful but it would be better to have a common API that can be understood and used throughout U-Boot. Add a simple clock API as a starting point. It supports querying and setting the rate of a clock. Each clock is a device. To reduce memory and processing overhead the concept of peripheral clocks is provided. These do not need to be explicit devices - it is possible to write a driver that can adjust the I2C clock (for example) without an explicit I2C clock device. This can dramatically reduce the number of devices (and associated overhead) in a complex SoC. Clocks are referenced by a number, and it is expected that SoCs will define that numbering themselves via an enum. Signed-off-by: Simon Glass <sjg@chromium.org>
2015-06-23 21:39:15 +00:00
*/
dm: define LOG_CATEGORY for all uclass Define LOG_CATEGORY for all uclass to allow filtering with log command. Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-04-27 09:02:19 +00:00
#define LOG_CATEGORY UCLASS_CLK
dm: Add a clock uclass Clocks are an important feature of platforms and have become increasing complex with time. Most modern SoCs have multiple PLLs and dozens of clock dividers which distribute clocks to on-chip peripherals. Some SoC implementations have a clock API which is private to that SoC family, e.g. Tegra and Exynos. This is useful but it would be better to have a common API that can be understood and used throughout U-Boot. Add a simple clock API as a starting point. It supports querying and setting the rate of a clock. Each clock is a device. To reduce memory and processing overhead the concept of peripheral clocks is provided. These do not need to be explicit devices - it is possible to write a driver that can adjust the I2C clock (for example) without an explicit I2C clock device. This can dramatically reduce the number of devices (and associated overhead) in a complex SoC. Clocks are referenced by a number, and it is expected that SoCs will define that numbering themselves via an enum. Signed-off-by: Simon Glass <sjg@chromium.org>
2015-06-23 21:39:15 +00:00
#include <common.h>
#include <clk.h>
clk: convert API to match reset/mailbox style The following changes are made to the clock API: * The concept of "clocks" and "peripheral clocks" are unified; each clock provider now implements a single set of clocks. This provides a simpler conceptual interface to clients, and better aligns with device tree clock bindings. * Clocks are now identified with a single "struct clk", rather than requiring clients to store the clock provider device and clock identity values separately. For simple clock consumers, this isolates clients from internal details of the clock API. * clk.h is split so it only contains the client/consumer API, whereas clk-uclass.h contains the provider API. This aligns with the recently added reset and mailbox APIs. * clk_ops .of_xlate(), .request(), and .free() are added so providers can customize these operations if needed. This also aligns with the recently added reset and mailbox APIs. * clk_disable() is added. * All users of the current clock APIs are updated. * Sandbox clock tests are updated to exercise clock lookup via DT, and clock enable/disable. * rkclk_get_clk() is removed and replaced with standard APIs. Buildman shows no clock-related errors for any board for which buildman can download a toolchain. test/py passes for sandbox (which invokes the dm clk test amongst others). Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org>
2016-06-17 15:44:00 +00:00
#include <clk-uclass.h>
dm: Add a clock uclass Clocks are an important feature of platforms and have become increasing complex with time. Most modern SoCs have multiple PLLs and dozens of clock dividers which distribute clocks to on-chip peripherals. Some SoC implementations have a clock API which is private to that SoC family, e.g. Tegra and Exynos. This is useful but it would be better to have a common API that can be understood and used throughout U-Boot. Add a simple clock API as a starting point. It supports querying and setting the rate of a clock. Each clock is a device. To reduce memory and processing overhead the concept of peripheral clocks is provided. These do not need to be explicit devices - it is possible to write a driver that can adjust the I2C clock (for example) without an explicit I2C clock device. This can dramatically reduce the number of devices (and associated overhead) in a complex SoC. Clocks are referenced by a number, and it is expected that SoCs will define that numbering themselves via an enum. Signed-off-by: Simon Glass <sjg@chromium.org>
2015-06-23 21:39:15 +00:00
#include <dm.h>
dm: clk: Add support for of-platdata Add support for this feature in the core clock code. Signed-off-by: Simon Glass <sjg@chromium.org>
2016-07-04 17:58:03 +00:00
#include <dt-structs.h>
dm: Add a clock uclass Clocks are an important feature of platforms and have become increasing complex with time. Most modern SoCs have multiple PLLs and dozens of clock dividers which distribute clocks to on-chip peripherals. Some SoC implementations have a clock API which is private to that SoC family, e.g. Tegra and Exynos. This is useful but it would be better to have a common API that can be understood and used throughout U-Boot. Add a simple clock API as a starting point. It supports querying and setting the rate of a clock. Each clock is a device. To reduce memory and processing overhead the concept of peripheral clocks is provided. These do not need to be explicit devices - it is possible to write a driver that can adjust the I2C clock (for example) without an explicit I2C clock device. This can dramatically reduce the number of devices (and associated overhead) in a complex SoC. Clocks are referenced by a number, and it is expected that SoCs will define that numbering themselves via an enum. Signed-off-by: Simon Glass <sjg@chromium.org>
2015-06-23 21:39:15 +00:00
#include <errno.h>
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-10 17:40:05 +00:00
#include <log.h>
dm: core: Create a new header file for 'compat' features At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-02-03 14:36:16 +00:00
#include <malloc.h>
clk: cosmetic: reorder include files Reorder include files in the U-Boot expected order: the common.h header should always be first, followed by other headers in order, then headers with directories, then local files. It is a preliminary step for next patch. Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Sean Anderson <seanga2@gmail.com>
2021-11-19 14:12:06 +00:00
#include <asm/global_data.h>
clk: Warn on failure to assign rate If the user/dev explicitly requests a clock be assigned a certain rate, then we should warn them if we can't do it. This makes it clear if the clock is running at the default rate. Signed-off-by: Sean Anderson <seanga2@gmail.com>
2021-04-09 02:13:03 +00:00
#include <dm/device_compat.h>
clk: bind clk to new parent device Clock re-parenting is not binding the clock's device to its new parent device, it only calls the clock's ops->set_parent() API. The changes in this commit re-parent the clock device to its new parent so that subsequent operations like clk_get_parent() to point to the proper parent. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2020-09-07 14:46:34 +00:00
#include <dm/device-internal.h>
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
2020-02-03 14:36:15 +00:00
#include <dm/devres.h>
#include <dm/read.h>
common: Drop linux/bug.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-10 17:40:08 +00:00
#include <linux/bug.h>
dm: clk: Define clk_get_parent() for clk operations This commit adds the clk_get_parent() function, which is responsible for getting the parent's struct clock pointer. U-Boot's DM support for getting parent is different (the parent relationship is in udevice) than the one in Common Clock Framework [CCF] in Linux. To obtain the pointer to struct clk of parent the pdev->uclass_priv field is read via dev_get_clk_ptr() wrapper. Signed-off-by: Lukasz Majewski <lukma@denx.de> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2019-06-24 13:50:42 +00:00
#include <linux/clk-provider.h>
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
2020-02-03 14:36:15 +00:00
#include <linux/err.h>
dm: Add a clock uclass Clocks are an important feature of platforms and have become increasing complex with time. Most modern SoCs have multiple PLLs and dozens of clock dividers which distribute clocks to on-chip peripherals. Some SoC implementations have a clock API which is private to that SoC family, e.g. Tegra and Exynos. This is useful but it would be better to have a common API that can be understood and used throughout U-Boot. Add a simple clock API as a starting point. It supports querying and setting the rate of a clock. Each clock is a device. To reduce memory and processing overhead the concept of peripheral clocks is provided. These do not need to be explicit devices - it is possible to write a driver that can adjust the I2C clock (for example) without an explicit I2C clock device. This can dramatically reduce the number of devices (and associated overhead) in a complex SoC. Clocks are referenced by a number, and it is expected that SoCs will define that numbering themselves via an enum. Signed-off-by: Simon Glass <sjg@chromium.org>
2015-06-23 21:39:15 +00:00
clk: clk-uclass: Fix style violations checkpatch.pl complains that the clk_ops structures used in clk-uclass.c ought to be const, so we mark them as const. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Mario Six <mario.six@gdsys.cc>
2018-01-15 10:06:51 +00:00
static inline const struct clk_ops *clk_dev_ops(struct udevice *dev)
dm: Add a clock uclass Clocks are an important feature of platforms and have become increasing complex with time. Most modern SoCs have multiple PLLs and dozens of clock dividers which distribute clocks to on-chip peripherals. Some SoC implementations have a clock API which is private to that SoC family, e.g. Tegra and Exynos. This is useful but it would be better to have a common API that can be understood and used throughout U-Boot. Add a simple clock API as a starting point. It supports querying and setting the rate of a clock. Each clock is a device. To reduce memory and processing overhead the concept of peripheral clocks is provided. These do not need to be explicit devices - it is possible to write a driver that can adjust the I2C clock (for example) without an explicit I2C clock device. This can dramatically reduce the number of devices (and associated overhead) in a complex SoC. Clocks are referenced by a number, and it is expected that SoCs will define that numbering themselves via an enum. Signed-off-by: Simon Glass <sjg@chromium.org>
2015-06-23 21:39:15 +00:00
{
clk: clk-uclass: Fix style violations checkpatch.pl complains that the clk_ops structures used in clk-uclass.c ought to be const, so we mark them as const. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Mario Six <mario.six@gdsys.cc>
2018-01-15 10:06:51 +00:00
return (const struct clk_ops *)dev->driver->ops;
dm: Add a clock uclass Clocks are an important feature of platforms and have become increasing complex with time. Most modern SoCs have multiple PLLs and dozens of clock dividers which distribute clocks to on-chip peripherals. Some SoC implementations have a clock API which is private to that SoC family, e.g. Tegra and Exynos. This is useful but it would be better to have a common API that can be understood and used throughout U-Boot. Add a simple clock API as a starting point. It supports querying and setting the rate of a clock. Each clock is a device. To reduce memory and processing overhead the concept of peripheral clocks is provided. These do not need to be explicit devices - it is possible to write a driver that can adjust the I2C clock (for example) without an explicit I2C clock device. This can dramatically reduce the number of devices (and associated overhead) in a complex SoC. Clocks are referenced by a number, and it is expected that SoCs will define that numbering themselves via an enum. Signed-off-by: Simon Glass <sjg@chromium.org>
2015-06-23 21:39:15 +00:00
}
clk: Drop dm.h header file in clk-provider.h This header file should not be included in other header files. Remove it and use a forward declaration and un-inlining of dev_get_clk_ptr() instead. Fix up the kendryte header files to avoid build errors. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Sean Anderson <seanga2@gmail.com>
2020-07-19 16:15:56 +00:00
struct clk *dev_get_clk_ptr(struct udevice *dev)
{
return (struct clk *)dev_get_uclass_priv(dev);
}
treewide: Simply conditions with the new OF_REAL Use this new Kconfig to simplify the compilation conditions where appropriate. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-08-07 13:24:03 +00:00
#if CONFIG_IS_ENABLED(OF_PLATDATA)
clk: Rename clk_get_by_driver_info() This is actually a misnomer now, since the phandle info may contain a driver_info index or a udevice index. Rename it to use the word 'phandle', which seems more accurate. Add a comment while we are here. Also add a test for this function. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-08-07 13:24:09 +00:00
int clk_get_by_phandle(struct udevice *dev, const struct phandle_1_arg *cells,
struct clk *clk)
dm: clk: Add support for of-platdata Add support for this feature in the core clock code. Signed-off-by: Simon Glass <sjg@chromium.org>
2016-07-04 17:58:03 +00:00
{
int ret;
dm: Rename device_get_by_driver_info_idx() This function finds a device by its driver_info index. With of-platdata-inst we do not use driver_info, but instead instantiate udevice records at build-time. However the semantics of using the function are the same in each case: the caller provides an index and gets back a device. So rename the function to device_get_by_ofplat_idx(), so that it can be used for both situations. The caller does not really need to worry about the details. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
2021-03-15 04:25:28 +00:00
ret = device_get_by_ofplat_idx(cells->idx, &clk->dev);
dm: clk: Add support for of-platdata Add support for this feature in the core clock code. Signed-off-by: Simon Glass <sjg@chromium.org>
2016-07-04 17:58:03 +00:00
if (ret)
return ret;
dtoc: extend dtoc to use struct driver_info when linking nodes In the current implementation, when dtoc parses a dtb to generate a struct platdata it converts the information related to linked nodes as pointers to struct platdata of destination nodes. By doing this, it makes difficult to get pointer to udevices created based on these information. This patch extends dtoc to use struct driver_info when populating information about linked nodes, which makes it easier to later get the devices created. In this context, reimplement functions like clk_get_by_index_platdata() which made use of the previous approach. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2020-06-25 04:10:13 +00:00
clk->id = cells->arg[0];
dm: clk: Add support for of-platdata Add support for this feature in the core clock code. Signed-off-by: Simon Glass <sjg@chromium.org>
2016-07-04 17:58:03 +00:00
return 0;
}
treewide: Simply conditions with the new OF_REAL Use this new Kconfig to simplify the compilation conditions where appropriate. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-08-07 13:24:03 +00:00
#endif
#if CONFIG_IS_ENABLED(OF_REAL)
clk: convert API to match reset/mailbox style The following changes are made to the clock API: * The concept of "clocks" and "peripheral clocks" are unified; each clock provider now implements a single set of clocks. This provides a simpler conceptual interface to clients, and better aligns with device tree clock bindings. * Clocks are now identified with a single "struct clk", rather than requiring clients to store the clock provider device and clock identity values separately. For simple clock consumers, this isolates clients from internal details of the clock API. * clk.h is split so it only contains the client/consumer API, whereas clk-uclass.h contains the provider API. This aligns with the recently added reset and mailbox APIs. * clk_ops .of_xlate(), .request(), and .free() are added so providers can customize these operations if needed. This also aligns with the recently added reset and mailbox APIs. * clk_disable() is added. * All users of the current clock APIs are updated. * Sandbox clock tests are updated to exercise clock lookup via DT, and clock enable/disable. * rkclk_get_clk() is removed and replaced with standard APIs. Buildman shows no clock-related errors for any board for which buildman can download a toolchain. test/py passes for sandbox (which invokes the dm clk test amongst others). Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org>
2016-06-17 15:44:00 +00:00
static int clk_of_xlate_default(struct clk *clk,
clk: Modify xlate() method for livetree Update the xlate() method to use ofnode_phandle_args instead of the fdtdec variant. This will allow drivers to support a live device tree. Signed-off-by: Simon Glass <sjg@chromium.org>
2017-05-19 02:09:40 +00:00
struct ofnode_phandle_args *args)
dm: Add a clock uclass Clocks are an important feature of platforms and have become increasing complex with time. Most modern SoCs have multiple PLLs and dozens of clock dividers which distribute clocks to on-chip peripherals. Some SoC implementations have a clock API which is private to that SoC family, e.g. Tegra and Exynos. This is useful but it would be better to have a common API that can be understood and used throughout U-Boot. Add a simple clock API as a starting point. It supports querying and setting the rate of a clock. Each clock is a device. To reduce memory and processing overhead the concept of peripheral clocks is provided. These do not need to be explicit devices - it is possible to write a driver that can adjust the I2C clock (for example) without an explicit I2C clock device. This can dramatically reduce the number of devices (and associated overhead) in a complex SoC. Clocks are referenced by a number, and it is expected that SoCs will define that numbering themselves via an enum. Signed-off-by: Simon Glass <sjg@chromium.org>
2015-06-23 21:39:15 +00:00
{
clk: convert API to match reset/mailbox style The following changes are made to the clock API: * The concept of "clocks" and "peripheral clocks" are unified; each clock provider now implements a single set of clocks. This provides a simpler conceptual interface to clients, and better aligns with device tree clock bindings. * Clocks are now identified with a single "struct clk", rather than requiring clients to store the clock provider device and clock identity values separately. For simple clock consumers, this isolates clients from internal details of the clock API. * clk.h is split so it only contains the client/consumer API, whereas clk-uclass.h contains the provider API. This aligns with the recently added reset and mailbox APIs. * clk_ops .of_xlate(), .request(), and .free() are added so providers can customize these operations if needed. This also aligns with the recently added reset and mailbox APIs. * clk_disable() is added. * All users of the current clock APIs are updated. * Sandbox clock tests are updated to exercise clock lookup via DT, and clock enable/disable. * rkclk_get_clk() is removed and replaced with standard APIs. Buildman shows no clock-related errors for any board for which buildman can download a toolchain. test/py passes for sandbox (which invokes the dm clk test amongst others). Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org>
2016-06-17 15:44:00 +00:00
debug("%s(clk=%p)\n", __func__, clk);
dm: Add a clock uclass Clocks are an important feature of platforms and have become increasing complex with time. Most modern SoCs have multiple PLLs and dozens of clock dividers which distribute clocks to on-chip peripherals. Some SoC implementations have a clock API which is private to that SoC family, e.g. Tegra and Exynos. This is useful but it would be better to have a common API that can be understood and used throughout U-Boot. Add a simple clock API as a starting point. It supports querying and setting the rate of a clock. Each clock is a device. To reduce memory and processing overhead the concept of peripheral clocks is provided. These do not need to be explicit devices - it is possible to write a driver that can adjust the I2C clock (for example) without an explicit I2C clock device. This can dramatically reduce the number of devices (and associated overhead) in a complex SoC. Clocks are referenced by a number, and it is expected that SoCs will define that numbering themselves via an enum. Signed-off-by: Simon Glass <sjg@chromium.org>
2015-06-23 21:39:15 +00:00
clk: convert API to match reset/mailbox style The following changes are made to the clock API: * The concept of "clocks" and "peripheral clocks" are unified; each clock provider now implements a single set of clocks. This provides a simpler conceptual interface to clients, and better aligns with device tree clock bindings. * Clocks are now identified with a single "struct clk", rather than requiring clients to store the clock provider device and clock identity values separately. For simple clock consumers, this isolates clients from internal details of the clock API. * clk.h is split so it only contains the client/consumer API, whereas clk-uclass.h contains the provider API. This aligns with the recently added reset and mailbox APIs. * clk_ops .of_xlate(), .request(), and .free() are added so providers can customize these operations if needed. This also aligns with the recently added reset and mailbox APIs. * clk_disable() is added. * All users of the current clock APIs are updated. * Sandbox clock tests are updated to exercise clock lookup via DT, and clock enable/disable. * rkclk_get_clk() is removed and replaced with standard APIs. Buildman shows no clock-related errors for any board for which buildman can download a toolchain. test/py passes for sandbox (which invokes the dm clk test amongst others). Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org>
2016-06-17 15:44:00 +00:00
if (args->args_count > 1) {
treewide: invaild -> invalid Somewhere along the way, someone misspelt "invalid" and it got copied everywhere. Fix it. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Alexander Dahl <ada@thorsis.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-12-01 19:26:53 +00:00
debug("Invalid args_count: %d\n", args->args_count);
clk: convert API to match reset/mailbox style The following changes are made to the clock API: * The concept of "clocks" and "peripheral clocks" are unified; each clock provider now implements a single set of clocks. This provides a simpler conceptual interface to clients, and better aligns with device tree clock bindings. * Clocks are now identified with a single "struct clk", rather than requiring clients to store the clock provider device and clock identity values separately. For simple clock consumers, this isolates clients from internal details of the clock API. * clk.h is split so it only contains the client/consumer API, whereas clk-uclass.h contains the provider API. This aligns with the recently added reset and mailbox APIs. * clk_ops .of_xlate(), .request(), and .free() are added so providers can customize these operations if needed. This also aligns with the recently added reset and mailbox APIs. * clk_disable() is added. * All users of the current clock APIs are updated. * Sandbox clock tests are updated to exercise clock lookup via DT, and clock enable/disable. * rkclk_get_clk() is removed and replaced with standard APIs. Buildman shows no clock-related errors for any board for which buildman can download a toolchain. test/py passes for sandbox (which invokes the dm clk test amongst others). Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org>
2016-06-17 15:44:00 +00:00
return -EINVAL;
}
dm: Add a clock uclass Clocks are an important feature of platforms and have become increasing complex with time. Most modern SoCs have multiple PLLs and dozens of clock dividers which distribute clocks to on-chip peripherals. Some SoC implementations have a clock API which is private to that SoC family, e.g. Tegra and Exynos. This is useful but it would be better to have a common API that can be understood and used throughout U-Boot. Add a simple clock API as a starting point. It supports querying and setting the rate of a clock. Each clock is a device. To reduce memory and processing overhead the concept of peripheral clocks is provided. These do not need to be explicit devices - it is possible to write a driver that can adjust the I2C clock (for example) without an explicit I2C clock device. This can dramatically reduce the number of devices (and associated overhead) in a complex SoC. Clocks are referenced by a number, and it is expected that SoCs will define that numbering themselves via an enum. Signed-off-by: Simon Glass <sjg@chromium.org>
2015-06-23 21:39:15 +00:00
clk: convert API to match reset/mailbox style The following changes are made to the clock API: * The concept of "clocks" and "peripheral clocks" are unified; each clock provider now implements a single set of clocks. This provides a simpler conceptual interface to clients, and better aligns with device tree clock bindings. * Clocks are now identified with a single "struct clk", rather than requiring clients to store the clock provider device and clock identity values separately. For simple clock consumers, this isolates clients from internal details of the clock API. * clk.h is split so it only contains the client/consumer API, whereas clk-uclass.h contains the provider API. This aligns with the recently added reset and mailbox APIs. * clk_ops .of_xlate(), .request(), and .free() are added so providers can customize these operations if needed. This also aligns with the recently added reset and mailbox APIs. * clk_disable() is added. * All users of the current clock APIs are updated. * Sandbox clock tests are updated to exercise clock lookup via DT, and clock enable/disable. * rkclk_get_clk() is removed and replaced with standard APIs. Buildman shows no clock-related errors for any board for which buildman can download a toolchain. test/py passes for sandbox (which invokes the dm clk test amongst others). Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org>
2016-06-17 15:44:00 +00:00
if (args->args_count)
clk->id = args->args[0];
else
clk->id = 0;
dm: Add a clock uclass Clocks are an important feature of platforms and have become increasing complex with time. Most modern SoCs have multiple PLLs and dozens of clock dividers which distribute clocks to on-chip peripherals. Some SoC implementations have a clock API which is private to that SoC family, e.g. Tegra and Exynos. This is useful but it would be better to have a common API that can be understood and used throughout U-Boot. Add a simple clock API as a starting point. It supports querying and setting the rate of a clock. Each clock is a device. To reduce memory and processing overhead the concept of peripheral clocks is provided. These do not need to be explicit devices - it is possible to write a driver that can adjust the I2C clock (for example) without an explicit I2C clock device. This can dramatically reduce the number of devices (and associated overhead) in a complex SoC. Clocks are referenced by a number, and it is expected that SoCs will define that numbering themselves via an enum. Signed-off-by: Simon Glass <sjg@chromium.org>
2015-06-23 21:39:15 +00:00
clk: initialize clk->data when using default xlate Right now when using clk_of_xlate_default(), clk->data remains un-initialized because clk_get_bulk() does not initialize memory on allocation of clock structure. This can cause problems when data is used to match if two clocks pointers are exactly the same underlying clocks, for example. Fix it by initializing clk->data to 0. Suggested-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com>
2019-07-11 09:00:24 +00:00
clk->data = 0;
clk: convert API to match reset/mailbox style The following changes are made to the clock API: * The concept of "clocks" and "peripheral clocks" are unified; each clock provider now implements a single set of clocks. This provides a simpler conceptual interface to clients, and better aligns with device tree clock bindings. * Clocks are now identified with a single "struct clk", rather than requiring clients to store the clock provider device and clock identity values separately. For simple clock consumers, this isolates clients from internal details of the clock API. * clk.h is split so it only contains the client/consumer API, whereas clk-uclass.h contains the provider API. This aligns with the recently added reset and mailbox APIs. * clk_ops .of_xlate(), .request(), and .free() are added so providers can customize these operations if needed. This also aligns with the recently added reset and mailbox APIs. * clk_disable() is added. * All users of the current clock APIs are updated. * Sandbox clock tests are updated to exercise clock lookup via DT, and clock enable/disable. * rkclk_get_clk() is removed and replaced with standard APIs. Buildman shows no clock-related errors for any board for which buildman can download a toolchain. test/py passes for sandbox (which invokes the dm clk test amongst others). Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org>
2016-06-17 15:44:00 +00:00
return 0;
dm: Add a clock uclass Clocks are an important feature of platforms and have become increasing complex with time. Most modern SoCs have multiple PLLs and dozens of clock dividers which distribute clocks to on-chip peripherals. Some SoC implementations have a clock API which is private to that SoC family, e.g. Tegra and Exynos. This is useful but it would be better to have a common API that can be understood and used throughout U-Boot. Add a simple clock API as a starting point. It supports querying and setting the rate of a clock. Each clock is a device. To reduce memory and processing overhead the concept of peripheral clocks is provided. These do not need to be explicit devices - it is possible to write a driver that can adjust the I2C clock (for example) without an explicit I2C clock device. This can dramatically reduce the number of devices (and associated overhead) in a complex SoC. Clocks are referenced by a number, and it is expected that SoCs will define that numbering themselves via an enum. Signed-off-by: Simon Glass <sjg@chromium.org>
2015-06-23 21:39:15 +00:00
}
clk: Get the CLK by index without device Getting a CLK by index with device is not straight forward for some use-cases like handling clock operations for child node in parent driver. So we need to process the child node in parent probe via ofnode and process CLK operation for child without udevice but with ofnode. So add clk_get_by_index_nodev() and move the common code in clk_get_by_index_tail() to use for clk_get_by_index() Cc: Stephen Warren <swarren@nvidia.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2019-02-27 18:56:52 +00:00
static int clk_get_by_index_tail(int ret, ofnode node,
struct ofnode_phandle_args *args,
const char *list_name, int index,
struct clk *clk)
{
struct udevice *dev_clk;
const struct clk_ops *ops;
assert(clk);
clk->dev = NULL;
if (ret)
goto err;
ret = uclass_get_device_by_ofnode(UCLASS_CLK, args->node, &dev_clk);
if (ret) {
debug("%s: uclass_get_device_by_of_offset failed: err=%d\n",
__func__, ret);
clk: Add debugging for return values Use the log_msg_ret() mechanism to get error-return information when clocks fail to probe, etc. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-01-21 20:57:11 +00:00
return log_msg_ret("get", ret);
clk: Get the CLK by index without device Getting a CLK by index with device is not straight forward for some use-cases like handling clock operations for child node in parent driver. So we need to process the child node in parent probe via ofnode and process CLK operation for child without udevice but with ofnode. So add clk_get_by_index_nodev() and move the common code in clk_get_by_index_tail() to use for clk_get_by_index() Cc: Stephen Warren <swarren@nvidia.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2019-02-27 18:56:52 +00:00
}
clk->dev = dev_clk;
ops = clk_dev_ops(dev_clk);
if (ops->of_xlate)
ret = ops->of_xlate(clk, args);
else
ret = clk_of_xlate_default(clk, args);
if (ret) {
debug("of_xlate() failed: %d\n", ret);
clk: Add debugging for return values Use the log_msg_ret() mechanism to get error-return information when clocks fail to probe, etc. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-01-21 20:57:11 +00:00
return log_msg_ret("xlate", ret);
clk: Get the CLK by index without device Getting a CLK by index with device is not straight forward for some use-cases like handling clock operations for child node in parent driver. So we need to process the child node in parent probe via ofnode and process CLK operation for child without udevice but with ofnode. So add clk_get_by_index_nodev() and move the common code in clk_get_by_index_tail() to use for clk_get_by_index() Cc: Stephen Warren <swarren@nvidia.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2019-02-27 18:56:52 +00:00
}
return clk_request(dev_clk, clk);
err:
debug("%s: Node '%s', property '%s', failed to request CLK index %d: %d\n",
__func__, ofnode_get_name(node), list_name, index, ret);
clk: Add debugging for return values Use the log_msg_ret() mechanism to get error-return information when clocks fail to probe, etc. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-01-21 20:57:11 +00:00
return log_msg_ret("prop", ret);
clk: Get the CLK by index without device Getting a CLK by index with device is not straight forward for some use-cases like handling clock operations for child node in parent driver. So we need to process the child node in parent probe via ofnode and process CLK operation for child without udevice but with ofnode. So add clk_get_by_index_nodev() and move the common code in clk_get_by_index_tail() to use for clk_get_by_index() Cc: Stephen Warren <swarren@nvidia.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2019-02-27 18:56:52 +00:00
}
clk: refactor clk_get_by_index() into clk_get_by_indexed_prop() The logic in clk_get_by_index() may be useful for other properties than 'clocks': e.g. 'assigned-clocks' and 'assigned-clock-parents' follows the same model. This commit refactors clk_get_by_index() by introducing an internal function clk_get_by_indexed_prop() that allows to specify the name of the property to process. The original clk_get_by_index() call is simply directed through this helper function with the property name fixed to "clocks". Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Tested-by: David Wu <david.wu@rock-chips.com> Series-changes: 2 - Fixed David's email address.
2018-01-08 10:18:18 +00:00
static int clk_get_by_indexed_prop(struct udevice *dev, const char *prop_name,
int index, struct clk *clk)
dm: clk: Add support for decoding clocks from the device tree Add a method which can locate a clock for a device, given its index. This uses the normal device tree bindings to return the clock device and the first argument which is normally used as a peripheral ID in U-Boot. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-01-21 02:43:02 +00:00
{
int ret;
dm: clk: Update uclass to support livetree Update the clk uclass to support a live device tree. Signed-off-by: Simon Glass <sjg@chromium.org>
2017-05-31 03:47:29 +00:00
struct ofnode_phandle_args args;
clk: convert API to match reset/mailbox style The following changes are made to the clock API: * The concept of "clocks" and "peripheral clocks" are unified; each clock provider now implements a single set of clocks. This provides a simpler conceptual interface to clients, and better aligns with device tree clock bindings. * Clocks are now identified with a single "struct clk", rather than requiring clients to store the clock provider device and clock identity values separately. For simple clock consumers, this isolates clients from internal details of the clock API. * clk.h is split so it only contains the client/consumer API, whereas clk-uclass.h contains the provider API. This aligns with the recently added reset and mailbox APIs. * clk_ops .of_xlate(), .request(), and .free() are added so providers can customize these operations if needed. This also aligns with the recently added reset and mailbox APIs. * clk_disable() is added. * All users of the current clock APIs are updated. * Sandbox clock tests are updated to exercise clock lookup via DT, and clock enable/disable. * rkclk_get_clk() is removed and replaced with standard APIs. Buildman shows no clock-related errors for any board for which buildman can download a toolchain. test/py passes for sandbox (which invokes the dm clk test amongst others). Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org>
2016-06-17 15:44:00 +00:00
debug("%s(dev=%p, index=%d, clk=%p)\n", __func__, dev, index, clk);
dm: clk: Add support for decoding clocks from the device tree Add a method which can locate a clock for a device, given its index. This uses the normal device tree bindings to return the clock device and the first argument which is normally used as a peripheral ID in U-Boot. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-01-21 02:43:02 +00:00
clk: convert API to match reset/mailbox style The following changes are made to the clock API: * The concept of "clocks" and "peripheral clocks" are unified; each clock provider now implements a single set of clocks. This provides a simpler conceptual interface to clients, and better aligns with device tree clock bindings. * Clocks are now identified with a single "struct clk", rather than requiring clients to store the clock provider device and clock identity values separately. For simple clock consumers, this isolates clients from internal details of the clock API. * clk.h is split so it only contains the client/consumer API, whereas clk-uclass.h contains the provider API. This aligns with the recently added reset and mailbox APIs. * clk_ops .of_xlate(), .request(), and .free() are added so providers can customize these operations if needed. This also aligns with the recently added reset and mailbox APIs. * clk_disable() is added. * All users of the current clock APIs are updated. * Sandbox clock tests are updated to exercise clock lookup via DT, and clock enable/disable. * rkclk_get_clk() is removed and replaced with standard APIs. Buildman shows no clock-related errors for any board for which buildman can download a toolchain. test/py passes for sandbox (which invokes the dm clk test amongst others). Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org>
2016-06-17 15:44:00 +00:00
assert(clk);
clk: add clk_release_all() Add clk_release_all() method which Disable/Free an array of clocks that has been previously requested by clk_request/get_by_*() Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-18 09:57:07 +00:00
clk->dev = NULL;
clk: refactor clk_get_by_index() into clk_get_by_indexed_prop() The logic in clk_get_by_index() may be useful for other properties than 'clocks': e.g. 'assigned-clocks' and 'assigned-clock-parents' follows the same model. This commit refactors clk_get_by_index() by introducing an internal function clk_get_by_indexed_prop() that allows to specify the name of the property to process. The original clk_get_by_index() call is simply directed through this helper function with the property name fixed to "clocks". Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Tested-by: David Wu <david.wu@rock-chips.com> Series-changes: 2 - Fixed David's email address.
2018-01-08 10:18:18 +00:00
ret = dev_read_phandle_with_args(dev, prop_name, "#clock-cells", 0,
clk: clk-uclass: Fix style violations checkpatch.pl complains that the clk_ops structures used in clk-uclass.c ought to be const, so we mark them as const. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Mario Six <mario.six@gdsys.cc>
2018-01-15 10:06:51 +00:00
index, &args);
dm: clk: Add support for decoding clocks from the device tree Add a method which can locate a clock for a device, given its index. This uses the normal device tree bindings to return the clock device and the first argument which is normally used as a peripheral ID in U-Boot. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-01-21 02:43:02 +00:00
if (ret) {
debug("%s: fdtdec_parse_phandle_with_args failed: err=%d\n",
__func__, ret);
clk: Add debugging for return values Use the log_msg_ret() mechanism to get error-return information when clocks fail to probe, etc. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-01-21 20:57:11 +00:00
return log_ret(ret);
dm: clk: Add support for decoding clocks from the device tree Add a method which can locate a clock for a device, given its index. This uses the normal device tree bindings to return the clock device and the first argument which is normally used as a peripheral ID in U-Boot. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-01-21 02:43:02 +00:00
}
clk: convert API to match reset/mailbox style The following changes are made to the clock API: * The concept of "clocks" and "peripheral clocks" are unified; each clock provider now implements a single set of clocks. This provides a simpler conceptual interface to clients, and better aligns with device tree clock bindings. * Clocks are now identified with a single "struct clk", rather than requiring clients to store the clock provider device and clock identity values separately. For simple clock consumers, this isolates clients from internal details of the clock API. * clk.h is split so it only contains the client/consumer API, whereas clk-uclass.h contains the provider API. This aligns with the recently added reset and mailbox APIs. * clk_ops .of_xlate(), .request(), and .free() are added so providers can customize these operations if needed. This also aligns with the recently added reset and mailbox APIs. * clk_disable() is added. * All users of the current clock APIs are updated. * Sandbox clock tests are updated to exercise clock lookup via DT, and clock enable/disable. * rkclk_get_clk() is removed and replaced with standard APIs. Buildman shows no clock-related errors for any board for which buildman can download a toolchain. test/py passes for sandbox (which invokes the dm clk test amongst others). Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org>
2016-06-17 15:44:00 +00:00
clk: Use clk_get_by_index_tail() clk_get_by_index_tail() now handle common clk get by index code so use it from clk_get_by_indexed_prop(). Cc: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2019-02-27 18:56:53 +00:00
return clk_get_by_index_tail(ret, dev_ofnode(dev), &args, "clocks",
clk: Fix clk_get_by_* handling of index clk_get_by_index_nodev only ever fetched clock 1, due to passing a boolean predicate instead of the index. Other clk_get_by_* functions got the clock correctly, but passed a predicate instead of the index to clk_get_by_tail. This could lead to confusing error messages. Signed-off-by: Sean Anderson <seanga2@gmail.com> CC: Lukasz Majewski <lukma@denx.de>
2020-06-24 10:41:08 +00:00
index, clk);
clk: convert API to match reset/mailbox style The following changes are made to the clock API: * The concept of "clocks" and "peripheral clocks" are unified; each clock provider now implements a single set of clocks. This provides a simpler conceptual interface to clients, and better aligns with device tree clock bindings. * Clocks are now identified with a single "struct clk", rather than requiring clients to store the clock provider device and clock identity values separately. For simple clock consumers, this isolates clients from internal details of the clock API. * clk.h is split so it only contains the client/consumer API, whereas clk-uclass.h contains the provider API. This aligns with the recently added reset and mailbox APIs. * clk_ops .of_xlate(), .request(), and .free() are added so providers can customize these operations if needed. This also aligns with the recently added reset and mailbox APIs. * clk_disable() is added. * All users of the current clock APIs are updated. * Sandbox clock tests are updated to exercise clock lookup via DT, and clock enable/disable. * rkclk_get_clk() is removed and replaced with standard APIs. Buildman shows no clock-related errors for any board for which buildman can download a toolchain. test/py passes for sandbox (which invokes the dm clk test amongst others). Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org>
2016-06-17 15:44:00 +00:00
}
clk: refactor clk_get_by_index() into clk_get_by_indexed_prop() The logic in clk_get_by_index() may be useful for other properties than 'clocks': e.g. 'assigned-clocks' and 'assigned-clock-parents' follows the same model. This commit refactors clk_get_by_index() by introducing an internal function clk_get_by_indexed_prop() that allows to specify the name of the property to process. The original clk_get_by_index() call is simply directed through this helper function with the property name fixed to "clocks". Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Tested-by: David Wu <david.wu@rock-chips.com> Series-changes: 2 - Fixed David's email address.
2018-01-08 10:18:18 +00:00
int clk_get_by_index(struct udevice *dev, int index, struct clk *clk)
{
clk: Consolidate some clock functions These functions are exactly the same as their "nodev" varients, except they accept a device and not an ofnode. Rewrite them to just call the other function. Signed-off-by: Sean Anderson <seanga2@gmail.com> Link: https://lore.kernel.org/r/20220227190113.1617498-1-seanga2@gmail.com
2022-02-27 19:01:13 +00:00
return clk_get_by_index_nodev(dev_ofnode(dev), index, clk);
clk: Get the CLK by index without device Getting a CLK by index with device is not straight forward for some use-cases like handling clock operations for child node in parent driver. So we need to process the child node in parent probe via ofnode and process CLK operation for child without udevice but with ofnode. So add clk_get_by_index_nodev() and move the common code in clk_get_by_index_tail() to use for clk_get_by_index() Cc: Stephen Warren <swarren@nvidia.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2019-02-27 18:56:52 +00:00
}
int clk_get_by_index_nodev(ofnode node, int index, struct clk *clk)
{
struct ofnode_phandle_args args;
int ret;
ret = ofnode_parse_phandle_with_args(node, "clocks", "#clock-cells", 0,
clk: Fix clk_get_by_* handling of index clk_get_by_index_nodev only ever fetched clock 1, due to passing a boolean predicate instead of the index. Other clk_get_by_* functions got the clock correctly, but passed a predicate instead of the index to clk_get_by_tail. This could lead to confusing error messages. Signed-off-by: Sean Anderson <seanga2@gmail.com> CC: Lukasz Majewski <lukma@denx.de>
2020-06-24 10:41:08 +00:00
index, &args);
clk: Get the CLK by index without device Getting a CLK by index with device is not straight forward for some use-cases like handling clock operations for child node in parent driver. So we need to process the child node in parent probe via ofnode and process CLK operation for child without udevice but with ofnode. So add clk_get_by_index_nodev() and move the common code in clk_get_by_index_tail() to use for clk_get_by_index() Cc: Stephen Warren <swarren@nvidia.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2019-02-27 18:56:52 +00:00
return clk_get_by_index_tail(ret, node, &args, "clocks",
clk: Fix clk_get_by_* handling of index clk_get_by_index_nodev only ever fetched clock 1, due to passing a boolean predicate instead of the index. Other clk_get_by_* functions got the clock correctly, but passed a predicate instead of the index to clk_get_by_tail. This could lead to confusing error messages. Signed-off-by: Sean Anderson <seanga2@gmail.com> CC: Lukasz Majewski <lukma@denx.de>
2020-06-24 10:41:08 +00:00
index, clk);
clk: refactor clk_get_by_index() into clk_get_by_indexed_prop() The logic in clk_get_by_index() may be useful for other properties than 'clocks': e.g. 'assigned-clocks' and 'assigned-clock-parents' follows the same model. This commit refactors clk_get_by_index() by introducing an internal function clk_get_by_indexed_prop() that allows to specify the name of the property to process. The original clk_get_by_index() call is simply directed through this helper function with the property name fixed to "clocks". Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Tested-by: David Wu <david.wu@rock-chips.com> Series-changes: 2 - Fixed David's email address.
2018-01-08 10:18:18 +00:00
}
clk: implement clk_set_defaults() Linux uses the properties 'assigned-clocks', 'assigned-clock-parents' and 'assigned-clock-rates' to configure the clock subsystem for use with various peripheral nodes. This implements clk_set_defaults() and hooks it up with the general device probibin in drivers/core/device.c: when a new device is probed, clk_set_defaults() will be called for it and will process the properties mentioned above. Note that this functionality is designed to fail gracefully (i.e. if a clock-driver does not implement set_parent(), we simply accept this and ignore the error) as not to break existing board-support. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Tested-by: David Wu <david.wu@rock-chips.com> Series-changes: 2 - Fixed David's email address. Series-version: 2 Cover-letter: clk: support assigned-clock, assigned-clock-parents, assigned-clock-rates For various peripherals on Rockchip SoCs (e.g. for the Ethernet GMAC), the parent-clock needs to be set via the DTS. This adds the required plumbing and implements the GMAC case for the RK3399. END
2018-01-08 12:59:18 +00:00
clk: Add get/enable/disable/release for a bulk of clocks This patch adds a "bulk" API to the clock API in order to get/enable/disable /release a group of clocks associated with a device. This bulk API will avoid adding a copy of the same code to manage a group of clocks in drivers. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2018-04-03 09:44:18 +00:00
int clk_get_bulk(struct udevice *dev, struct clk_bulk *bulk)
{
int i, ret, err, count;
clk: cosmetic change in uclass Remove the tab in clk_get_bulk to respect the coding rules. Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2021-04-27 08:57:54 +00:00
clk: Add get/enable/disable/release for a bulk of clocks This patch adds a "bulk" API to the clock API in order to get/enable/disable /release a group of clocks associated with a device. This bulk API will avoid adding a copy of the same code to manage a group of clocks in drivers. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2018-04-03 09:44:18 +00:00
bulk->count = 0;
dm: add cells_count parameter in *_count_phandle_with_args The cell_count argument is required when cells_name is NULL. This patch adds this parameter in live tree API - of_count_phandle_with_args - ofnode_count_phandle_with_args - dev_count_phandle_with_args This parameter solves issue when these API is used to count the number of element of a cell without cell name. This parameter allow to force the size cell. For example: count = dev_count_phandle_with_args(dev, "array", NULL, 3); Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2020-09-25 07:41:14 +00:00
count = dev_count_phandle_with_args(dev, "clocks", "#clock-cells", 0);
clk: fix clk_get_bulk when phandle error This fixes the Coverity Defect CID 175347 when dev_count_phandle_with_args() returns a negative value. Fixes: a855be87da49 ("clk: Add get/enable/disable/release for a bulk of clocks") Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2018-04-17 09:30:31 +00:00
if (count < 1)
return count;
clk: Add get/enable/disable/release for a bulk of clocks This patch adds a "bulk" API to the clock API in order to get/enable/disable /release a group of clocks associated with a device. This bulk API will avoid adding a copy of the same code to manage a group of clocks in drivers. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2018-04-03 09:44:18 +00:00
bulk->clks = devm_kcalloc(dev, count, sizeof(struct clk), GFP_KERNEL);
if (!bulk->clks)
return -ENOMEM;
for (i = 0; i < count; i++) {
ret = clk_get_by_index(dev, i, &bulk->clks[i]);
if (ret < 0)
goto bulk_get_err;
++bulk->count;
}
return 0;
bulk_get_err:
err = clk_release_all(bulk->clks, bulk->count);
if (err)
debug("%s: could release all clocks for %p\n",
__func__, dev);
return ret;
}
clk: get clock pointer before proceeding clk_get_by_indexed_prop() retrieves a clock with dev member being set with the pointer to the udevice for the clock controller driver. But in case of CCF each clock driver has set in dev member the reference to its parent (the root of the clock tree is a fixed clock, every node in clock tree is a clock registered with clk_register()). In this case the subsequent operations like dev_get_clk_ptr() on clocks retrieved by clk_get_by_indexed_prop() will fail. For this, get the pointer to the proper clock registered (with clk_register()) using clk_get_by_id() before proceeding. Fixes: 1d7993d1d0ef ("clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12)") Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2020-09-07 14:46:36 +00:00
static struct clk *clk_set_default_get_by_id(struct clk *clk)
{
struct clk *c = clk;
if (CONFIG_IS_ENABLED(CLK_CCF)) {
int ret = clk_get_by_id(clk->id, &c);
if (ret) {
debug("%s(): could not get parent clock pointer, id %lu\n",
__func__, clk->id);
ERR_PTR(ret);
}
}
return c;
}
clk: Allow force setting clock defaults before relocation Since 291da96b8e ("clk: Allow clock defaults to be set during re-reloc state for SPL only") it has been impossible to set clock defaults before relocation. This is annoying on boards without SPL, since there is no way to set clock defaults before U-Boot proper. In particular, the aisram rate must be changed before relocation on the K210, since U-Boot will hang if we try and change the rate while we are using aisram. To get around this, extend the stage parameter to allow force setting defaults, even if they would be otherwise postponed for later. A device tree property was decided against because of the concerns in the original commit thread about the overhead of repeatedly parsing the device tree. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-06-11 04:16:07 +00:00
static int clk_set_default_parents(struct udevice *dev,
enum clk_defaults_stage stage)
clk: implement clk_set_defaults() Linux uses the properties 'assigned-clocks', 'assigned-clock-parents' and 'assigned-clock-rates' to configure the clock subsystem for use with various peripheral nodes. This implements clk_set_defaults() and hooks it up with the general device probibin in drivers/core/device.c: when a new device is probed, clk_set_defaults() will be called for it and will process the properties mentioned above. Note that this functionality is designed to fail gracefully (i.e. if a clock-driver does not implement set_parent(), we simply accept this and ignore the error) as not to break existing board-support. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Tested-by: David Wu <david.wu@rock-chips.com> Series-changes: 2 - Fixed David's email address. Series-version: 2 Cover-letter: clk: support assigned-clock, assigned-clock-parents, assigned-clock-rates For various peripherals on Rockchip SoCs (e.g. for the Ethernet GMAC), the parent-clock needs to be set via the DTS. This adds the required plumbing and implements the GMAC case for the RK3399. END
2018-01-08 12:59:18 +00:00
{
clk: get clock pointer before proceeding clk_get_by_indexed_prop() retrieves a clock with dev member being set with the pointer to the udevice for the clock controller driver. But in case of CCF each clock driver has set in dev member the reference to its parent (the root of the clock tree is a fixed clock, every node in clock tree is a clock registered with clk_register()). In this case the subsequent operations like dev_get_clk_ptr() on clocks retrieved by clk_get_by_indexed_prop() will fail. For this, get the pointer to the proper clock registered (with clk_register()) using clk_get_by_id() before proceeding. Fixes: 1d7993d1d0ef ("clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12)") Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2020-09-07 14:46:36 +00:00
struct clk clk, parent_clk, *c, *p;
clk: implement clk_set_defaults() Linux uses the properties 'assigned-clocks', 'assigned-clock-parents' and 'assigned-clock-rates' to configure the clock subsystem for use with various peripheral nodes. This implements clk_set_defaults() and hooks it up with the general device probibin in drivers/core/device.c: when a new device is probed, clk_set_defaults() will be called for it and will process the properties mentioned above. Note that this functionality is designed to fail gracefully (i.e. if a clock-driver does not implement set_parent(), we simply accept this and ignore the error) as not to break existing board-support. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Tested-by: David Wu <david.wu@rock-chips.com> Series-changes: 2 - Fixed David's email address. Series-version: 2 Cover-letter: clk: support assigned-clock, assigned-clock-parents, assigned-clock-rates For various peripherals on Rockchip SoCs (e.g. for the Ethernet GMAC), the parent-clock needs to be set via the DTS. This adds the required plumbing and implements the GMAC case for the RK3399. END
2018-01-08 12:59:18 +00:00
int index;
int num_parents;
int ret;
num_parents = dev_count_phandle_with_args(dev, "assigned-clock-parents",
dm: add cells_count parameter in *_count_phandle_with_args The cell_count argument is required when cells_name is NULL. This patch adds this parameter in live tree API - of_count_phandle_with_args - ofnode_count_phandle_with_args - dev_count_phandle_with_args This parameter solves issue when these API is used to count the number of element of a cell without cell name. This parameter allow to force the size cell. For example: count = dev_count_phandle_with_args(dev, "array", NULL, 3); Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2020-09-25 07:41:14 +00:00
"#clock-cells", 0);
clk: implement clk_set_defaults() Linux uses the properties 'assigned-clocks', 'assigned-clock-parents' and 'assigned-clock-rates' to configure the clock subsystem for use with various peripheral nodes. This implements clk_set_defaults() and hooks it up with the general device probibin in drivers/core/device.c: when a new device is probed, clk_set_defaults() will be called for it and will process the properties mentioned above. Note that this functionality is designed to fail gracefully (i.e. if a clock-driver does not implement set_parent(), we simply accept this and ignore the error) as not to break existing board-support. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Tested-by: David Wu <david.wu@rock-chips.com> Series-changes: 2 - Fixed David's email address. Series-version: 2 Cover-letter: clk: support assigned-clock, assigned-clock-parents, assigned-clock-rates For various peripherals on Rockchip SoCs (e.g. for the Ethernet GMAC), the parent-clock needs to be set via the DTS. This adds the required plumbing and implements the GMAC case for the RK3399. END
2018-01-08 12:59:18 +00:00
if (num_parents < 0) {
debug("%s: could not read assigned-clock-parents for %p\n",
__func__, dev);
return 0;
}
for (index = 0; index < num_parents; index++) {
ret = clk_get_by_indexed_prop(dev, "assigned-clock-parents",
index, &parent_clk);
clk: clk_set_default: accept no-op skip fields The Assigned Clock parents and rates misses the fact that a "0" entry can be passed to skip setting a parent or rate of an assigned clock as described in the Linux clock bindings at [1]. This patch simply skips the clock reparenting if the DT parsing returns -ENOENT and the clock rate setting if "0" is passed as clock rate. [1] https://github.com/torvalds/linux/blob/master/Documentation/devicetree/bindings/clock/clock-bindings.txt#L135 Fixes: f4fcba5c5baa "clk: implement clk_set_defaults()" Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2018-07-26 13:19:32 +00:00
/* If -ENOENT, this is a no-op entry */
if (ret == -ENOENT)
continue;
clk: implement clk_set_defaults() Linux uses the properties 'assigned-clocks', 'assigned-clock-parents' and 'assigned-clock-rates' to configure the clock subsystem for use with various peripheral nodes. This implements clk_set_defaults() and hooks it up with the general device probibin in drivers/core/device.c: when a new device is probed, clk_set_defaults() will be called for it and will process the properties mentioned above. Note that this functionality is designed to fail gracefully (i.e. if a clock-driver does not implement set_parent(), we simply accept this and ignore the error) as not to break existing board-support. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Tested-by: David Wu <david.wu@rock-chips.com> Series-changes: 2 - Fixed David's email address. Series-version: 2 Cover-letter: clk: support assigned-clock, assigned-clock-parents, assigned-clock-rates For various peripherals on Rockchip SoCs (e.g. for the Ethernet GMAC), the parent-clock needs to be set via the DTS. This adds the required plumbing and implements the GMAC case for the RK3399. END
2018-01-08 12:59:18 +00:00
if (ret) {
debug("%s: could not get parent clock %d for %s\n",
__func__, index, dev_read_name(dev));
return ret;
}
clk: get clock pointer before proceeding clk_get_by_indexed_prop() retrieves a clock with dev member being set with the pointer to the udevice for the clock controller driver. But in case of CCF each clock driver has set in dev member the reference to its parent (the root of the clock tree is a fixed clock, every node in clock tree is a clock registered with clk_register()). In this case the subsequent operations like dev_get_clk_ptr() on clocks retrieved by clk_get_by_indexed_prop() will fail. For this, get the pointer to the proper clock registered (with clk_register()) using clk_get_by_id() before proceeding. Fixes: 1d7993d1d0ef ("clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12)") Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2020-09-07 14:46:36 +00:00
p = clk_set_default_get_by_id(&parent_clk);
if (IS_ERR(p))
return PTR_ERR(p);
clk: implement clk_set_defaults() Linux uses the properties 'assigned-clocks', 'assigned-clock-parents' and 'assigned-clock-rates' to configure the clock subsystem for use with various peripheral nodes. This implements clk_set_defaults() and hooks it up with the general device probibin in drivers/core/device.c: when a new device is probed, clk_set_defaults() will be called for it and will process the properties mentioned above. Note that this functionality is designed to fail gracefully (i.e. if a clock-driver does not implement set_parent(), we simply accept this and ignore the error) as not to break existing board-support. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Tested-by: David Wu <david.wu@rock-chips.com> Series-changes: 2 - Fixed David's email address. Series-version: 2 Cover-letter: clk: support assigned-clock, assigned-clock-parents, assigned-clock-rates For various peripherals on Rockchip SoCs (e.g. for the Ethernet GMAC), the parent-clock needs to be set via the DTS. This adds the required plumbing and implements the GMAC case for the RK3399. END
2018-01-08 12:59:18 +00:00
ret = clk_get_by_indexed_prop(dev, "assigned-clocks",
index, &clk);
clk: fix assigned-clocks to pass with deferring provider If a clock provider is not ready for assigning default rates/parents during its probe, it may return -EPROBE_DEFER directly from xlate. Handle this special case properly by skipping the entry and adjusting the return value to pass. The defaults will be handled properly in post probe phase then. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
2021-06-11 08:45:11 +00:00
/*
* If the clock provider is not ready yet, let it handle
* the re-programming later.
*/
if (ret == -EPROBE_DEFER) {
ret = 0;
continue;
}
clk: implement clk_set_defaults() Linux uses the properties 'assigned-clocks', 'assigned-clock-parents' and 'assigned-clock-rates' to configure the clock subsystem for use with various peripheral nodes. This implements clk_set_defaults() and hooks it up with the general device probibin in drivers/core/device.c: when a new device is probed, clk_set_defaults() will be called for it and will process the properties mentioned above. Note that this functionality is designed to fail gracefully (i.e. if a clock-driver does not implement set_parent(), we simply accept this and ignore the error) as not to break existing board-support. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Tested-by: David Wu <david.wu@rock-chips.com> Series-changes: 2 - Fixed David's email address. Series-version: 2 Cover-letter: clk: support assigned-clock, assigned-clock-parents, assigned-clock-rates For various peripherals on Rockchip SoCs (e.g. for the Ethernet GMAC), the parent-clock needs to be set via the DTS. This adds the required plumbing and implements the GMAC case for the RK3399. END
2018-01-08 12:59:18 +00:00
if (ret) {
debug("%s: could not get assigned clock %d for %s\n",
__func__, index, dev_read_name(dev));
return ret;
}
drivers: clk: Fix using assigned-clocks in the node of the clock it sets up This fixes the case where assigned-clocks is used to define a clock defaults inside this same clock's node. This is used sometimes to setup a default parents and/or rate for a clock. example: muxed_clock: muxed_clock { clocks = <&clk_provider 0>, <&clk_provider 1>; #clock-cells = <0>; assigned-clocks = <&muxed_clock>; assigned-clock-parents = <&clk_provider 1>; }; It doesn't work in u-boot because the assigned-clocks are setup *before* the clock is probed. (clk_set_parent() will likely crash or fail if called before the device probe function) Making it work by handling "assigned-clocks" in 2 steps: first before the clk device is probed, and then after the clk device is probed. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2019-10-22 12:00:06 +00:00
/* This is clk provider device trying to reparent itself
* It cannot be done right now but need to wait after the
* device is probed
*/
clk: Allow force setting clock defaults before relocation Since 291da96b8e ("clk: Allow clock defaults to be set during re-reloc state for SPL only") it has been impossible to set clock defaults before relocation. This is annoying on boards without SPL, since there is no way to set clock defaults before U-Boot proper. In particular, the aisram rate must be changed before relocation on the K210, since U-Boot will hang if we try and change the rate while we are using aisram. To get around this, extend the stage parameter to allow force setting defaults, even if they would be otherwise postponed for later. A device tree property was decided against because of the concerns in the original commit thread about the overhead of repeatedly parsing the device tree. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-06-11 04:16:07 +00:00
if (stage == CLK_DEFAULTS_PRE && clk.dev == dev)
drivers: clk: Fix using assigned-clocks in the node of the clock it sets up This fixes the case where assigned-clocks is used to define a clock defaults inside this same clock's node. This is used sometimes to setup a default parents and/or rate for a clock. example: muxed_clock: muxed_clock { clocks = <&clk_provider 0>, <&clk_provider 1>; #clock-cells = <0>; assigned-clocks = <&muxed_clock>; assigned-clock-parents = <&clk_provider 1>; }; It doesn't work in u-boot because the assigned-clocks are setup *before* the clock is probed. (clk_set_parent() will likely crash or fail if called before the device probe function) Making it work by handling "assigned-clocks" in 2 steps: first before the clk device is probed, and then after the clk device is probed. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2019-10-22 12:00:06 +00:00
continue;
clk: Allow force setting clock defaults before relocation Since 291da96b8e ("clk: Allow clock defaults to be set during re-reloc state for SPL only") it has been impossible to set clock defaults before relocation. This is annoying on boards without SPL, since there is no way to set clock defaults before U-Boot proper. In particular, the aisram rate must be changed before relocation on the K210, since U-Boot will hang if we try and change the rate while we are using aisram. To get around this, extend the stage parameter to allow force setting defaults, even if they would be otherwise postponed for later. A device tree property was decided against because of the concerns in the original commit thread about the overhead of repeatedly parsing the device tree. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-06-11 04:16:07 +00:00
if (stage != CLK_DEFAULTS_PRE && clk.dev != dev)
drivers: clk: Fix using assigned-clocks in the node of the clock it sets up This fixes the case where assigned-clocks is used to define a clock defaults inside this same clock's node. This is used sometimes to setup a default parents and/or rate for a clock. example: muxed_clock: muxed_clock { clocks = <&clk_provider 0>, <&clk_provider 1>; #clock-cells = <0>; assigned-clocks = <&muxed_clock>; assigned-clock-parents = <&clk_provider 1>; }; It doesn't work in u-boot because the assigned-clocks are setup *before* the clock is probed. (clk_set_parent() will likely crash or fail if called before the device probe function) Making it work by handling "assigned-clocks" in 2 steps: first before the clk device is probed, and then after the clk device is probed. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2019-10-22 12:00:06 +00:00
/* do not setup twice the parent clocks */
continue;
clk: implement clk_set_defaults() Linux uses the properties 'assigned-clocks', 'assigned-clock-parents' and 'assigned-clock-rates' to configure the clock subsystem for use with various peripheral nodes. This implements clk_set_defaults() and hooks it up with the general device probibin in drivers/core/device.c: when a new device is probed, clk_set_defaults() will be called for it and will process the properties mentioned above. Note that this functionality is designed to fail gracefully (i.e. if a clock-driver does not implement set_parent(), we simply accept this and ignore the error) as not to break existing board-support. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Tested-by: David Wu <david.wu@rock-chips.com> Series-changes: 2 - Fixed David's email address. Series-version: 2 Cover-letter: clk: support assigned-clock, assigned-clock-parents, assigned-clock-rates For various peripherals on Rockchip SoCs (e.g. for the Ethernet GMAC), the parent-clock needs to be set via the DTS. This adds the required plumbing and implements the GMAC case for the RK3399. END
2018-01-08 12:59:18 +00:00
clk: get clock pointer before proceeding clk_get_by_indexed_prop() retrieves a clock with dev member being set with the pointer to the udevice for the clock controller driver. But in case of CCF each clock driver has set in dev member the reference to its parent (the root of the clock tree is a fixed clock, every node in clock tree is a clock registered with clk_register()). In this case the subsequent operations like dev_get_clk_ptr() on clocks retrieved by clk_get_by_indexed_prop() will fail. For this, get the pointer to the proper clock registered (with clk_register()) using clk_get_by_id() before proceeding. Fixes: 1d7993d1d0ef ("clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12)") Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2020-09-07 14:46:36 +00:00
c = clk_set_default_get_by_id(&clk);
if (IS_ERR(c))
return PTR_ERR(c);
ret = clk_set_parent(c, p);
clk: implement clk_set_defaults() Linux uses the properties 'assigned-clocks', 'assigned-clock-parents' and 'assigned-clock-rates' to configure the clock subsystem for use with various peripheral nodes. This implements clk_set_defaults() and hooks it up with the general device probibin in drivers/core/device.c: when a new device is probed, clk_set_defaults() will be called for it and will process the properties mentioned above. Note that this functionality is designed to fail gracefully (i.e. if a clock-driver does not implement set_parent(), we simply accept this and ignore the error) as not to break existing board-support. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Tested-by: David Wu <david.wu@rock-chips.com> Series-changes: 2 - Fixed David's email address. Series-version: 2 Cover-letter: clk: support assigned-clock, assigned-clock-parents, assigned-clock-rates For various peripherals on Rockchip SoCs (e.g. for the Ethernet GMAC), the parent-clock needs to be set via the DTS. This adds the required plumbing and implements the GMAC case for the RK3399. END
2018-01-08 12:59:18 +00:00
/*
* Not all drivers may support clock-reparenting (as of now).
* Ignore errors due to this.
*/
if (ret == -ENOSYS)
continue;
clk: Fix error check in clk_set_default_parents() According to the documentation in clk.h, clk_set_parent() return the new rate of the clock or a negative error code. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2019-09-26 13:42:42 +00:00
if (ret < 0) {
clk: implement clk_set_defaults() Linux uses the properties 'assigned-clocks', 'assigned-clock-parents' and 'assigned-clock-rates' to configure the clock subsystem for use with various peripheral nodes. This implements clk_set_defaults() and hooks it up with the general device probibin in drivers/core/device.c: when a new device is probed, clk_set_defaults() will be called for it and will process the properties mentioned above. Note that this functionality is designed to fail gracefully (i.e. if a clock-driver does not implement set_parent(), we simply accept this and ignore the error) as not to break existing board-support. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Tested-by: David Wu <david.wu@rock-chips.com> Series-changes: 2 - Fixed David's email address. Series-version: 2 Cover-letter: clk: support assigned-clock, assigned-clock-parents, assigned-clock-rates For various peripherals on Rockchip SoCs (e.g. for the Ethernet GMAC), the parent-clock needs to be set via the DTS. This adds the required plumbing and implements the GMAC case for the RK3399. END
2018-01-08 12:59:18 +00:00
debug("%s: failed to reparent clock %d for %s\n",
__func__, index, dev_read_name(dev));
return ret;
}
}
return 0;
}
clk: Allow force setting clock defaults before relocation Since 291da96b8e ("clk: Allow clock defaults to be set during re-reloc state for SPL only") it has been impossible to set clock defaults before relocation. This is annoying on boards without SPL, since there is no way to set clock defaults before U-Boot proper. In particular, the aisram rate must be changed before relocation on the K210, since U-Boot will hang if we try and change the rate while we are using aisram. To get around this, extend the stage parameter to allow force setting defaults, even if they would be otherwise postponed for later. A device tree property was decided against because of the concerns in the original commit thread about the overhead of repeatedly parsing the device tree. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-06-11 04:16:07 +00:00
static int clk_set_default_rates(struct udevice *dev,
enum clk_defaults_stage stage)
clk: implement clk_set_defaults() Linux uses the properties 'assigned-clocks', 'assigned-clock-parents' and 'assigned-clock-rates' to configure the clock subsystem for use with various peripheral nodes. This implements clk_set_defaults() and hooks it up with the general device probibin in drivers/core/device.c: when a new device is probed, clk_set_defaults() will be called for it and will process the properties mentioned above. Note that this functionality is designed to fail gracefully (i.e. if a clock-driver does not implement set_parent(), we simply accept this and ignore the error) as not to break existing board-support. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Tested-by: David Wu <david.wu@rock-chips.com> Series-changes: 2 - Fixed David's email address. Series-version: 2 Cover-letter: clk: support assigned-clock, assigned-clock-parents, assigned-clock-rates For various peripherals on Rockchip SoCs (e.g. for the Ethernet GMAC), the parent-clock needs to be set via the DTS. This adds the required plumbing and implements the GMAC case for the RK3399. END
2018-01-08 12:59:18 +00:00
{
clk: get clock pointer before proceeding clk_get_by_indexed_prop() retrieves a clock with dev member being set with the pointer to the udevice for the clock controller driver. But in case of CCF each clock driver has set in dev member the reference to its parent (the root of the clock tree is a fixed clock, every node in clock tree is a clock registered with clk_register()). In this case the subsequent operations like dev_get_clk_ptr() on clocks retrieved by clk_get_by_indexed_prop() will fail. For this, get the pointer to the proper clock registered (with clk_register()) using clk_get_by_id() before proceeding. Fixes: 1d7993d1d0ef ("clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12)") Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2020-09-07 14:46:36 +00:00
struct clk clk, *c;
clk: implement clk_set_defaults() Linux uses the properties 'assigned-clocks', 'assigned-clock-parents' and 'assigned-clock-rates' to configure the clock subsystem for use with various peripheral nodes. This implements clk_set_defaults() and hooks it up with the general device probibin in drivers/core/device.c: when a new device is probed, clk_set_defaults() will be called for it and will process the properties mentioned above. Note that this functionality is designed to fail gracefully (i.e. if a clock-driver does not implement set_parent(), we simply accept this and ignore the error) as not to break existing board-support. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Tested-by: David Wu <david.wu@rock-chips.com> Series-changes: 2 - Fixed David's email address. Series-version: 2 Cover-letter: clk: support assigned-clock, assigned-clock-parents, assigned-clock-rates For various peripherals on Rockchip SoCs (e.g. for the Ethernet GMAC), the parent-clock needs to be set via the DTS. This adds the required plumbing and implements the GMAC case for the RK3399. END
2018-01-08 12:59:18 +00:00
int index;
int num_rates;
int size;
int ret = 0;
u32 *rates = NULL;
size = dev_read_size(dev, "assigned-clock-rates");
if (size < 0)
return 0;
num_rates = size / sizeof(u32);
rates = calloc(num_rates, sizeof(u32));
if (!rates)
return -ENOMEM;
ret = dev_read_u32_array(dev, "assigned-clock-rates", rates, num_rates);
if (ret)
goto fail;
for (index = 0; index < num_rates; index++) {
clk: clk_set_default: accept no-op skip fields The Assigned Clock parents and rates misses the fact that a "0" entry can be passed to skip setting a parent or rate of an assigned clock as described in the Linux clock bindings at [1]. This patch simply skips the clock reparenting if the DT parsing returns -ENOENT and the clock rate setting if "0" is passed as clock rate. [1] https://github.com/torvalds/linux/blob/master/Documentation/devicetree/bindings/clock/clock-bindings.txt#L135 Fixes: f4fcba5c5baa "clk: implement clk_set_defaults()" Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2018-07-26 13:19:32 +00:00
/* If 0 is passed, this is a no-op */
if (!rates[index])
continue;
clk: implement clk_set_defaults() Linux uses the properties 'assigned-clocks', 'assigned-clock-parents' and 'assigned-clock-rates' to configure the clock subsystem for use with various peripheral nodes. This implements clk_set_defaults() and hooks it up with the general device probibin in drivers/core/device.c: when a new device is probed, clk_set_defaults() will be called for it and will process the properties mentioned above. Note that this functionality is designed to fail gracefully (i.e. if a clock-driver does not implement set_parent(), we simply accept this and ignore the error) as not to break existing board-support. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Tested-by: David Wu <david.wu@rock-chips.com> Series-changes: 2 - Fixed David's email address. Series-version: 2 Cover-letter: clk: support assigned-clock, assigned-clock-parents, assigned-clock-rates For various peripherals on Rockchip SoCs (e.g. for the Ethernet GMAC), the parent-clock needs to be set via the DTS. This adds the required plumbing and implements the GMAC case for the RK3399. END
2018-01-08 12:59:18 +00:00
ret = clk_get_by_indexed_prop(dev, "assigned-clocks",
index, &clk);
clk: fix assigned-clocks to pass with deferring provider If a clock provider is not ready for assigning default rates/parents during its probe, it may return -EPROBE_DEFER directly from xlate. Handle this special case properly by skipping the entry and adjusting the return value to pass. The defaults will be handled properly in post probe phase then. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
2021-06-11 08:45:11 +00:00
/*
* If the clock provider is not ready yet, let it handle
* the re-programming later.
*/
if (ret == -EPROBE_DEFER) {
ret = 0;
continue;
}
clk: implement clk_set_defaults() Linux uses the properties 'assigned-clocks', 'assigned-clock-parents' and 'assigned-clock-rates' to configure the clock subsystem for use with various peripheral nodes. This implements clk_set_defaults() and hooks it up with the general device probibin in drivers/core/device.c: when a new device is probed, clk_set_defaults() will be called for it and will process the properties mentioned above. Note that this functionality is designed to fail gracefully (i.e. if a clock-driver does not implement set_parent(), we simply accept this and ignore the error) as not to break existing board-support. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Tested-by: David Wu <david.wu@rock-chips.com> Series-changes: 2 - Fixed David's email address. Series-version: 2 Cover-letter: clk: support assigned-clock, assigned-clock-parents, assigned-clock-rates For various peripherals on Rockchip SoCs (e.g. for the Ethernet GMAC), the parent-clock needs to be set via the DTS. This adds the required plumbing and implements the GMAC case for the RK3399. END
2018-01-08 12:59:18 +00:00
if (ret) {
clk: Warn on failure to assign rate If the user/dev explicitly requests a clock be assigned a certain rate, then we should warn them if we can't do it. This makes it clear if the clock is running at the default rate. Signed-off-by: Sean Anderson <seanga2@gmail.com>
2021-04-09 02:13:03 +00:00
dev_dbg(dev,
"could not get assigned clock %d (err = %d)\n",
index, ret);
clk: implement clk_set_defaults() Linux uses the properties 'assigned-clocks', 'assigned-clock-parents' and 'assigned-clock-rates' to configure the clock subsystem for use with various peripheral nodes. This implements clk_set_defaults() and hooks it up with the general device probibin in drivers/core/device.c: when a new device is probed, clk_set_defaults() will be called for it and will process the properties mentioned above. Note that this functionality is designed to fail gracefully (i.e. if a clock-driver does not implement set_parent(), we simply accept this and ignore the error) as not to break existing board-support. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Tested-by: David Wu <david.wu@rock-chips.com> Series-changes: 2 - Fixed David's email address. Series-version: 2 Cover-letter: clk: support assigned-clock, assigned-clock-parents, assigned-clock-rates For various peripherals on Rockchip SoCs (e.g. for the Ethernet GMAC), the parent-clock needs to be set via the DTS. This adds the required plumbing and implements the GMAC case for the RK3399. END
2018-01-08 12:59:18 +00:00
continue;
}
drivers: clk: Fix using assigned-clocks in the node of the clock it sets up This fixes the case where assigned-clocks is used to define a clock defaults inside this same clock's node. This is used sometimes to setup a default parents and/or rate for a clock. example: muxed_clock: muxed_clock { clocks = <&clk_provider 0>, <&clk_provider 1>; #clock-cells = <0>; assigned-clocks = <&muxed_clock>; assigned-clock-parents = <&clk_provider 1>; }; It doesn't work in u-boot because the assigned-clocks are setup *before* the clock is probed. (clk_set_parent() will likely crash or fail if called before the device probe function) Making it work by handling "assigned-clocks" in 2 steps: first before the clk device is probed, and then after the clk device is probed. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2019-10-22 12:00:06 +00:00
/* This is clk provider device trying to program itself
* It cannot be done right now but need to wait after the
* device is probed
*/
clk: Allow force setting clock defaults before relocation Since 291da96b8e ("clk: Allow clock defaults to be set during re-reloc state for SPL only") it has been impossible to set clock defaults before relocation. This is annoying on boards without SPL, since there is no way to set clock defaults before U-Boot proper. In particular, the aisram rate must be changed before relocation on the K210, since U-Boot will hang if we try and change the rate while we are using aisram. To get around this, extend the stage parameter to allow force setting defaults, even if they would be otherwise postponed for later. A device tree property was decided against because of the concerns in the original commit thread about the overhead of repeatedly parsing the device tree. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-06-11 04:16:07 +00:00
if (stage == CLK_DEFAULTS_PRE && clk.dev == dev)
drivers: clk: Fix using assigned-clocks in the node of the clock it sets up This fixes the case where assigned-clocks is used to define a clock defaults inside this same clock's node. This is used sometimes to setup a default parents and/or rate for a clock. example: muxed_clock: muxed_clock { clocks = <&clk_provider 0>, <&clk_provider 1>; #clock-cells = <0>; assigned-clocks = <&muxed_clock>; assigned-clock-parents = <&clk_provider 1>; }; It doesn't work in u-boot because the assigned-clocks are setup *before* the clock is probed. (clk_set_parent() will likely crash or fail if called before the device probe function) Making it work by handling "assigned-clocks" in 2 steps: first before the clk device is probed, and then after the clk device is probed. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2019-10-22 12:00:06 +00:00
continue;
clk: Allow force setting clock defaults before relocation Since 291da96b8e ("clk: Allow clock defaults to be set during re-reloc state for SPL only") it has been impossible to set clock defaults before relocation. This is annoying on boards without SPL, since there is no way to set clock defaults before U-Boot proper. In particular, the aisram rate must be changed before relocation on the K210, since U-Boot will hang if we try and change the rate while we are using aisram. To get around this, extend the stage parameter to allow force setting defaults, even if they would be otherwise postponed for later. A device tree property was decided against because of the concerns in the original commit thread about the overhead of repeatedly parsing the device tree. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-06-11 04:16:07 +00:00
if (stage != CLK_DEFAULTS_PRE && clk.dev != dev)
drivers: clk: Fix using assigned-clocks in the node of the clock it sets up This fixes the case where assigned-clocks is used to define a clock defaults inside this same clock's node. This is used sometimes to setup a default parents and/or rate for a clock. example: muxed_clock: muxed_clock { clocks = <&clk_provider 0>, <&clk_provider 1>; #clock-cells = <0>; assigned-clocks = <&muxed_clock>; assigned-clock-parents = <&clk_provider 1>; }; It doesn't work in u-boot because the assigned-clocks are setup *before* the clock is probed. (clk_set_parent() will likely crash or fail if called before the device probe function) Making it work by handling "assigned-clocks" in 2 steps: first before the clk device is probed, and then after the clk device is probed. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2019-10-22 12:00:06 +00:00
/* do not setup twice the parent clocks */
continue;
clk: get clock pointer before proceeding clk_get_by_indexed_prop() retrieves a clock with dev member being set with the pointer to the udevice for the clock controller driver. But in case of CCF each clock driver has set in dev member the reference to its parent (the root of the clock tree is a fixed clock, every node in clock tree is a clock registered with clk_register()). In this case the subsequent operations like dev_get_clk_ptr() on clocks retrieved by clk_get_by_indexed_prop() will fail. For this, get the pointer to the proper clock registered (with clk_register()) using clk_get_by_id() before proceeding. Fixes: 1d7993d1d0ef ("clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12)") Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2020-09-07 14:46:36 +00:00
c = clk_set_default_get_by_id(&clk);
if (IS_ERR(c))
return PTR_ERR(c);
ret = clk_set_rate(c, rates[index]);
drivers: clk: Fix using assigned-clocks in the node of the clock it sets up This fixes the case where assigned-clocks is used to define a clock defaults inside this same clock's node. This is used sometimes to setup a default parents and/or rate for a clock. example: muxed_clock: muxed_clock { clocks = <&clk_provider 0>, <&clk_provider 1>; #clock-cells = <0>; assigned-clocks = <&muxed_clock>; assigned-clock-parents = <&clk_provider 1>; }; It doesn't work in u-boot because the assigned-clocks are setup *before* the clock is probed. (clk_set_parent() will likely crash or fail if called before the device probe function) Making it work by handling "assigned-clocks" in 2 steps: first before the clk device is probed, and then after the clk device is probed. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2019-10-22 12:00:06 +00:00
clk: implement clk_set_defaults() Linux uses the properties 'assigned-clocks', 'assigned-clock-parents' and 'assigned-clock-rates' to configure the clock subsystem for use with various peripheral nodes. This implements clk_set_defaults() and hooks it up with the general device probibin in drivers/core/device.c: when a new device is probed, clk_set_defaults() will be called for it and will process the properties mentioned above. Note that this functionality is designed to fail gracefully (i.e. if a clock-driver does not implement set_parent(), we simply accept this and ignore the error) as not to break existing board-support. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Tested-by: David Wu <david.wu@rock-chips.com> Series-changes: 2 - Fixed David's email address. Series-version: 2 Cover-letter: clk: support assigned-clock, assigned-clock-parents, assigned-clock-rates For various peripherals on Rockchip SoCs (e.g. for the Ethernet GMAC), the parent-clock needs to be set via the DTS. This adds the required plumbing and implements the GMAC case for the RK3399. END
2018-01-08 12:59:18 +00:00
if (ret < 0) {
clk: Warn on failure to assign rate If the user/dev explicitly requests a clock be assigned a certain rate, then we should warn them if we can't do it. This makes it clear if the clock is running at the default rate. Signed-off-by: Sean Anderson <seanga2@gmail.com>
2021-04-09 02:13:03 +00:00
dev_warn(dev,
"failed to set rate on clock index %d (%ld) (error = %d)\n",
index, clk.id, ret);
clk: implement clk_set_defaults() Linux uses the properties 'assigned-clocks', 'assigned-clock-parents' and 'assigned-clock-rates' to configure the clock subsystem for use with various peripheral nodes. This implements clk_set_defaults() and hooks it up with the general device probibin in drivers/core/device.c: when a new device is probed, clk_set_defaults() will be called for it and will process the properties mentioned above. Note that this functionality is designed to fail gracefully (i.e. if a clock-driver does not implement set_parent(), we simply accept this and ignore the error) as not to break existing board-support. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Tested-by: David Wu <david.wu@rock-chips.com> Series-changes: 2 - Fixed David's email address. Series-version: 2 Cover-letter: clk: support assigned-clock, assigned-clock-parents, assigned-clock-rates For various peripherals on Rockchip SoCs (e.g. for the Ethernet GMAC), the parent-clock needs to be set via the DTS. This adds the required plumbing and implements the GMAC case for the RK3399. END
2018-01-08 12:59:18 +00:00
break;
}
}
fail:
free(rates);
return ret;
}
clk: Allow force setting clock defaults before relocation Since 291da96b8e ("clk: Allow clock defaults to be set during re-reloc state for SPL only") it has been impossible to set clock defaults before relocation. This is annoying on boards without SPL, since there is no way to set clock defaults before U-Boot proper. In particular, the aisram rate must be changed before relocation on the K210, since U-Boot will hang if we try and change the rate while we are using aisram. To get around this, extend the stage parameter to allow force setting defaults, even if they would be otherwise postponed for later. A device tree property was decided against because of the concerns in the original commit thread about the overhead of repeatedly parsing the device tree. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-06-11 04:16:07 +00:00
int clk_set_defaults(struct udevice *dev, enum clk_defaults_stage stage)
clk: implement clk_set_defaults() Linux uses the properties 'assigned-clocks', 'assigned-clock-parents' and 'assigned-clock-rates' to configure the clock subsystem for use with various peripheral nodes. This implements clk_set_defaults() and hooks it up with the general device probibin in drivers/core/device.c: when a new device is probed, clk_set_defaults() will be called for it and will process the properties mentioned above. Note that this functionality is designed to fail gracefully (i.e. if a clock-driver does not implement set_parent(), we simply accept this and ignore the error) as not to break existing board-support. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Tested-by: David Wu <david.wu@rock-chips.com> Series-changes: 2 - Fixed David's email address. Series-version: 2 Cover-letter: clk: support assigned-clock, assigned-clock-parents, assigned-clock-rates For various peripherals on Rockchip SoCs (e.g. for the Ethernet GMAC), the parent-clock needs to be set via the DTS. This adds the required plumbing and implements the GMAC case for the RK3399. END
2018-01-08 12:59:18 +00:00
{
int ret;
dm: core: Use dev_has_ofnode() instead of dev_of_valid() We have two functions which do the same thing. Standardise on dev_has_ofnode() since there is no such thing as an 'invalid' ofnode in normal operation: it is either null or missing. Also move the functions into one place. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2020-12-19 17:40:13 +00:00
if (!dev_has_ofnode(dev))
dm: clk: ignore default settings when node not valid When the device not binded with a node, we need ignore the parents and rate settings. Cc: Simon Glass <sjg@chromium.org> Cc: Jagan Teki <jagan@amarulasolutions.com> Cc: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Cc: Neil Armstrong <narmstrong@baylibre.com> Cc: Andreas Dannenberg <dannenberg@ti.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-07-31 07:01:49 +00:00
return 0;
clk: Allow force setting clock defaults before relocation Since 291da96b8e ("clk: Allow clock defaults to be set during re-reloc state for SPL only") it has been impossible to set clock defaults before relocation. This is annoying on boards without SPL, since there is no way to set clock defaults before U-Boot proper. In particular, the aisram rate must be changed before relocation on the K210, since U-Boot will hang if we try and change the rate while we are using aisram. To get around this, extend the stage parameter to allow force setting defaults, even if they would be otherwise postponed for later. A device tree property was decided against because of the concerns in the original commit thread about the overhead of repeatedly parsing the device tree. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-06-11 04:16:07 +00:00
/*
* To avoid setting defaults twice, don't set them before relocation.
* However, still set them for SPL. And still set them if explicitly
* asked.
*/
clk: Allow clock defaults to be set during re-reloc state for SPL only In commit e5e06b65ad65 ("clk: Allow clock defaults to be set also during re-reloc state") the earlier guard against setting clock defaults in pre-reloc state was removed. While it is easy to filter 'assigned-clocks' properties for SPL using CONFIG_OF_SPL_REMOVE_PROPS, no such mechanism exists for the pre-reloc stage of the full U-Boot. With the default defconfig for the RK3399-Q7 (which filter the 'assigned-clocks' property for the DTS used by SPL anyway), this caused a pause during startup of the full U-Boot stage that lasted for almost 10s (due to the CPU not having been clocked up yet). This reintroduces the guard from commit f4fcba5c5baa ("clk: Allow clock defaults to be set also during re-reloc state") and extends it to only apply outside of a TPL/SPL build: i.e. clk_set_defaults will now run in pre-reloc state for SPL, but only after reloc for the full U-Boot. References: commit f4fcba5c5baa ("clk: implement clk_set_defaults()") References: commit e5e06b65ad65 ("clk: Allow clock defaults to be set also during re-reloc state") Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-11-26 19:20:19 +00:00
if (!(IS_ENABLED(CONFIG_SPL_BUILD) || (gd->flags & GD_FLG_RELOC)))
clk: Allow force setting clock defaults before relocation Since 291da96b8e ("clk: Allow clock defaults to be set during re-reloc state for SPL only") it has been impossible to set clock defaults before relocation. This is annoying on boards without SPL, since there is no way to set clock defaults before U-Boot proper. In particular, the aisram rate must be changed before relocation on the K210, since U-Boot will hang if we try and change the rate while we are using aisram. To get around this, extend the stage parameter to allow force setting defaults, even if they would be otherwise postponed for later. A device tree property was decided against because of the concerns in the original commit thread about the overhead of repeatedly parsing the device tree. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-06-11 04:16:07 +00:00
if (stage != CLK_DEFAULTS_POST_FORCE)
return 0;
clk: Allow clock defaults to be set during re-reloc state for SPL only In commit e5e06b65ad65 ("clk: Allow clock defaults to be set also during re-reloc state") the earlier guard against setting clock defaults in pre-reloc state was removed. While it is easy to filter 'assigned-clocks' properties for SPL using CONFIG_OF_SPL_REMOVE_PROPS, no such mechanism exists for the pre-reloc stage of the full U-Boot. With the default defconfig for the RK3399-Q7 (which filter the 'assigned-clocks' property for the DTS used by SPL anyway), this caused a pause during startup of the full U-Boot stage that lasted for almost 10s (due to the CPU not having been clocked up yet). This reintroduces the guard from commit f4fcba5c5baa ("clk: Allow clock defaults to be set also during re-reloc state") and extends it to only apply outside of a TPL/SPL build: i.e. clk_set_defaults will now run in pre-reloc state for SPL, but only after reloc for the full U-Boot. References: commit f4fcba5c5baa ("clk: implement clk_set_defaults()") References: commit e5e06b65ad65 ("clk: Allow clock defaults to be set also during re-reloc state") Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-11-26 19:20:19 +00:00
clk: implement clk_set_defaults() Linux uses the properties 'assigned-clocks', 'assigned-clock-parents' and 'assigned-clock-rates' to configure the clock subsystem for use with various peripheral nodes. This implements clk_set_defaults() and hooks it up with the general device probibin in drivers/core/device.c: when a new device is probed, clk_set_defaults() will be called for it and will process the properties mentioned above. Note that this functionality is designed to fail gracefully (i.e. if a clock-driver does not implement set_parent(), we simply accept this and ignore the error) as not to break existing board-support. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Tested-by: David Wu <david.wu@rock-chips.com> Series-changes: 2 - Fixed David's email address. Series-version: 2 Cover-letter: clk: support assigned-clock, assigned-clock-parents, assigned-clock-rates For various peripherals on Rockchip SoCs (e.g. for the Ethernet GMAC), the parent-clock needs to be set via the DTS. This adds the required plumbing and implements the GMAC case for the RK3399. END
2018-01-08 12:59:18 +00:00
debug("%s(%s)\n", __func__, dev_read_name(dev));
drivers: clk: Fix using assigned-clocks in the node of the clock it sets up This fixes the case where assigned-clocks is used to define a clock defaults inside this same clock's node. This is used sometimes to setup a default parents and/or rate for a clock. example: muxed_clock: muxed_clock { clocks = <&clk_provider 0>, <&clk_provider 1>; #clock-cells = <0>; assigned-clocks = <&muxed_clock>; assigned-clock-parents = <&clk_provider 1>; }; It doesn't work in u-boot because the assigned-clocks are setup *before* the clock is probed. (clk_set_parent() will likely crash or fail if called before the device probe function) Making it work by handling "assigned-clocks" in 2 steps: first before the clk device is probed, and then after the clk device is probed. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2019-10-22 12:00:06 +00:00
ret = clk_set_default_parents(dev, stage);
clk: implement clk_set_defaults() Linux uses the properties 'assigned-clocks', 'assigned-clock-parents' and 'assigned-clock-rates' to configure the clock subsystem for use with various peripheral nodes. This implements clk_set_defaults() and hooks it up with the general device probibin in drivers/core/device.c: when a new device is probed, clk_set_defaults() will be called for it and will process the properties mentioned above. Note that this functionality is designed to fail gracefully (i.e. if a clock-driver does not implement set_parent(), we simply accept this and ignore the error) as not to break existing board-support. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Tested-by: David Wu <david.wu@rock-chips.com> Series-changes: 2 - Fixed David's email address. Series-version: 2 Cover-letter: clk: support assigned-clock, assigned-clock-parents, assigned-clock-rates For various peripherals on Rockchip SoCs (e.g. for the Ethernet GMAC), the parent-clock needs to be set via the DTS. This adds the required plumbing and implements the GMAC case for the RK3399. END
2018-01-08 12:59:18 +00:00
if (ret)
return ret;
drivers: clk: Fix using assigned-clocks in the node of the clock it sets up This fixes the case where assigned-clocks is used to define a clock defaults inside this same clock's node. This is used sometimes to setup a default parents and/or rate for a clock. example: muxed_clock: muxed_clock { clocks = <&clk_provider 0>, <&clk_provider 1>; #clock-cells = <0>; assigned-clocks = <&muxed_clock>; assigned-clock-parents = <&clk_provider 1>; }; It doesn't work in u-boot because the assigned-clocks are setup *before* the clock is probed. (clk_set_parent() will likely crash or fail if called before the device probe function) Making it work by handling "assigned-clocks" in 2 steps: first before the clk device is probed, and then after the clk device is probed. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2019-10-22 12:00:06 +00:00
ret = clk_set_default_rates(dev, stage);
clk: implement clk_set_defaults() Linux uses the properties 'assigned-clocks', 'assigned-clock-parents' and 'assigned-clock-rates' to configure the clock subsystem for use with various peripheral nodes. This implements clk_set_defaults() and hooks it up with the general device probibin in drivers/core/device.c: when a new device is probed, clk_set_defaults() will be called for it and will process the properties mentioned above. Note that this functionality is designed to fail gracefully (i.e. if a clock-driver does not implement set_parent(), we simply accept this and ignore the error) as not to break existing board-support. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Tested-by: David Wu <david.wu@rock-chips.com> Series-changes: 2 - Fixed David's email address. Series-version: 2 Cover-letter: clk: support assigned-clock, assigned-clock-parents, assigned-clock-rates For various peripherals on Rockchip SoCs (e.g. for the Ethernet GMAC), the parent-clock needs to be set via the DTS. This adds the required plumbing and implements the GMAC case for the RK3399. END
2018-01-08 12:59:18 +00:00
if (ret < 0)
return ret;
return 0;
}
clk: convert API to match reset/mailbox style The following changes are made to the clock API: * The concept of "clocks" and "peripheral clocks" are unified; each clock provider now implements a single set of clocks. This provides a simpler conceptual interface to clients, and better aligns with device tree clock bindings. * Clocks are now identified with a single "struct clk", rather than requiring clients to store the clock provider device and clock identity values separately. For simple clock consumers, this isolates clients from internal details of the clock API. * clk.h is split so it only contains the client/consumer API, whereas clk-uclass.h contains the provider API. This aligns with the recently added reset and mailbox APIs. * clk_ops .of_xlate(), .request(), and .free() are added so providers can customize these operations if needed. This also aligns with the recently added reset and mailbox APIs. * clk_disable() is added. * All users of the current clock APIs are updated. * Sandbox clock tests are updated to exercise clock lookup via DT, and clock enable/disable. * rkclk_get_clk() is removed and replaced with standard APIs. Buildman shows no clock-related errors for any board for which buildman can download a toolchain. test/py passes for sandbox (which invokes the dm clk test amongst others). Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org>
2016-06-17 15:44:00 +00:00
int clk_get_by_name(struct udevice *dev, const char *name, struct clk *clk)
{
clk: Consolidate some clock functions These functions are exactly the same as their "nodev" varients, except they accept a device and not an ofnode. Rewrite them to just call the other function. Signed-off-by: Sean Anderson <seanga2@gmail.com> Link: https://lore.kernel.org/r/20220227190113.1617498-1-seanga2@gmail.com
2022-02-27 19:01:13 +00:00
return clk_get_by_name_nodev(dev_ofnode(dev), name, clk);
dm: clk: Add support for decoding clocks from the device tree Add a method which can locate a clock for a device, given its index. This uses the normal device tree bindings to return the clock device and the first argument which is normally used as a peripheral ID in U-Boot. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-01-21 02:43:02 +00:00
}
clk: Rename clk_get_by_driver_info() This is actually a misnomer now, since the phandle info may contain a driver_info index or a udevice index. Rename it to use the word 'phandle', which seems more accurate. Add a comment while we are here. Also add a test for this function. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-08-07 13:24:09 +00:00
#endif /* OF_REAL */
clk: fix compilation errors for poplar platform Move clk_release_all() prototype and definition inside OF_CONTROL flag to avoid following compilation error for poplar platform: aarch64: + poplar +drivers/usb/host/built-in.o: In function `ehci_usb_remove': +drivers/usb/host/ehci-generic.c:159: undefined reference to `clk_release_all' +drivers/usb/host/built-in.o: In function `ehci_usb_probe': +drivers/usb/host/ehci-generic.c:133: undefined reference to `clk_release_all' +make[1]: *** [u-boot] Error 139 +make: *** [sub-make] Error 2 Introduced by 4e542c4 clk: add clk_release_all() Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2017-07-25 11:24:45 +00:00
clk: add APIs to get (optional) clock by name without a device Sometimes we may need get (optional) clock without a device, that means use ofnode. e.g. when the phy node has subnode, and there is no device created for subnode, in this case, we need these new APIs to get subnode's clock. Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Ryder Lee <ryder.lee@mediatek.com>
2020-01-09 03:35:07 +00:00
int clk_get_by_name_nodev(ofnode node, const char *name, struct clk *clk)
{
clk: Allow clk_get_by_name() with NULL name This allows devm_clock_get(dev, NULL) to work and get the first clock, which is common in code ported from Linux. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Link: https://lore.kernel.org/r/20230122000252.53642-1-samuel@sholland.org
2023-01-22 00:02:51 +00:00
int index = 0;
clk: add APIs to get (optional) clock by name without a device Sometimes we may need get (optional) clock without a device, that means use ofnode. e.g. when the phy node has subnode, and there is no device created for subnode, in this case, we need these new APIs to get subnode's clock. Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Ryder Lee <ryder.lee@mediatek.com>
2020-01-09 03:35:07 +00:00
debug("%s(node=%p, name=%s, clk=%p)\n", __func__,
ofnode_get_name(node), name, clk);
clk->dev = NULL;
clk: Allow clk_get_by_name() with NULL name This allows devm_clock_get(dev, NULL) to work and get the first clock, which is common in code ported from Linux. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Link: https://lore.kernel.org/r/20230122000252.53642-1-samuel@sholland.org
2023-01-22 00:02:51 +00:00
if (name) {
index = ofnode_stringlist_search(node, "clock-names", name);
if (index < 0) {
debug("fdt_stringlist_search() failed: %d\n", index);
return index;
}
clk: add APIs to get (optional) clock by name without a device Sometimes we may need get (optional) clock without a device, that means use ofnode. e.g. when the phy node has subnode, and there is no device created for subnode, in this case, we need these new APIs to get subnode's clock. Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Ryder Lee <ryder.lee@mediatek.com>
2020-01-09 03:35:07 +00:00
}
return clk_get_by_index_nodev(node, index, clk);
}
clk: fix compilation errors for poplar platform Move clk_release_all() prototype and definition inside OF_CONTROL flag to avoid following compilation error for poplar platform: aarch64: + poplar +drivers/usb/host/built-in.o: In function `ehci_usb_remove': +drivers/usb/host/ehci-generic.c:159: undefined reference to `clk_release_all' +drivers/usb/host/built-in.o: In function `ehci_usb_probe': +drivers/usb/host/ehci-generic.c:133: undefined reference to `clk_release_all' +make[1]: *** [u-boot] Error 139 +make: *** [sub-make] Error 2 Introduced by 4e542c4 clk: add clk_release_all() Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2017-07-25 11:24:45 +00:00
int clk_release_all(struct clk *clk, int count)
{
int i, ret;
for (i = 0; i < count; i++) {
debug("%s(clk[%d]=%p)\n", __func__, i, &clk[i]);
/* check if clock has been previously requested */
if (!clk[i].dev)
continue;
ret = clk_disable(&clk[i]);
if (ret && ret != -ENOSYS)
return ret;
clk: Make clk_free return void Most callers of this function do not check the return value, and it is unclear what action they should take if it fails. If a function is freeing multiple clocks, it should not stop just because the first one failed. Since the callbacks can no longer fail, just convert the return type to void. Signed-off-by: Sean Anderson <seanga2@gmail.com> Link: https://lore.kernel.org/r/20220115222504.617013-8-seanga2@gmail.com
2022-01-15 22:25:04 +00:00
clk_free(&clk[i]);
clk: fix compilation errors for poplar platform Move clk_release_all() prototype and definition inside OF_CONTROL flag to avoid following compilation error for poplar platform: aarch64: + poplar +drivers/usb/host/built-in.o: In function `ehci_usb_remove': +drivers/usb/host/ehci-generic.c:159: undefined reference to `clk_release_all' +drivers/usb/host/built-in.o: In function `ehci_usb_probe': +drivers/usb/host/ehci-generic.c:133: undefined reference to `clk_release_all' +make[1]: *** [u-boot] Error 139 +make: *** [sub-make] Error 2 Introduced by 4e542c4 clk: add clk_release_all() Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2017-07-25 11:24:45 +00:00
}
return 0;
}
clk: convert API to match reset/mailbox style The following changes are made to the clock API: * The concept of "clocks" and "peripheral clocks" are unified; each clock provider now implements a single set of clocks. This provides a simpler conceptual interface to clients, and better aligns with device tree clock bindings. * Clocks are now identified with a single "struct clk", rather than requiring clients to store the clock provider device and clock identity values separately. For simple clock consumers, this isolates clients from internal details of the clock API. * clk.h is split so it only contains the client/consumer API, whereas clk-uclass.h contains the provider API. This aligns with the recently added reset and mailbox APIs. * clk_ops .of_xlate(), .request(), and .free() are added so providers can customize these operations if needed. This also aligns with the recently added reset and mailbox APIs. * clk_disable() is added. * All users of the current clock APIs are updated. * Sandbox clock tests are updated to exercise clock lookup via DT, and clock enable/disable. * rkclk_get_clk() is removed and replaced with standard APIs. Buildman shows no clock-related errors for any board for which buildman can download a toolchain. test/py passes for sandbox (which invokes the dm clk test amongst others). Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org>
2016-06-17 15:44:00 +00:00
int clk_request(struct udevice *dev, struct clk *clk)
{
drivers: clk: Handle gracefully NULL pointers Prepare the way for a managed CLK API by handling NULL pointers without crashing nor failing. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2019-10-22 12:00:03 +00:00
const struct clk_ops *ops;
clk: convert API to match reset/mailbox style The following changes are made to the clock API: * The concept of "clocks" and "peripheral clocks" are unified; each clock provider now implements a single set of clocks. This provides a simpler conceptual interface to clients, and better aligns with device tree clock bindings. * Clocks are now identified with a single "struct clk", rather than requiring clients to store the clock provider device and clock identity values separately. For simple clock consumers, this isolates clients from internal details of the clock API. * clk.h is split so it only contains the client/consumer API, whereas clk-uclass.h contains the provider API. This aligns with the recently added reset and mailbox APIs. * clk_ops .of_xlate(), .request(), and .free() are added so providers can customize these operations if needed. This also aligns with the recently added reset and mailbox APIs. * clk_disable() is added. * All users of the current clock APIs are updated. * Sandbox clock tests are updated to exercise clock lookup via DT, and clock enable/disable. * rkclk_get_clk() is removed and replaced with standard APIs. Buildman shows no clock-related errors for any board for which buildman can download a toolchain. test/py passes for sandbox (which invokes the dm clk test amongst others). Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org>
2016-06-17 15:44:00 +00:00
debug("%s(dev=%p, clk=%p)\n", __func__, dev, clk);
drivers: clk: Handle gracefully NULL pointers Prepare the way for a managed CLK API by handling NULL pointers without crashing nor failing. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2019-10-22 12:00:03 +00:00
if (!clk)
return 0;
ops = clk_dev_ops(dev);
clk: convert API to match reset/mailbox style The following changes are made to the clock API: * The concept of "clocks" and "peripheral clocks" are unified; each clock provider now implements a single set of clocks. This provides a simpler conceptual interface to clients, and better aligns with device tree clock bindings. * Clocks are now identified with a single "struct clk", rather than requiring clients to store the clock provider device and clock identity values separately. For simple clock consumers, this isolates clients from internal details of the clock API. * clk.h is split so it only contains the client/consumer API, whereas clk-uclass.h contains the provider API. This aligns with the recently added reset and mailbox APIs. * clk_ops .of_xlate(), .request(), and .free() are added so providers can customize these operations if needed. This also aligns with the recently added reset and mailbox APIs. * clk_disable() is added. * All users of the current clock APIs are updated. * Sandbox clock tests are updated to exercise clock lookup via DT, and clock enable/disable. * rkclk_get_clk() is removed and replaced with standard APIs. Buildman shows no clock-related errors for any board for which buildman can download a toolchain. test/py passes for sandbox (which invokes the dm clk test amongst others). Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org>
2016-06-17 15:44:00 +00:00
clk->dev = dev;
if (!ops->request)
return 0;
return ops->request(clk);
}
clk: Make clk_free return void Most callers of this function do not check the return value, and it is unclear what action they should take if it fails. If a function is freeing multiple clocks, it should not stop just because the first one failed. Since the callbacks can no longer fail, just convert the return type to void. Signed-off-by: Sean Anderson <seanga2@gmail.com> Link: https://lore.kernel.org/r/20220115222504.617013-8-seanga2@gmail.com
2022-01-15 22:25:04 +00:00
void clk_free(struct clk *clk)
clk: convert API to match reset/mailbox style The following changes are made to the clock API: * The concept of "clocks" and "peripheral clocks" are unified; each clock provider now implements a single set of clocks. This provides a simpler conceptual interface to clients, and better aligns with device tree clock bindings. * Clocks are now identified with a single "struct clk", rather than requiring clients to store the clock provider device and clock identity values separately. For simple clock consumers, this isolates clients from internal details of the clock API. * clk.h is split so it only contains the client/consumer API, whereas clk-uclass.h contains the provider API. This aligns with the recently added reset and mailbox APIs. * clk_ops .of_xlate(), .request(), and .free() are added so providers can customize these operations if needed. This also aligns with the recently added reset and mailbox APIs. * clk_disable() is added. * All users of the current clock APIs are updated. * Sandbox clock tests are updated to exercise clock lookup via DT, and clock enable/disable. * rkclk_get_clk() is removed and replaced with standard APIs. Buildman shows no clock-related errors for any board for which buildman can download a toolchain. test/py passes for sandbox (which invokes the dm clk test amongst others). Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org>
2016-06-17 15:44:00 +00:00
{
drivers: clk: Handle gracefully NULL pointers Prepare the way for a managed CLK API by handling NULL pointers without crashing nor failing. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2019-10-22 12:00:03 +00:00
const struct clk_ops *ops;
clk: convert API to match reset/mailbox style The following changes are made to the clock API: * The concept of "clocks" and "peripheral clocks" are unified; each clock provider now implements a single set of clocks. This provides a simpler conceptual interface to clients, and better aligns with device tree clock bindings. * Clocks are now identified with a single "struct clk", rather than requiring clients to store the clock provider device and clock identity values separately. For simple clock consumers, this isolates clients from internal details of the clock API. * clk.h is split so it only contains the client/consumer API, whereas clk-uclass.h contains the provider API. This aligns with the recently added reset and mailbox APIs. * clk_ops .of_xlate(), .request(), and .free() are added so providers can customize these operations if needed. This also aligns with the recently added reset and mailbox APIs. * clk_disable() is added. * All users of the current clock APIs are updated. * Sandbox clock tests are updated to exercise clock lookup via DT, and clock enable/disable. * rkclk_get_clk() is removed and replaced with standard APIs. Buildman shows no clock-related errors for any board for which buildman can download a toolchain. test/py passes for sandbox (which invokes the dm clk test amongst others). Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org>
2016-06-17 15:44:00 +00:00
debug("%s(clk=%p)\n", __func__, clk);
clk: check valid clock by clk_valid() Add valid check for clk->dev, it's useful when get optional clock even when the clk point is valid, but its dev will be NULL. Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Ryder Lee <ryder.lee@mediatek.com>
2020-01-09 03:35:06 +00:00
if (!clk_valid(clk))
clk: Make clk_free return void Most callers of this function do not check the return value, and it is unclear what action they should take if it fails. If a function is freeing multiple clocks, it should not stop just because the first one failed. Since the callbacks can no longer fail, just convert the return type to void. Signed-off-by: Sean Anderson <seanga2@gmail.com> Link: https://lore.kernel.org/r/20220115222504.617013-8-seanga2@gmail.com
2022-01-15 22:25:04 +00:00
return;
drivers: clk: Handle gracefully NULL pointers Prepare the way for a managed CLK API by handling NULL pointers without crashing nor failing. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2019-10-22 12:00:03 +00:00
ops = clk_dev_ops(clk->dev);
clk: convert API to match reset/mailbox style The following changes are made to the clock API: * The concept of "clocks" and "peripheral clocks" are unified; each clock provider now implements a single set of clocks. This provides a simpler conceptual interface to clients, and better aligns with device tree clock bindings. * Clocks are now identified with a single "struct clk", rather than requiring clients to store the clock provider device and clock identity values separately. For simple clock consumers, this isolates clients from internal details of the clock API. * clk.h is split so it only contains the client/consumer API, whereas clk-uclass.h contains the provider API. This aligns with the recently added reset and mailbox APIs. * clk_ops .of_xlate(), .request(), and .free() are added so providers can customize these operations if needed. This also aligns with the recently added reset and mailbox APIs. * clk_disable() is added. * All users of the current clock APIs are updated. * Sandbox clock tests are updated to exercise clock lookup via DT, and clock enable/disable. * rkclk_get_clk() is removed and replaced with standard APIs. Buildman shows no clock-related errors for any board for which buildman can download a toolchain. test/py passes for sandbox (which invokes the dm clk test amongst others). Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org>
2016-06-17 15:44:00 +00:00
clk: Make rfree return void When freeing a clock there is not much we can do if there is an error, and most callers do not actually check the return value. Even e.g. checking to make sure that clk->id is valid should have been done in request() in the first place (unless someone is messing with the driver behind our back). Just return void and don't bother returning an error. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Link: https://lore.kernel.org/r/20220115222504.617013-2-seanga2@gmail.com
2022-01-15 22:24:58 +00:00
if (ops->rfree)
ops->rfree(clk);
clk: Make clk_free return void Most callers of this function do not check the return value, and it is unclear what action they should take if it fails. If a function is freeing multiple clocks, it should not stop just because the first one failed. Since the callbacks can no longer fail, just convert the return type to void. Signed-off-by: Sean Anderson <seanga2@gmail.com> Link: https://lore.kernel.org/r/20220115222504.617013-8-seanga2@gmail.com
2022-01-15 22:25:04 +00:00
return;
clk: convert API to match reset/mailbox style The following changes are made to the clock API: * The concept of "clocks" and "peripheral clocks" are unified; each clock provider now implements a single set of clocks. This provides a simpler conceptual interface to clients, and better aligns with device tree clock bindings. * Clocks are now identified with a single "struct clk", rather than requiring clients to store the clock provider device and clock identity values separately. For simple clock consumers, this isolates clients from internal details of the clock API. * clk.h is split so it only contains the client/consumer API, whereas clk-uclass.h contains the provider API. This aligns with the recently added reset and mailbox APIs. * clk_ops .of_xlate(), .request(), and .free() are added so providers can customize these operations if needed. This also aligns with the recently added reset and mailbox APIs. * clk_disable() is added. * All users of the current clock APIs are updated. * Sandbox clock tests are updated to exercise clock lookup via DT, and clock enable/disable. * rkclk_get_clk() is removed and replaced with standard APIs. Buildman shows no clock-related errors for any board for which buildman can download a toolchain. test/py passes for sandbox (which invokes the dm clk test amongst others). Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org>
2016-06-17 15:44:00 +00:00
}
ulong clk_get_rate(struct clk *clk)
{
drivers: clk: Handle gracefully NULL pointers Prepare the way for a managed CLK API by handling NULL pointers without crashing nor failing. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2019-10-22 12:00:03 +00:00
const struct clk_ops *ops;
clk: Add debugging for return values Use the log_msg_ret() mechanism to get error-return information when clocks fail to probe, etc. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-01-21 20:57:11 +00:00
int ret;
clk: convert API to match reset/mailbox style The following changes are made to the clock API: * The concept of "clocks" and "peripheral clocks" are unified; each clock provider now implements a single set of clocks. This provides a simpler conceptual interface to clients, and better aligns with device tree clock bindings. * Clocks are now identified with a single "struct clk", rather than requiring clients to store the clock provider device and clock identity values separately. For simple clock consumers, this isolates clients from internal details of the clock API. * clk.h is split so it only contains the client/consumer API, whereas clk-uclass.h contains the provider API. This aligns with the recently added reset and mailbox APIs. * clk_ops .of_xlate(), .request(), and .free() are added so providers can customize these operations if needed. This also aligns with the recently added reset and mailbox APIs. * clk_disable() is added. * All users of the current clock APIs are updated. * Sandbox clock tests are updated to exercise clock lookup via DT, and clock enable/disable. * rkclk_get_clk() is removed and replaced with standard APIs. Buildman shows no clock-related errors for any board for which buildman can download a toolchain. test/py passes for sandbox (which invokes the dm clk test amongst others). Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org>
2016-06-17 15:44:00 +00:00
debug("%s(clk=%p)\n", __func__, clk);
clk: check valid clock by clk_valid() Add valid check for clk->dev, it's useful when get optional clock even when the clk point is valid, but its dev will be NULL. Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Ryder Lee <ryder.lee@mediatek.com>
2020-01-09 03:35:06 +00:00
if (!clk_valid(clk))
drivers: clk: Handle gracefully NULL pointers Prepare the way for a managed CLK API by handling NULL pointers without crashing nor failing. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2019-10-22 12:00:03 +00:00
return 0;
ops = clk_dev_ops(clk->dev);
clk: convert API to match reset/mailbox style The following changes are made to the clock API: * The concept of "clocks" and "peripheral clocks" are unified; each clock provider now implements a single set of clocks. This provides a simpler conceptual interface to clients, and better aligns with device tree clock bindings. * Clocks are now identified with a single "struct clk", rather than requiring clients to store the clock provider device and clock identity values separately. For simple clock consumers, this isolates clients from internal details of the clock API. * clk.h is split so it only contains the client/consumer API, whereas clk-uclass.h contains the provider API. This aligns with the recently added reset and mailbox APIs. * clk_ops .of_xlate(), .request(), and .free() are added so providers can customize these operations if needed. This also aligns with the recently added reset and mailbox APIs. * clk_disable() is added. * All users of the current clock APIs are updated. * Sandbox clock tests are updated to exercise clock lookup via DT, and clock enable/disable. * rkclk_get_clk() is removed and replaced with standard APIs. Buildman shows no clock-related errors for any board for which buildman can download a toolchain. test/py passes for sandbox (which invokes the dm clk test amongst others). Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org>
2016-06-17 15:44:00 +00:00
if (!ops->get_rate)
return -ENOSYS;
clk: Add debugging for return values Use the log_msg_ret() mechanism to get error-return information when clocks fail to probe, etc. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-01-21 20:57:11 +00:00
ret = ops->get_rate(clk);
if (ret)
return log_ret(ret);
return 0;
clk: convert API to match reset/mailbox style The following changes are made to the clock API: * The concept of "clocks" and "peripheral clocks" are unified; each clock provider now implements a single set of clocks. This provides a simpler conceptual interface to clients, and better aligns with device tree clock bindings. * Clocks are now identified with a single "struct clk", rather than requiring clients to store the clock provider device and clock identity values separately. For simple clock consumers, this isolates clients from internal details of the clock API. * clk.h is split so it only contains the client/consumer API, whereas clk-uclass.h contains the provider API. This aligns with the recently added reset and mailbox APIs. * clk_ops .of_xlate(), .request(), and .free() are added so providers can customize these operations if needed. This also aligns with the recently added reset and mailbox APIs. * clk_disable() is added. * All users of the current clock APIs are updated. * Sandbox clock tests are updated to exercise clock lookup via DT, and clock enable/disable. * rkclk_get_clk() is removed and replaced with standard APIs. Buildman shows no clock-related errors for any board for which buildman can download a toolchain. test/py passes for sandbox (which invokes the dm clk test amongst others). Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org>
2016-06-17 15:44:00 +00:00
}
dm: clk: Define clk_get_parent() for clk operations This commit adds the clk_get_parent() function, which is responsible for getting the parent's struct clock pointer. U-Boot's DM support for getting parent is different (the parent relationship is in udevice) than the one in Common Clock Framework [CCF] in Linux. To obtain the pointer to struct clk of parent the pdev->uclass_priv field is read via dev_get_clk_ptr() wrapper. Signed-off-by: Lukasz Majewski <lukma@denx.de> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2019-06-24 13:50:42 +00:00
struct clk *clk_get_parent(struct clk *clk)
{
struct udevice *pdev;
struct clk *pclk;
debug("%s(clk=%p)\n", __func__, clk);
clk: check valid clock by clk_valid() Add valid check for clk->dev, it's useful when get optional clock even when the clk point is valid, but its dev will be NULL. Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Ryder Lee <ryder.lee@mediatek.com>
2020-01-09 03:35:06 +00:00
if (!clk_valid(clk))
drivers: clk: Handle gracefully NULL pointers Prepare the way for a managed CLK API by handling NULL pointers without crashing nor failing. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2019-10-22 12:00:03 +00:00
return NULL;
dm: clk: Define clk_get_parent() for clk operations This commit adds the clk_get_parent() function, which is responsible for getting the parent's struct clock pointer. U-Boot's DM support for getting parent is different (the parent relationship is in udevice) than the one in Common Clock Framework [CCF] in Linux. To obtain the pointer to struct clk of parent the pdev->uclass_priv field is read via dev_get_clk_ptr() wrapper. Signed-off-by: Lukasz Majewski <lukma@denx.de> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2019-06-24 13:50:42 +00:00
pdev = dev_get_parent(clk->dev);
clk: do not attempt to fetch clock pointer with null device Bail out early if device returned for the parent clock is null. This avoids warning prints like this when doing clk dump: dev_get_uclass_priv: null device Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
2021-06-11 08:45:08 +00:00
if (!pdev)
return ERR_PTR(-ENODEV);
dm: clk: Define clk_get_parent() for clk operations This commit adds the clk_get_parent() function, which is responsible for getting the parent's struct clock pointer. U-Boot's DM support for getting parent is different (the parent relationship is in udevice) than the one in Common Clock Framework [CCF] in Linux. To obtain the pointer to struct clk of parent the pdev->uclass_priv field is read via dev_get_clk_ptr() wrapper. Signed-off-by: Lukasz Majewski <lukma@denx.de> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2019-06-24 13:50:42 +00:00
pclk = dev_get_clk_ptr(pdev);
if (!pclk)
return ERR_PTR(-ENODEV);
return pclk;
}
clk: change return type of clk_get_parent_rate from long long to ulong All functions getting and setting clock rate use ulong for rate, only clk_get_parent_rate is an exception. Change the return value to match other clock rate funcrions. Most users directly assign the rate to unsigned long anyway, and the few users that use u64 (not s64) multiply the rate so they may need the extra bits for the result in their use case. Fixes: 4aa78300a0 ("dm: clk: Define clk_get_parent_rate() for clk operations") Signed-off-by: Michal Suchanek <msuchanek@suse.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Sean Anderson <seanga2@gmail.com> Link: https://lore.kernel.org/r/20220928103757.11870-1-msuchanek@suse.de
2022-09-28 10:37:57 +00:00
ulong clk_get_parent_rate(struct clk *clk)
dm: clk: Define clk_get_parent_rate() for clk operations This commit adds the clk_get_parent_rate() function, which is responsible for getting the rate of parent clock. Unfortunately, u-boot's DM support for getting parent is different (the parent relationship is in udevice) than the one in Common Clock Framework [CCF] in Linux. To alleviate this problem - the clk_get_parent_rate() function has been introduced to clk-uclass.c. Signed-off-by: Lukasz Majewski <lukma@denx.de> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2019-06-24 13:50:43 +00:00
{
const struct clk_ops *ops;
struct clk *pclk;
debug("%s(clk=%p)\n", __func__, clk);
clk: check valid clock by clk_valid() Add valid check for clk->dev, it's useful when get optional clock even when the clk point is valid, but its dev will be NULL. Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Ryder Lee <ryder.lee@mediatek.com>
2020-01-09 03:35:06 +00:00
if (!clk_valid(clk))
drivers: clk: Handle gracefully NULL pointers Prepare the way for a managed CLK API by handling NULL pointers without crashing nor failing. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2019-10-22 12:00:03 +00:00
return 0;
dm: clk: Define clk_get_parent_rate() for clk operations This commit adds the clk_get_parent_rate() function, which is responsible for getting the rate of parent clock. Unfortunately, u-boot's DM support for getting parent is different (the parent relationship is in udevice) than the one in Common Clock Framework [CCF] in Linux. To alleviate this problem - the clk_get_parent_rate() function has been introduced to clk-uclass.c. Signed-off-by: Lukasz Majewski <lukma@denx.de> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2019-06-24 13:50:43 +00:00
pclk = clk_get_parent(clk);
if (IS_ERR(pclk))
return -ENODEV;
ops = clk_dev_ops(pclk->dev);
if (!ops->get_rate)
return -ENOSYS;
dm: clk: Extend clk_get_parent_rate() to support CLK_GET_RATE_NOCACHE flag If the CLK_GET_RATE_NOCACHE flag is set - the clk_get_parent_rate() provides recalculated clock value without considering the cache setting. This may be necessary for some clocks tightly coupled with power domains (i.e. imx8), and prevents from reading invalid cached values. Signed-off-by: Lukasz Majewski <lukma@denx.de> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2019-06-24 13:50:46 +00:00
/* Read the 'rate' if not already set or if proper flag set*/
if (!pclk->rate || pclk->flags & CLK_GET_RATE_NOCACHE)
dm: clk: Define clk_get_parent_rate() for clk operations This commit adds the clk_get_parent_rate() function, which is responsible for getting the rate of parent clock. Unfortunately, u-boot's DM support for getting parent is different (the parent relationship is in udevice) than the one in Common Clock Framework [CCF] in Linux. To alleviate this problem - the clk_get_parent_rate() function has been introduced to clk-uclass.c. Signed-off-by: Lukasz Majewski <lukma@denx.de> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2019-06-24 13:50:43 +00:00
pclk->rate = clk_get_rate(pclk);
return pclk->rate;
}
clk: add clk_round_rate() It returns the rate which will be set if you ask clk_set_rate() to set that rate. It provides a way to query exactly what rate you'll get if you call clk_set_rate() with that same argument. So essentially, clk_round_rate() and clk_set_rate() are equivalent except the former does not modify the clock hardware in any way. Signed-off-by: Dario Binacchi <dariobin@libero.it> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Sean Anderson <seanga2@gmail.com>
2020-12-29 23:06:31 +00:00
ulong clk_round_rate(struct clk *clk, ulong rate)
{
const struct clk_ops *ops;
debug("%s(clk=%p, rate=%lu)\n", __func__, clk, rate);
if (!clk_valid(clk))
return 0;
ops = clk_dev_ops(clk->dev);
if (!ops->round_rate)
return -ENOSYS;
return ops->round_rate(clk, rate);
}
clk: update clk_clean_rate_cache to use private clk struct In clk_clean_rate_cache, clk->rate should update the private clock struct, in particular when CCF is activated, to save the cached rate value. When clk_get_parent_rate is called, the cached information is read from pclk->rate, with pclk = clk_get_parent(clk). As the cached is read from private clk data, the update should be done also on it. Fixes: 6b7fd3128f7 ("clk: fix set_rate to clean up cached rates for the hierarchy") Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Sean Anderson <seanga2@gmail.com> Link: https://lore.kernel.org/r/20220620153717.v2.1.Ifa06360115ffa3f3307372e6cdd98ec16759d6ba@changeid Link: https://lore.kernel.org/r/20220712142352.RESEND.v2.1.Ifa06360115ffa3f3307372e6cdd98ec16759d6ba@changeid/
2022-06-20 13:37:25 +00:00
static void clk_get_priv(struct clk *clk, struct clk **clkp)
{
*clkp = clk;
/* get private clock struct associated to the provided clock */
if (CONFIG_IS_ENABLED(CLK_CCF)) {
/* Take id 0 as a non-valid clk, such as dummy */
if (clk->id)
clk_get_by_id(clk->id, clkp);
}
}
/* clean cache, called with private clock struct */
clk: fix set_rate to clean up cached rates for the hierarchy Clock rates are cached within the individual clock nodes, and right now if one changes a clock rate somewhere in the middle of the tree, none of its child clocks notice the change. To fix this, clear up all the cached rates for us and our child clocks. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
2021-06-11 08:45:12 +00:00
static void clk_clean_rate_cache(struct clk *clk)
{
struct udevice *child_dev;
struct clk *clkp;
if (!clk)
return;
clk->rate = 0;
list_for_each_entry(child_dev, &clk->dev->child_head, sibling_node) {
clkp = dev_get_clk_ptr(child_dev);
clk_clean_rate_cache(clkp);
}
}
clk: convert API to match reset/mailbox style The following changes are made to the clock API: * The concept of "clocks" and "peripheral clocks" are unified; each clock provider now implements a single set of clocks. This provides a simpler conceptual interface to clients, and better aligns with device tree clock bindings. * Clocks are now identified with a single "struct clk", rather than requiring clients to store the clock provider device and clock identity values separately. For simple clock consumers, this isolates clients from internal details of the clock API. * clk.h is split so it only contains the client/consumer API, whereas clk-uclass.h contains the provider API. This aligns with the recently added reset and mailbox APIs. * clk_ops .of_xlate(), .request(), and .free() are added so providers can customize these operations if needed. This also aligns with the recently added reset and mailbox APIs. * clk_disable() is added. * All users of the current clock APIs are updated. * Sandbox clock tests are updated to exercise clock lookup via DT, and clock enable/disable. * rkclk_get_clk() is removed and replaced with standard APIs. Buildman shows no clock-related errors for any board for which buildman can download a toolchain. test/py passes for sandbox (which invokes the dm clk test amongst others). Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org>
2016-06-17 15:44:00 +00:00
ulong clk_set_rate(struct clk *clk, ulong rate)
{
drivers: clk: Handle gracefully NULL pointers Prepare the way for a managed CLK API by handling NULL pointers without crashing nor failing. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2019-10-22 12:00:03 +00:00
const struct clk_ops *ops;
clk: update clk_clean_rate_cache to use private clk struct In clk_clean_rate_cache, clk->rate should update the private clock struct, in particular when CCF is activated, to save the cached rate value. When clk_get_parent_rate is called, the cached information is read from pclk->rate, with pclk = clk_get_parent(clk). As the cached is read from private clk data, the update should be done also on it. Fixes: 6b7fd3128f7 ("clk: fix set_rate to clean up cached rates for the hierarchy") Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Sean Anderson <seanga2@gmail.com> Link: https://lore.kernel.org/r/20220620153717.v2.1.Ifa06360115ffa3f3307372e6cdd98ec16759d6ba@changeid Link: https://lore.kernel.org/r/20220712142352.RESEND.v2.1.Ifa06360115ffa3f3307372e6cdd98ec16759d6ba@changeid/
2022-06-20 13:37:25 +00:00
struct clk *clkp;
clk: convert API to match reset/mailbox style The following changes are made to the clock API: * The concept of "clocks" and "peripheral clocks" are unified; each clock provider now implements a single set of clocks. This provides a simpler conceptual interface to clients, and better aligns with device tree clock bindings. * Clocks are now identified with a single "struct clk", rather than requiring clients to store the clock provider device and clock identity values separately. For simple clock consumers, this isolates clients from internal details of the clock API. * clk.h is split so it only contains the client/consumer API, whereas clk-uclass.h contains the provider API. This aligns with the recently added reset and mailbox APIs. * clk_ops .of_xlate(), .request(), and .free() are added so providers can customize these operations if needed. This also aligns with the recently added reset and mailbox APIs. * clk_disable() is added. * All users of the current clock APIs are updated. * Sandbox clock tests are updated to exercise clock lookup via DT, and clock enable/disable. * rkclk_get_clk() is removed and replaced with standard APIs. Buildman shows no clock-related errors for any board for which buildman can download a toolchain. test/py passes for sandbox (which invokes the dm clk test amongst others). Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org>
2016-06-17 15:44:00 +00:00
debug("%s(clk=%p, rate=%lu)\n", __func__, clk, rate);
clk: check valid clock by clk_valid() Add valid check for clk->dev, it's useful when get optional clock even when the clk point is valid, but its dev will be NULL. Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Ryder Lee <ryder.lee@mediatek.com>
2020-01-09 03:35:06 +00:00
if (!clk_valid(clk))
drivers: clk: Handle gracefully NULL pointers Prepare the way for a managed CLK API by handling NULL pointers without crashing nor failing. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2019-10-22 12:00:03 +00:00
return 0;
ops = clk_dev_ops(clk->dev);
clk: convert API to match reset/mailbox style The following changes are made to the clock API: * The concept of "clocks" and "peripheral clocks" are unified; each clock provider now implements a single set of clocks. This provides a simpler conceptual interface to clients, and better aligns with device tree clock bindings. * Clocks are now identified with a single "struct clk", rather than requiring clients to store the clock provider device and clock identity values separately. For simple clock consumers, this isolates clients from internal details of the clock API. * clk.h is split so it only contains the client/consumer API, whereas clk-uclass.h contains the provider API. This aligns with the recently added reset and mailbox APIs. * clk_ops .of_xlate(), .request(), and .free() are added so providers can customize these operations if needed. This also aligns with the recently added reset and mailbox APIs. * clk_disable() is added. * All users of the current clock APIs are updated. * Sandbox clock tests are updated to exercise clock lookup via DT, and clock enable/disable. * rkclk_get_clk() is removed and replaced with standard APIs. Buildman shows no clock-related errors for any board for which buildman can download a toolchain. test/py passes for sandbox (which invokes the dm clk test amongst others). Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org>
2016-06-17 15:44:00 +00:00
if (!ops->set_rate)
return -ENOSYS;
clk: update clk_clean_rate_cache to use private clk struct In clk_clean_rate_cache, clk->rate should update the private clock struct, in particular when CCF is activated, to save the cached rate value. When clk_get_parent_rate is called, the cached information is read from pclk->rate, with pclk = clk_get_parent(clk). As the cached is read from private clk data, the update should be done also on it. Fixes: 6b7fd3128f7 ("clk: fix set_rate to clean up cached rates for the hierarchy") Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Sean Anderson <seanga2@gmail.com> Link: https://lore.kernel.org/r/20220620153717.v2.1.Ifa06360115ffa3f3307372e6cdd98ec16759d6ba@changeid Link: https://lore.kernel.org/r/20220712142352.RESEND.v2.1.Ifa06360115ffa3f3307372e6cdd98ec16759d6ba@changeid/
2022-06-20 13:37:25 +00:00
/* get private clock struct used for cache */
clk_get_priv(clk, &clkp);
clk: fix set_rate to clean up cached rates for the hierarchy Clock rates are cached within the individual clock nodes, and right now if one changes a clock rate somewhere in the middle of the tree, none of its child clocks notice the change. To fix this, clear up all the cached rates for us and our child clocks. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
2021-06-11 08:45:12 +00:00
/* Clean up cached rates for us and all child clocks */
clk: update clk_clean_rate_cache to use private clk struct In clk_clean_rate_cache, clk->rate should update the private clock struct, in particular when CCF is activated, to save the cached rate value. When clk_get_parent_rate is called, the cached information is read from pclk->rate, with pclk = clk_get_parent(clk). As the cached is read from private clk data, the update should be done also on it. Fixes: 6b7fd3128f7 ("clk: fix set_rate to clean up cached rates for the hierarchy") Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Sean Anderson <seanga2@gmail.com> Link: https://lore.kernel.org/r/20220620153717.v2.1.Ifa06360115ffa3f3307372e6cdd98ec16759d6ba@changeid Link: https://lore.kernel.org/r/20220712142352.RESEND.v2.1.Ifa06360115ffa3f3307372e6cdd98ec16759d6ba@changeid/
2022-06-20 13:37:25 +00:00
clk_clean_rate_cache(clkp);
clk: fix set_rate to clean up cached rates for the hierarchy Clock rates are cached within the individual clock nodes, and right now if one changes a clock rate somewhere in the middle of the tree, none of its child clocks notice the change. To fix this, clear up all the cached rates for us and our child clocks. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
2021-06-11 08:45:12 +00:00
clk: convert API to match reset/mailbox style The following changes are made to the clock API: * The concept of "clocks" and "peripheral clocks" are unified; each clock provider now implements a single set of clocks. This provides a simpler conceptual interface to clients, and better aligns with device tree clock bindings. * Clocks are now identified with a single "struct clk", rather than requiring clients to store the clock provider device and clock identity values separately. For simple clock consumers, this isolates clients from internal details of the clock API. * clk.h is split so it only contains the client/consumer API, whereas clk-uclass.h contains the provider API. This aligns with the recently added reset and mailbox APIs. * clk_ops .of_xlate(), .request(), and .free() are added so providers can customize these operations if needed. This also aligns with the recently added reset and mailbox APIs. * clk_disable() is added. * All users of the current clock APIs are updated. * Sandbox clock tests are updated to exercise clock lookup via DT, and clock enable/disable. * rkclk_get_clk() is removed and replaced with standard APIs. Buildman shows no clock-related errors for any board for which buildman can download a toolchain. test/py passes for sandbox (which invokes the dm clk test amongst others). Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org>
2016-06-17 15:44:00 +00:00
return ops->set_rate(clk, rate);
}
clk: add clk_set_parent() Clocks may support multiple parents: this change introduces an optional operation on the clk-uclass to set a clock's parent. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Tested-by: David Wu <david.wu@rock-chips.com> Series-changes: 2 - Fixed David's email address.
2018-01-08 10:15:08 +00:00
int clk_set_parent(struct clk *clk, struct clk *parent)
{
drivers: clk: Handle gracefully NULL pointers Prepare the way for a managed CLK API by handling NULL pointers without crashing nor failing. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2019-10-22 12:00:03 +00:00
const struct clk_ops *ops;
clk: bind clk to new parent device Clock re-parenting is not binding the clock's device to its new parent device, it only calls the clock's ops->set_parent() API. The changes in this commit re-parent the clock device to its new parent so that subsequent operations like clk_get_parent() to point to the proper parent. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2020-09-07 14:46:34 +00:00
int ret;
clk: add clk_set_parent() Clocks may support multiple parents: this change introduces an optional operation on the clk-uclass to set a clock's parent. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Tested-by: David Wu <david.wu@rock-chips.com> Series-changes: 2 - Fixed David's email address.
2018-01-08 10:15:08 +00:00
debug("%s(clk=%p, parent=%p)\n", __func__, clk, parent);
clk: check valid clock by clk_valid() Add valid check for clk->dev, it's useful when get optional clock even when the clk point is valid, but its dev will be NULL. Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Ryder Lee <ryder.lee@mediatek.com>
2020-01-09 03:35:06 +00:00
if (!clk_valid(clk))
drivers: clk: Handle gracefully NULL pointers Prepare the way for a managed CLK API by handling NULL pointers without crashing nor failing. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2019-10-22 12:00:03 +00:00
return 0;
ops = clk_dev_ops(clk->dev);
clk: add clk_set_parent() Clocks may support multiple parents: this change introduces an optional operation on the clk-uclass to set a clock's parent. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Tested-by: David Wu <david.wu@rock-chips.com> Series-changes: 2 - Fixed David's email address.
2018-01-08 10:15:08 +00:00
if (!ops->set_parent)
return -ENOSYS;
clk: bind clk to new parent device Clock re-parenting is not binding the clock's device to its new parent device, it only calls the clock's ops->set_parent() API. The changes in this commit re-parent the clock device to its new parent so that subsequent operations like clk_get_parent() to point to the proper parent. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2020-09-07 14:46:34 +00:00
ret = ops->set_parent(clk, parent);
if (ret)
return ret;
if (CONFIG_IS_ENABLED(CLK_CCF))
ret = device_reparent(clk->dev, parent->dev);
return ret;
clk: add clk_set_parent() Clocks may support multiple parents: this change introduces an optional operation on the clk-uclass to set a clock's parent. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Tested-by: David Wu <david.wu@rock-chips.com> Series-changes: 2 - Fixed David's email address.
2018-01-08 10:15:08 +00:00
}
clk: convert API to match reset/mailbox style The following changes are made to the clock API: * The concept of "clocks" and "peripheral clocks" are unified; each clock provider now implements a single set of clocks. This provides a simpler conceptual interface to clients, and better aligns with device tree clock bindings. * Clocks are now identified with a single "struct clk", rather than requiring clients to store the clock provider device and clock identity values separately. For simple clock consumers, this isolates clients from internal details of the clock API. * clk.h is split so it only contains the client/consumer API, whereas clk-uclass.h contains the provider API. This aligns with the recently added reset and mailbox APIs. * clk_ops .of_xlate(), .request(), and .free() are added so providers can customize these operations if needed. This also aligns with the recently added reset and mailbox APIs. * clk_disable() is added. * All users of the current clock APIs are updated. * Sandbox clock tests are updated to exercise clock lookup via DT, and clock enable/disable. * rkclk_get_clk() is removed and replaced with standard APIs. Buildman shows no clock-related errors for any board for which buildman can download a toolchain. test/py passes for sandbox (which invokes the dm clk test amongst others). Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org>
2016-06-17 15:44:00 +00:00
int clk_enable(struct clk *clk)
{
drivers: clk: Handle gracefully NULL pointers Prepare the way for a managed CLK API by handling NULL pointers without crashing nor failing. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2019-10-22 12:00:03 +00:00
const struct clk_ops *ops;
clk: prograte clk enable/disable to parent On i.MX8MM, thinking such as clk path OSC->PLL->PLL GATE->CCM ROOT->CCGR GATE->Device Only enabling CCGR GATE is not enough, we also need to enable PLL GATE to make sure the clk path work. So when enabling CCGR GATE, we could prograte to enabling PLL GATE to make life easier. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-08-21 13:35:09 +00:00
struct clk *clkp = NULL;
int ret;
clk: convert API to match reset/mailbox style The following changes are made to the clock API: * The concept of "clocks" and "peripheral clocks" are unified; each clock provider now implements a single set of clocks. This provides a simpler conceptual interface to clients, and better aligns with device tree clock bindings. * Clocks are now identified with a single "struct clk", rather than requiring clients to store the clock provider device and clock identity values separately. For simple clock consumers, this isolates clients from internal details of the clock API. * clk.h is split so it only contains the client/consumer API, whereas clk-uclass.h contains the provider API. This aligns with the recently added reset and mailbox APIs. * clk_ops .of_xlate(), .request(), and .free() are added so providers can customize these operations if needed. This also aligns with the recently added reset and mailbox APIs. * clk_disable() is added. * All users of the current clock APIs are updated. * Sandbox clock tests are updated to exercise clock lookup via DT, and clock enable/disable. * rkclk_get_clk() is removed and replaced with standard APIs. Buildman shows no clock-related errors for any board for which buildman can download a toolchain. test/py passes for sandbox (which invokes the dm clk test amongst others). Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org>
2016-06-17 15:44:00 +00:00
debug("%s(clk=%p)\n", __func__, clk);
clk: check valid clock by clk_valid() Add valid check for clk->dev, it's useful when get optional clock even when the clk point is valid, but its dev will be NULL. Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Ryder Lee <ryder.lee@mediatek.com>
2020-01-09 03:35:06 +00:00
if (!clk_valid(clk))
drivers: clk: Handle gracefully NULL pointers Prepare the way for a managed CLK API by handling NULL pointers without crashing nor failing. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2019-10-22 12:00:03 +00:00
return 0;
ops = clk_dev_ops(clk->dev);
clk: convert API to match reset/mailbox style The following changes are made to the clock API: * The concept of "clocks" and "peripheral clocks" are unified; each clock provider now implements a single set of clocks. This provides a simpler conceptual interface to clients, and better aligns with device tree clock bindings. * Clocks are now identified with a single "struct clk", rather than requiring clients to store the clock provider device and clock identity values separately. For simple clock consumers, this isolates clients from internal details of the clock API. * clk.h is split so it only contains the client/consumer API, whereas clk-uclass.h contains the provider API. This aligns with the recently added reset and mailbox APIs. * clk_ops .of_xlate(), .request(), and .free() are added so providers can customize these operations if needed. This also aligns with the recently added reset and mailbox APIs. * clk_disable() is added. * All users of the current clock APIs are updated. * Sandbox clock tests are updated to exercise clock lookup via DT, and clock enable/disable. * rkclk_get_clk() is removed and replaced with standard APIs. Buildman shows no clock-related errors for any board for which buildman can download a toolchain. test/py passes for sandbox (which invokes the dm clk test amongst others). Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org>
2016-06-17 15:44:00 +00:00
clk: prograte clk enable/disable to parent On i.MX8MM, thinking such as clk path OSC->PLL->PLL GATE->CCM ROOT->CCGR GATE->Device Only enabling CCGR GATE is not enough, we also need to enable PLL GATE to make sure the clk path work. So when enabling CCGR GATE, we could prograte to enabling PLL GATE to make life easier. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-08-21 13:35:09 +00:00
if (CONFIG_IS_ENABLED(CLK_CCF)) {
/* Take id 0 as a non-valid clk, such as dummy */
if (clk->id && !clk_get_by_id(clk->id, &clkp)) {
if (clkp->enable_count) {
clkp->enable_count++;
return 0;
}
if (clkp->dev->parent &&
clk: ccf: correct the test on the parent uclass in clk_enable/clk_disable It is safe to check if the uclass id on the device is UCLASS_CLK before to call the clk_ functions, but today this comparison is not done on the device used in API: clkp->dev->parent but on the device himself: clkp->dev. This patch corrects this behavior and tests if the parent device is a clock device before to call the clock API, clk_enable or clk_disable, on this device. Fixes: 0520be0f67e3 ("clk: prograte clk enable/disable to parent") Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Sean Anderson <seanga2@gmail.com>
2022-01-24 13:17:14 +00:00
device_get_uclass_id(clkp->dev->parent) == UCLASS_CLK) {
clk: prograte clk enable/disable to parent On i.MX8MM, thinking such as clk path OSC->PLL->PLL GATE->CCM ROOT->CCGR GATE->Device Only enabling CCGR GATE is not enough, we also need to enable PLL GATE to make sure the clk path work. So when enabling CCGR GATE, we could prograte to enabling PLL GATE to make life easier. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-08-21 13:35:09 +00:00
ret = clk_enable(dev_get_clk_ptr(clkp->dev->parent));
if (ret) {
printf("Enable %s failed\n",
clkp->dev->parent->name);
return ret;
}
}
}
clk: convert API to match reset/mailbox style The following changes are made to the clock API: * The concept of "clocks" and "peripheral clocks" are unified; each clock provider now implements a single set of clocks. This provides a simpler conceptual interface to clients, and better aligns with device tree clock bindings. * Clocks are now identified with a single "struct clk", rather than requiring clients to store the clock provider device and clock identity values separately. For simple clock consumers, this isolates clients from internal details of the clock API. * clk.h is split so it only contains the client/consumer API, whereas clk-uclass.h contains the provider API. This aligns with the recently added reset and mailbox APIs. * clk_ops .of_xlate(), .request(), and .free() are added so providers can customize these operations if needed. This also aligns with the recently added reset and mailbox APIs. * clk_disable() is added. * All users of the current clock APIs are updated. * Sandbox clock tests are updated to exercise clock lookup via DT, and clock enable/disable. * rkclk_get_clk() is removed and replaced with standard APIs. Buildman shows no clock-related errors for any board for which buildman can download a toolchain. test/py passes for sandbox (which invokes the dm clk test amongst others). Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org>
2016-06-17 15:44:00 +00:00
clk: prograte clk enable/disable to parent On i.MX8MM, thinking such as clk path OSC->PLL->PLL GATE->CCM ROOT->CCGR GATE->Device Only enabling CCGR GATE is not enough, we also need to enable PLL GATE to make sure the clk path work. So when enabling CCGR GATE, we could prograte to enabling PLL GATE to make life easier. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-08-21 13:35:09 +00:00
if (ops->enable) {
ret = ops->enable(clk);
if (ret) {
printf("Enable %s failed\n", clk->dev->name);
return ret;
}
}
if (clkp)
clkp->enable_count++;
} else {
if (!ops->enable)
return -ENOSYS;
return ops->enable(clk);
}
return 0;
clk: convert API to match reset/mailbox style The following changes are made to the clock API: * The concept of "clocks" and "peripheral clocks" are unified; each clock provider now implements a single set of clocks. This provides a simpler conceptual interface to clients, and better aligns with device tree clock bindings. * Clocks are now identified with a single "struct clk", rather than requiring clients to store the clock provider device and clock identity values separately. For simple clock consumers, this isolates clients from internal details of the clock API. * clk.h is split so it only contains the client/consumer API, whereas clk-uclass.h contains the provider API. This aligns with the recently added reset and mailbox APIs. * clk_ops .of_xlate(), .request(), and .free() are added so providers can customize these operations if needed. This also aligns with the recently added reset and mailbox APIs. * clk_disable() is added. * All users of the current clock APIs are updated. * Sandbox clock tests are updated to exercise clock lookup via DT, and clock enable/disable. * rkclk_get_clk() is removed and replaced with standard APIs. Buildman shows no clock-related errors for any board for which buildman can download a toolchain. test/py passes for sandbox (which invokes the dm clk test amongst others). Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org>
2016-06-17 15:44:00 +00:00
}
clk: Add get/enable/disable/release for a bulk of clocks This patch adds a "bulk" API to the clock API in order to get/enable/disable /release a group of clocks associated with a device. This bulk API will avoid adding a copy of the same code to manage a group of clocks in drivers. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2018-04-03 09:44:18 +00:00
int clk_enable_bulk(struct clk_bulk *bulk)
{
int i, ret;
for (i = 0; i < bulk->count; i++) {
ret = clk_enable(&bulk->clks[i]);
if (ret < 0 && ret != -ENOSYS)
return ret;
}
return 0;
}
clk: convert API to match reset/mailbox style The following changes are made to the clock API: * The concept of "clocks" and "peripheral clocks" are unified; each clock provider now implements a single set of clocks. This provides a simpler conceptual interface to clients, and better aligns with device tree clock bindings. * Clocks are now identified with a single "struct clk", rather than requiring clients to store the clock provider device and clock identity values separately. For simple clock consumers, this isolates clients from internal details of the clock API. * clk.h is split so it only contains the client/consumer API, whereas clk-uclass.h contains the provider API. This aligns with the recently added reset and mailbox APIs. * clk_ops .of_xlate(), .request(), and .free() are added so providers can customize these operations if needed. This also aligns with the recently added reset and mailbox APIs. * clk_disable() is added. * All users of the current clock APIs are updated. * Sandbox clock tests are updated to exercise clock lookup via DT, and clock enable/disable. * rkclk_get_clk() is removed and replaced with standard APIs. Buildman shows no clock-related errors for any board for which buildman can download a toolchain. test/py passes for sandbox (which invokes the dm clk test amongst others). Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org>
2016-06-17 15:44:00 +00:00
int clk_disable(struct clk *clk)
{
drivers: clk: Handle gracefully NULL pointers Prepare the way for a managed CLK API by handling NULL pointers without crashing nor failing. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2019-10-22 12:00:03 +00:00
const struct clk_ops *ops;
clk: prograte clk enable/disable to parent On i.MX8MM, thinking such as clk path OSC->PLL->PLL GATE->CCM ROOT->CCGR GATE->Device Only enabling CCGR GATE is not enough, we also need to enable PLL GATE to make sure the clk path work. So when enabling CCGR GATE, we could prograte to enabling PLL GATE to make life easier. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-08-21 13:35:09 +00:00
struct clk *clkp = NULL;
int ret;
clk: convert API to match reset/mailbox style The following changes are made to the clock API: * The concept of "clocks" and "peripheral clocks" are unified; each clock provider now implements a single set of clocks. This provides a simpler conceptual interface to clients, and better aligns with device tree clock bindings. * Clocks are now identified with a single "struct clk", rather than requiring clients to store the clock provider device and clock identity values separately. For simple clock consumers, this isolates clients from internal details of the clock API. * clk.h is split so it only contains the client/consumer API, whereas clk-uclass.h contains the provider API. This aligns with the recently added reset and mailbox APIs. * clk_ops .of_xlate(), .request(), and .free() are added so providers can customize these operations if needed. This also aligns with the recently added reset and mailbox APIs. * clk_disable() is added. * All users of the current clock APIs are updated. * Sandbox clock tests are updated to exercise clock lookup via DT, and clock enable/disable. * rkclk_get_clk() is removed and replaced with standard APIs. Buildman shows no clock-related errors for any board for which buildman can download a toolchain. test/py passes for sandbox (which invokes the dm clk test amongst others). Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org>
2016-06-17 15:44:00 +00:00
debug("%s(clk=%p)\n", __func__, clk);
clk: check valid clock by clk_valid() Add valid check for clk->dev, it's useful when get optional clock even when the clk point is valid, but its dev will be NULL. Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Ryder Lee <ryder.lee@mediatek.com>
2020-01-09 03:35:06 +00:00
if (!clk_valid(clk))
drivers: clk: Handle gracefully NULL pointers Prepare the way for a managed CLK API by handling NULL pointers without crashing nor failing. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2019-10-22 12:00:03 +00:00
return 0;
ops = clk_dev_ops(clk->dev);
clk: convert API to match reset/mailbox style The following changes are made to the clock API: * The concept of "clocks" and "peripheral clocks" are unified; each clock provider now implements a single set of clocks. This provides a simpler conceptual interface to clients, and better aligns with device tree clock bindings. * Clocks are now identified with a single "struct clk", rather than requiring clients to store the clock provider device and clock identity values separately. For simple clock consumers, this isolates clients from internal details of the clock API. * clk.h is split so it only contains the client/consumer API, whereas clk-uclass.h contains the provider API. This aligns with the recently added reset and mailbox APIs. * clk_ops .of_xlate(), .request(), and .free() are added so providers can customize these operations if needed. This also aligns with the recently added reset and mailbox APIs. * clk_disable() is added. * All users of the current clock APIs are updated. * Sandbox clock tests are updated to exercise clock lookup via DT, and clock enable/disable. * rkclk_get_clk() is removed and replaced with standard APIs. Buildman shows no clock-related errors for any board for which buildman can download a toolchain. test/py passes for sandbox (which invokes the dm clk test amongst others). Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org>
2016-06-17 15:44:00 +00:00
clk: prograte clk enable/disable to parent On i.MX8MM, thinking such as clk path OSC->PLL->PLL GATE->CCM ROOT->CCGR GATE->Device Only enabling CCGR GATE is not enough, we also need to enable PLL GATE to make sure the clk path work. So when enabling CCGR GATE, we could prograte to enabling PLL GATE to make life easier. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-08-21 13:35:09 +00:00
if (CONFIG_IS_ENABLED(CLK_CCF)) {
if (clk->id && !clk_get_by_id(clk->id, &clkp)) {
clk: do not disable clock if it is critical Do not disable clock if it is a critical one. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2020-09-07 14:46:35 +00:00
if (clkp->flags & CLK_IS_CRITICAL)
return 0;
clk: prograte clk enable/disable to parent On i.MX8MM, thinking such as clk path OSC->PLL->PLL GATE->CCM ROOT->CCGR GATE->Device Only enabling CCGR GATE is not enough, we also need to enable PLL GATE to make sure the clk path work. So when enabling CCGR GATE, we could prograte to enabling PLL GATE to make life easier. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-08-21 13:35:09 +00:00
if (clkp->enable_count == 0) {
printf("clk %s already disabled\n",
clkp->dev->name);
return 0;
}
clk: convert API to match reset/mailbox style The following changes are made to the clock API: * The concept of "clocks" and "peripheral clocks" are unified; each clock provider now implements a single set of clocks. This provides a simpler conceptual interface to clients, and better aligns with device tree clock bindings. * Clocks are now identified with a single "struct clk", rather than requiring clients to store the clock provider device and clock identity values separately. For simple clock consumers, this isolates clients from internal details of the clock API. * clk.h is split so it only contains the client/consumer API, whereas clk-uclass.h contains the provider API. This aligns with the recently added reset and mailbox APIs. * clk_ops .of_xlate(), .request(), and .free() are added so providers can customize these operations if needed. This also aligns with the recently added reset and mailbox APIs. * clk_disable() is added. * All users of the current clock APIs are updated. * Sandbox clock tests are updated to exercise clock lookup via DT, and clock enable/disable. * rkclk_get_clk() is removed and replaced with standard APIs. Buildman shows no clock-related errors for any board for which buildman can download a toolchain. test/py passes for sandbox (which invokes the dm clk test amongst others). Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org>
2016-06-17 15:44:00 +00:00
clk: prograte clk enable/disable to parent On i.MX8MM, thinking such as clk path OSC->PLL->PLL GATE->CCM ROOT->CCGR GATE->Device Only enabling CCGR GATE is not enough, we also need to enable PLL GATE to make sure the clk path work. So when enabling CCGR GATE, we could prograte to enabling PLL GATE to make life easier. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-08-21 13:35:09 +00:00
if (--clkp->enable_count > 0)
return 0;
}
if (ops->disable) {
ret = ops->disable(clk);
if (ret)
return ret;
}
if (clkp && clkp->dev->parent &&
clk: ccf: correct the test on the parent uclass in clk_enable/clk_disable It is safe to check if the uclass id on the device is UCLASS_CLK before to call the clk_ functions, but today this comparison is not done on the device used in API: clkp->dev->parent but on the device himself: clkp->dev. This patch corrects this behavior and tests if the parent device is a clock device before to call the clock API, clk_enable or clk_disable, on this device. Fixes: 0520be0f67e3 ("clk: prograte clk enable/disable to parent") Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Sean Anderson <seanga2@gmail.com>
2022-01-24 13:17:14 +00:00
device_get_uclass_id(clkp->dev->parent) == UCLASS_CLK) {
clk: prograte clk enable/disable to parent On i.MX8MM, thinking such as clk path OSC->PLL->PLL GATE->CCM ROOT->CCGR GATE->Device Only enabling CCGR GATE is not enough, we also need to enable PLL GATE to make sure the clk path work. So when enabling CCGR GATE, we could prograte to enabling PLL GATE to make life easier. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-08-21 13:35:09 +00:00
ret = clk_disable(dev_get_clk_ptr(clkp->dev->parent));
if (ret) {
printf("Disable %s failed\n",
clkp->dev->parent->name);
return ret;
}
}
} else {
if (!ops->disable)
return -ENOSYS;
return ops->disable(clk);
}
return 0;
clk: convert API to match reset/mailbox style The following changes are made to the clock API: * The concept of "clocks" and "peripheral clocks" are unified; each clock provider now implements a single set of clocks. This provides a simpler conceptual interface to clients, and better aligns with device tree clock bindings. * Clocks are now identified with a single "struct clk", rather than requiring clients to store the clock provider device and clock identity values separately. For simple clock consumers, this isolates clients from internal details of the clock API. * clk.h is split so it only contains the client/consumer API, whereas clk-uclass.h contains the provider API. This aligns with the recently added reset and mailbox APIs. * clk_ops .of_xlate(), .request(), and .free() are added so providers can customize these operations if needed. This also aligns with the recently added reset and mailbox APIs. * clk_disable() is added. * All users of the current clock APIs are updated. * Sandbox clock tests are updated to exercise clock lookup via DT, and clock enable/disable. * rkclk_get_clk() is removed and replaced with standard APIs. Buildman shows no clock-related errors for any board for which buildman can download a toolchain. test/py passes for sandbox (which invokes the dm clk test amongst others). Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org>
2016-06-17 15:44:00 +00:00
}
dm: clk: Add support for decoding clocks from the device tree Add a method which can locate a clock for a device, given its index. This uses the normal device tree bindings to return the clock device and the first argument which is normally used as a peripheral ID in U-Boot. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-01-21 02:43:02 +00:00
clk: Add get/enable/disable/release for a bulk of clocks This patch adds a "bulk" API to the clock API in order to get/enable/disable /release a group of clocks associated with a device. This bulk API will avoid adding a copy of the same code to manage a group of clocks in drivers. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2018-04-03 09:44:18 +00:00
int clk_disable_bulk(struct clk_bulk *bulk)
{
int i, ret;
for (i = 0; i < bulk->count; i++) {
ret = clk_disable(&bulk->clks[i]);
if (ret < 0 && ret != -ENOSYS)
return ret;
}
return 0;
}
dm: clk: Define clk_get_by_id() for clk operations This commit adds the clk_get_by_id() function, which is responsible for getting the udevice with matching clk->id. Such approach allows re-usage of inherit DM list relationship for the same class (UCLASS_CLK). As a result - we don't need any other external list - it is just enough to look for UCLASS_CLK related udevices. Signed-off-by: Lukasz Majewski <lukma@denx.de> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2019-06-24 13:50:44 +00:00
int clk_get_by_id(ulong id, struct clk **clkp)
{
struct udevice *dev;
struct uclass *uc;
int ret;
ret = uclass_get(UCLASS_CLK, &uc);
if (ret)
return ret;
uclass_foreach_dev(dev, uc) {
struct clk *clk = dev_get_clk_ptr(dev);
if (clk && clk->id == id) {
*clkp = clk;
return 0;
}
}
return -ENOENT;
}
clk: add support for clk_is_match() Add support for clk_is_match() which is required to know if two clock pointers point to the same exact physical clock. Also add a unit test for the new API. Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com>
2019-08-01 13:42:55 +00:00
bool clk_is_match(const struct clk *p, const struct clk *q)
{
/* trivial case: identical struct clk's or both NULL */
if (p == q)
return true;
drivers: clk: Handle gracefully NULL pointers Prepare the way for a managed CLK API by handling NULL pointers without crashing nor failing. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2019-10-22 12:00:03 +00:00
/* trivial case #2: on the clk pointer is NULL */
if (!p || !q)
return false;
clk: add support for clk_is_match() Add support for clk_is_match() which is required to know if two clock pointers point to the same exact physical clock. Also add a unit test for the new API. Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com>
2019-08-01 13:42:55 +00:00
/* same device, id and data */
if (p->dev == q->dev && p->id == q->id && p->data == q->data)
return true;
return false;
}
drivers: clk: Add a managed API to get clocks from the device-tree Add devm_clk_get(), devm_clk_get_optional() to get clocks from the device-tree. The clocks is automatically released and the data structure freed when the device is unbound. Also add devm_clk_put() to release the clock and free the data structure manually. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2019-10-22 12:00:04 +00:00
static void devm_clk_release(struct udevice *dev, void *res)
{
clk_free(res);
}
static int devm_clk_match(struct udevice *dev, void *res, void *data)
{
return res == data;
}
struct clk *devm_clk_get(struct udevice *dev, const char *id)
{
int rc;
struct clk *clk;
clk = devres_alloc(devm_clk_release, sizeof(struct clk), __GFP_ZERO);
if (unlikely(!clk))
return ERR_PTR(-ENOMEM);
rc = clk_get_by_name(dev, id, clk);
if (rc)
return ERR_PTR(rc);
devres_add(dev, clk);
return clk;
}
void devm_clk_put(struct udevice *dev, struct clk *clk)
{
int rc;
if (!clk)
return;
rc = devres_release(dev, devm_clk_release, devm_clk_match, clk);
WARN_ON(rc);
}
drivers: clk: Fix using assigned-clocks in the node of the clock it sets up This fixes the case where assigned-clocks is used to define a clock defaults inside this same clock's node. This is used sometimes to setup a default parents and/or rate for a clock. example: muxed_clock: muxed_clock { clocks = <&clk_provider 0>, <&clk_provider 1>; #clock-cells = <0>; assigned-clocks = <&muxed_clock>; assigned-clock-parents = <&clk_provider 1>; }; It doesn't work in u-boot because the assigned-clocks are setup *before* the clock is probed. (clk_set_parent() will likely crash or fail if called before the device probe function) Making it work by handling "assigned-clocks" in 2 steps: first before the clk device is probed, and then after the clk device is probed. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2019-10-22 12:00:06 +00:00
int clk_uclass_post_probe(struct udevice *dev)
{
/*
* when a clock provider is probed. Call clk_set_defaults()
* also after the device is probed. This takes care of cases
* where the DT is used to setup default parents and rates
* using assigned-clocks
*/
Revert "clk: Detect failure to set defaults" This reverts commit 92f1e9a4b31c0bf0f4f61ab823a6a88657323646. The aforementioned patch causes massive breakage on all platforms which have 'assigned-clock' DT property in their DT which references any clock that are not supported by the platform clock driver. That can easily happen either in SPL, or because the clock driver is reduced. Currently it seems all iMX8M are affected and fail to boot altogether. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Peng Fan <peng.fan@oss.nxp.com> Cc: Simon Glass <sjg@chromium.org> Reviewed-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Fabio Estevam <festevam@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2022-01-01 18:51:39 +00:00
clk_set_defaults(dev, CLK_DEFAULTS_POST);
drivers: clk: Fix using assigned-clocks in the node of the clock it sets up This fixes the case where assigned-clocks is used to define a clock defaults inside this same clock's node. This is used sometimes to setup a default parents and/or rate for a clock. example: muxed_clock: muxed_clock { clocks = <&clk_provider 0>, <&clk_provider 1>; #clock-cells = <0>; assigned-clocks = <&muxed_clock>; assigned-clock-parents = <&clk_provider 1>; }; It doesn't work in u-boot because the assigned-clocks are setup *before* the clock is probed. (clk_set_parent() will likely crash or fail if called before the device probe function) Making it work by handling "assigned-clocks" in 2 steps: first before the clk device is probed, and then after the clk device is probed. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2019-10-22 12:00:06 +00:00
return 0;
}
dm: Add a clock uclass Clocks are an important feature of platforms and have become increasing complex with time. Most modern SoCs have multiple PLLs and dozens of clock dividers which distribute clocks to on-chip peripherals. Some SoC implementations have a clock API which is private to that SoC family, e.g. Tegra and Exynos. This is useful but it would be better to have a common API that can be understood and used throughout U-Boot. Add a simple clock API as a starting point. It supports querying and setting the rate of a clock. Each clock is a device. To reduce memory and processing overhead the concept of peripheral clocks is provided. These do not need to be explicit devices - it is possible to write a driver that can adjust the I2C clock (for example) without an explicit I2C clock device. This can dramatically reduce the number of devices (and associated overhead) in a complex SoC. Clocks are referenced by a number, and it is expected that SoCs will define that numbering themselves via an enum. Signed-off-by: Simon Glass <sjg@chromium.org>
2015-06-23 21:39:15 +00:00
UCLASS_DRIVER(clk) = {
.id = UCLASS_CLK,
.name = "clk",
drivers: clk: Fix using assigned-clocks in the node of the clock it sets up This fixes the case where assigned-clocks is used to define a clock defaults inside this same clock's node. This is used sometimes to setup a default parents and/or rate for a clock. example: muxed_clock: muxed_clock { clocks = <&clk_provider 0>, <&clk_provider 1>; #clock-cells = <0>; assigned-clocks = <&muxed_clock>; assigned-clock-parents = <&clk_provider 1>; }; It doesn't work in u-boot because the assigned-clocks are setup *before* the clock is probed. (clk_set_parent() will likely crash or fail if called before the device probe function) Making it work by handling "assigned-clocks" in 2 steps: first before the clk device is probed, and then after the clk device is probed. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2019-10-22 12:00:06 +00:00
.post_probe = clk_uclass_post_probe,
dm: Add a clock uclass Clocks are an important feature of platforms and have become increasing complex with time. Most modern SoCs have multiple PLLs and dozens of clock dividers which distribute clocks to on-chip peripherals. Some SoC implementations have a clock API which is private to that SoC family, e.g. Tegra and Exynos. This is useful but it would be better to have a common API that can be understood and used throughout U-Boot. Add a simple clock API as a starting point. It supports querying and setting the rate of a clock. Each clock is a device. To reduce memory and processing overhead the concept of peripheral clocks is provided. These do not need to be explicit devices - it is possible to write a driver that can adjust the I2C clock (for example) without an explicit I2C clock device. This can dramatically reduce the number of devices (and associated overhead) in a complex SoC. Clocks are referenced by a number, and it is expected that SoCs will define that numbering themselves via an enum. Signed-off-by: Simon Glass <sjg@chromium.org>
2015-06-23 21:39:15 +00:00
};
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