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u-boot/arch/arm/mach-k3/arm64-mmu.c

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armv8: K3: am654: Add custom MMU support Add MMU mappings for AM654 SoC. Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2018-08-27 10:27:13 +00:00
// SPDX-License-Identifier: GPL-2.0+
/*
* K3: ARM64 MMU setup
*
* Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
* Lokesh Vutla <lokeshvutla@ti.com>
arm64: zynqmp: Move SoC sources to mach-zynqmp Similar changes was done for Zynq in past and this patch just follow this pattern to separate cpu code from SoC code. Move arch/arm/cpu/armv8/zynqmp/* -> arch/arm/mach-zynqmp/* And also fix references to these files. Based on "ARM: zynq: move SoC sources to mach-zynq" (sha1: 0107f2403669f764ab726d0d404e35bb9447bbcc) Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-01-17 07:22:43 +00:00
* (This file is derived from arch/arm/mach-zynqmp/cpu.c)
armv8: K3: am654: Add custom MMU support Add MMU mappings for AM654 SoC. Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2018-08-27 10:27:13 +00:00
*
*/
#include <common.h>
#include <asm/system.h>
#include <asm/armv8/mmu.h>
armv8: K3: j721e: Add custom MMU support The A72 U-Boot code loads and boots a number of remote processors including the C71x DSP, both the C66_0 and C66_1 DSPs, and the various Main R5FSS Cores. Change the memory attributes for the DDR regions used by the remote processors so that the cores can see and execute the proper code. A separate table based on the current AM65x table is added for J721E SoCs, since the number of remote processors and their DDR usage will be different between the two SoC families. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2019-06-13 04:59:48 +00:00
#ifdef CONFIG_SOC_K3_AM6
armv8: K3: am654: Add custom MMU support Add MMU mappings for AM654 SoC. Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2018-08-27 10:27:13 +00:00
/* NR_DRAM_BANKS + 32bit IO + 64bit IO + terminator */
armv8: K3: am65x: Update DDR address regions in MMU table The A53 U-Boot code can load and boot the MCU domain R5F cores (either a single core in LockStep mode or 2 cores in Split mode) to achieve various early system functionalities. Change the memory attributes for the DDR regions used by the remote processors so that the cores can see and execute the proper code loaded by U-Boot. These regions are currently limited to 0xa0000000 to 0xa2100000 as per the DDR carveouts assigned for these R5F cores in the overall DDR memory map. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2019-09-04 10:31:49 +00:00
#define NR_MMU_REGIONS (CONFIG_NR_DRAM_BANKS + 5)
armv8: K3: am654: Add custom MMU support Add MMU mappings for AM654 SoC. Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2018-08-27 10:27:13 +00:00
/* ToDo: Add 64bit IO */
struct mm_region am654_mem_map[NR_MMU_REGIONS] = {
{
.virt = 0x0UL,
.phys = 0x0UL,
.size = 0x80000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, {
.virt = 0x80000000UL,
.phys = 0x80000000UL,
armv8: K3: am65x: Update DDR address regions in MMU table The A53 U-Boot code can load and boot the MCU domain R5F cores (either a single core in LockStep mode or 2 cores in Split mode) to achieve various early system functionalities. Change the memory attributes for the DDR regions used by the remote processors so that the cores can see and execute the proper code loaded by U-Boot. These regions are currently limited to 0xa0000000 to 0xa2100000 as per the DDR carveouts assigned for these R5F cores in the overall DDR memory map. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2019-09-04 10:31:49 +00:00
.size = 0x20000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_INNER_SHARE
}, {
.virt = 0xa0000000UL,
.phys = 0xa0000000UL,
.size = 0x02100000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL_NC) |
PTE_BLOCK_INNER_SHARE
}, {
.virt = 0xa2100000UL,
.phys = 0xa2100000UL,
.size = 0x5df00000UL,
armv8: K3: am654: Add custom MMU support Add MMU mappings for AM654 SoC. Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2018-08-27 10:27:13 +00:00
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_INNER_SHARE
}, {
.virt = 0x880000000UL,
.phys = 0x880000000UL,
.size = 0x80000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_INNER_SHARE
}, {
/* List terminator */
0,
}
};
struct mm_region *mem_map = am654_mem_map;
armv8: K3: j721e: Add custom MMU support The A72 U-Boot code loads and boots a number of remote processors including the C71x DSP, both the C66_0 and C66_1 DSPs, and the various Main R5FSS Cores. Change the memory attributes for the DDR regions used by the remote processors so that the cores can see and execute the proper code. A separate table based on the current AM65x table is added for J721E SoCs, since the number of remote processors and their DDR usage will be different between the two SoC families. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2019-06-13 04:59:48 +00:00
#endif /* CONFIG_SOC_K3_AM6 */
#ifdef CONFIG_SOC_K3_J721E
/* NR_DRAM_BANKS + 32bit IO + 64bit IO + terminator */
#define NR_MMU_REGIONS (CONFIG_NR_DRAM_BANKS + 5)
/* ToDo: Add 64bit IO */
struct mm_region j721e_mem_map[NR_MMU_REGIONS] = {
{
.virt = 0x0UL,
.phys = 0x0UL,
.size = 0x80000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, {
.virt = 0x80000000UL,
.phys = 0x80000000UL,
.size = 0x20000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_INNER_SHARE
}, {
.virt = 0xa0000000UL,
.phys = 0xa0000000UL,
armv8: K3: j721e: Updated ddr address regions in MMU table The A72 U-Boot code loads and boots a number of remote processors including the C71x DSP, both the C66_0 and C66_1 DSPs, and the various Main R5FSS Cores. In order to view the code loaded by the U-Boot by remote cores, U-Boot should configure the memory region with right memory attributes. Right now U-Boot carves out a memory region which is not sufficient for all the images to be loaded. So, increase this carve out region by 256MB. Signed-off-by: Kedar Chitnis <kedarc@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2019-09-04 10:31:50 +00:00
.size = 0x1bc00000UL,
armv8: K3: j721e: Add custom MMU support The A72 U-Boot code loads and boots a number of remote processors including the C71x DSP, both the C66_0 and C66_1 DSPs, and the various Main R5FSS Cores. Change the memory attributes for the DDR regions used by the remote processors so that the cores can see and execute the proper code. A separate table based on the current AM65x table is added for J721E SoCs, since the number of remote processors and their DDR usage will be different between the two SoC families. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2019-06-13 04:59:48 +00:00
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL_NC) |
PTE_BLOCK_NON_SHARE
}, {
armv8: K3: j721e: Updated ddr address regions in MMU table The A72 U-Boot code loads and boots a number of remote processors including the C71x DSP, both the C66_0 and C66_1 DSPs, and the various Main R5FSS Cores. In order to view the code loaded by the U-Boot by remote cores, U-Boot should configure the memory region with right memory attributes. Right now U-Boot carves out a memory region which is not sufficient for all the images to be loaded. So, increase this carve out region by 256MB. Signed-off-by: Kedar Chitnis <kedarc@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2019-09-04 10:31:50 +00:00
.virt = 0xbbc00000UL,
.phys = 0xbbc00000UL,
.size = 0x44400000UL,
armv8: K3: j721e: Add custom MMU support The A72 U-Boot code loads and boots a number of remote processors including the C71x DSP, both the C66_0 and C66_1 DSPs, and the various Main R5FSS Cores. Change the memory attributes for the DDR regions used by the remote processors so that the cores can see and execute the proper code. A separate table based on the current AM65x table is added for J721E SoCs, since the number of remote processors and their DDR usage will be different between the two SoC families. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2019-06-13 04:59:48 +00:00
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_INNER_SHARE
}, {
.virt = 0x880000000UL,
.phys = 0x880000000UL,
.size = 0x80000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_INNER_SHARE
}, {
.virt = 0x500000000UL,
.phys = 0x500000000UL,
.size = 0x400000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, {
/* List terminator */
0,
}
};
struct mm_region *mem_map = j721e_mem_map;
#endif /* CONFIG_SOC_K3_J721E */
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