2020-01-20 09:18:18 +00:00
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// SPDX-License-Identifier: GPL-2.0+
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#include "rk3399-u-boot.dtsi"
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2020-06-05 10:06:40 +00:00
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#ifdef CONFIG_TARGET_PUMA_RK3399_RAM_DDR3_1333
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#include "rk3399-sdram-ddr3-1333.dtsi"
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#endif
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#ifdef CONFIG_TARGET_PUMA_RK3399_RAM_DDR3_1600
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#include "rk3399-sdram-ddr3-1600.dtsi"
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#endif
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#ifdef CONFIG_TARGET_PUMA_RK3399_RAM_DDR3_1866
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#include "rk3399-sdram-ddr3-1866.dtsi"
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#endif
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2020-01-20 09:18:18 +00:00
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/ {
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2020-06-05 10:06:38 +00:00
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config {
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u-boot,spl-payload-offset = <0x40000>; /* @ 256KB */
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u-boot,mmc-env-offset = <0x4000>; /* @ 16KB */
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u-boot,efi-partition-entries-offset = <0x200000>; /* 2MB */
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u-boot,boot-led = "module_led";
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sysreset-gpio = <&gpio1 RK_PA6 GPIO_ACTIVE_HIGH>;
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};
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2020-01-20 09:18:18 +00:00
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2020-06-05 10:06:38 +00:00
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chosen {
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stdout-path = "serial0:115200n8";
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u-boot,spl-boot-order = \
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2020-04-28 10:00:17 +00:00
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"same-as-spl", &norflash, &sdhci, &sdmmc;
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2020-06-05 10:06:38 +00:00
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};
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2020-01-20 09:18:18 +00:00
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2020-06-05 10:06:38 +00:00
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aliases {
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spi0 = &spi1;
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spi1 = &spi5;
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};
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2020-01-20 09:18:18 +00:00
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2020-04-28 10:00:17 +00:00
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/*
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* The Qseven BIOS_DISABLE signal on the RK3399-Q7 keeps the on-module
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* eMMC and SPI flash powered-down initially (in fact it keeps the
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* reset signal asserted). Even though it is an enable signal, we
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* model this as a regulator.
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*/
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bios_enable: bios_enable {
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compatible = "regulator-fixed";
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u-boot,dm-pre-reloc;
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regulator-name = "bios_enable";
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enable-active-high;
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gpio = <&gpio3 RK_PD5 GPIO_ACTIVE_LOW>;
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regulator-always-on;
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regulator-boot-on;
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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};
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2020-04-28 10:00:14 +00:00
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};
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&gpio1 {
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u-boot,dm-pre-reloc;
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};
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&gpio3 {
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u-boot,dm-pre-reloc;
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};
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2020-04-28 10:00:17 +00:00
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&norflash {
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2020-04-28 10:00:14 +00:00
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u-boot,dm-pre-reloc;
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};
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