2013-09-22 01:56:02 +00:00
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#PBI commands
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#Initialize CPC1
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09010000 00200400
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09138000 00000000
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091380c0 00000100
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#Configure CPC1 as 512KB SRAM
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09010100 00000000
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09010104 fff80009
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09010f00 08000000
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09010000 80000000
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#Configure LAW for CPC1
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09000d00 00000000
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09000d04 fff80000
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09000d08 81000012
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#Configure alternate space
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09000010 00000000
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09000014 ff000000
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09000018 81000000
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#Configure SPI controller
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09110000 80000403
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09110020 2d170008
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09110024 00100008
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09110028 00100008
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0911002c 00100008
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2014-03-08 11:15:04 +00:00
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#slowing down the MDC clock to make it <= 2.5 MHZ
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094fc030 00008148
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094fd030 00008148
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2013-09-22 01:56:02 +00:00
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#Flush PBL data
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09138000 00000000
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091380c0 00000000
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