2018-05-06 21:58:06 +00:00
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/* SPDX-License-Identifier: GPL-2.0 */
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2016-03-16 13:44:36 +00:00
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/*
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* Copyright (c) 2016 Google, Inc
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*/
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#ifndef __asm_pch_common_h
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#define __asm_pch_common_h
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/* Common Intel SATA registers */
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#define SATA_SIRI 0xa0 /* SATA Indexed Register Index */
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#define SATA_SIRD 0xa4 /* SATA Indexed Register Data */
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#define SATA_SP 0xd0 /* Scratchpad */
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#define INTR_LN 0x3c
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#define IDE_TIM_PRI 0x40 /* IDE timings, primary */
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#define IDE_DECODE_ENABLE (1 << 15)
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#define IDE_SITRE (1 << 14)
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#define IDE_ISP_5_CLOCKS (0 << 12)
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#define IDE_ISP_4_CLOCKS (1 << 12)
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#define IDE_ISP_3_CLOCKS (2 << 12)
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#define IDE_RCT_4_CLOCKS (0 << 8)
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#define IDE_RCT_3_CLOCKS (1 << 8)
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#define IDE_RCT_2_CLOCKS (2 << 8)
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#define IDE_RCT_1_CLOCKS (3 << 8)
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#define IDE_DTE1 (1 << 7)
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#define IDE_PPE1 (1 << 6)
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#define IDE_IE1 (1 << 5)
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#define IDE_TIME1 (1 << 4)
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#define IDE_DTE0 (1 << 3)
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#define IDE_PPE0 (1 << 2)
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#define IDE_IE0 (1 << 1)
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#define IDE_TIME0 (1 << 0)
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#define IDE_TIM_SEC 0x42 /* IDE timings, secondary */
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#define SERIRQ_CNTL 0x64
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/**
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* pch_common_sir_read() - Read from a SATA indexed register
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*
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* @dev: SATA device
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* @idx: Register index to read
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* @return value read from register
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*/
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u32 pch_common_sir_read(struct udevice *dev, int idx);
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/**
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* pch_common_sir_write() - Write to a SATA indexed register
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*
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* @dev: SATA device
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* @idx: Register index to write
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* @value: Value to write
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*/
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void pch_common_sir_write(struct udevice *dev, int idx, u32 value);
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#endif
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