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u-boot/arch/riscv/lib/Makefile

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SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
2018-05-06 21:58:06 +00:00
# SPDX-License-Identifier: GPL-2.0+
riscv: nx25: lib: Add relative lib funcs to support RISC-V Add makefile, interrupts.c and boot.c,... functions to support RISC-V arch. Signed-off-by: Rick Chen <rick@andestech.com> Signed-off-by: Rick Chen <rickchen36@gmail.com> Signed-off-by: Greentime Hu <green.hu@gmail.com> Cc: Padmarao Begari <Padmarao.Begari@microsemi.com>
2017-12-26 05:55:49 +00:00
#
# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# Copyright (C) 2017 Andes Technology Corporation
# Rick Chen, Andes Technology Corporation <rick@andestech.com>
obj-$(CONFIG_CMD_BOOTM) += bootm.o
RISCV: image: Add booti support This patch adds booti support for RISC-V Linux kernel. The existing bootm method will also continue to work as it is. It depends on the following kernel patch which adds the header to the flat Image. Gzip compressed Image (Image.gz) support is not enabled with this patch. https://patchwork.kernel.org/patch/10925543/ Tested on HiFive Unleashed and QEMU. Signed-off-by: Atish Patra <atish.patra@wdc.com> Reviewed-by: Tom Rini <trini@konsulko.com> Tested-by: Karsten Merker <merker@debian.org> Reviewed-by: Marek Vasut <marek.vasut@gmail.com>
2019-05-07 00:49:39 +00:00
obj-$(CONFIG_CMD_BOOTI) += bootm.o image.o
riscv: nx25: lib: Add relative lib funcs to support RISC-V Add makefile, interrupts.c and boot.c,... functions to support RISC-V arch. Signed-off-by: Rick Chen <rick@andestech.com> Signed-off-by: Rick Chen <rickchen36@gmail.com> Signed-off-by: Greentime Hu <green.hu@gmail.com> Cc: Padmarao Begari <Padmarao.Begari@microsemi.com>
2017-12-26 05:55:49 +00:00
obj-$(CONFIG_CMD_GO) += boot.o
obj-y += cache.o
riscv: add run mode configuration for SPL U-Boot SPL can be run in a different privilege mode from U-Boot proper. Add new configuration entries for SPL to allow the run mode to be configured independently of U-Boot proper. Extend all uses of the CONFIG_RISCV_SMODE and CONFIG_RISCV_MMODE configuration symbols to also cover the SPL equivalents. Ensure that files compatible with only one privilege mode are not included in builds targeting an incompatible privilege mode. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Anup Patel <anup.patel@wdc.com>
2019-08-21 19:14:43 +00:00
ifeq ($(CONFIG_$(SPL_)RISCV_MMODE),y)
riscv: Add a SYSCON driver for SiFive's Core Local Interruptor This adds U-Boot syscon driver for SiFive's Core Local Interruptor (CLINT). The CLINT block holds memory-mapped control and status registers associated with software and timer interrupts. This driver implements the riscv_get_time() API as required by the generic RISC-V timer driver, as well as some other APIs that are needed for handling IPI. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup@brainfault.org>
2018-12-12 14:12:30 +00:00
obj-$(CONFIG_SIFIVE_CLINT) += sifive_clint.o
riscv: Add a SYSCON driver for Andestech's PLIC The Platform-Level Interrupt Controller (PLIC) block holds memory-mapped claim and pending registers associated with software interrupt. It is required for handling IPI. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
2019-04-02 07:56:39 +00:00
obj-$(CONFIG_ANDES_PLIC) += andes_plic.o
riscv: Add a SYSCON driver for Andestech's PLMT The platform-Level Machine Timer (PLMT) block holds memory-mapped mtime register associated with timer tick. This driver implements the riscv_get_time() which is required by the generic RISC-V timer driver. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
2019-04-02 07:56:40 +00:00
obj-$(CONFIG_ANDES_PLMT) += andes_plmt.o
riscv: add run mode configuration for SPL U-Boot SPL can be run in a different privilege mode from U-Boot proper. Add new configuration entries for SPL to allow the run mode to be configured independently of U-Boot proper. Extend all uses of the CONFIG_RISCV_SMODE and CONFIG_RISCV_MMODE configuration symbols to also cover the SPL equivalents. Ensure that files compatible with only one privilege mode are not included in builds targeting an incompatible privilege mode. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Anup Patel <anup.patel@wdc.com>
2019-08-21 19:14:43 +00:00
else
obj-$(CONFIG_RISCV_RDTIME) += rdtime.o
riscv: Add basic support for SBI v0.2 The SBI v0.2 introduces a base extension which is backward compatible with v0.1. Implement all helper functions and minimum required SBI calls from v0.2 for now. All other base extension function will be added later as per need. As v0.2 calling convention is backward compatible with v0.1, remove the v0.1 helper functions and just use v0.2 calling convention. Add a new Kconfig options CONFIG_SBI for the new SBI v0.2 codes, and let CONFIG_SBI_IPI depend on it. This commit is inspired from Linux kernel patch: https://patchwork.kernel.org/patch/11407363/ Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Pragnesh Patel <pragnesh.patel@sifive.com>
2020-03-10 02:35:28 +00:00
obj-$(CONFIG_SBI) += sbi.o
riscv: add run mode configuration for SPL U-Boot SPL can be run in a different privilege mode from U-Boot proper. Add new configuration entries for SPL to allow the run mode to be configured independently of U-Boot proper. Extend all uses of the CONFIG_RISCV_SMODE and CONFIG_RISCV_MMODE configuration symbols to also cover the SPL equivalents. Ensure that files compatible with only one privilege mode are not included in builds targeting an incompatible privilege mode. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Anup Patel <anup.patel@wdc.com>
2019-08-21 19:14:43 +00:00
obj-$(CONFIG_SBI_IPI) += sbi_ipi.o
endif
riscv: nx25: lib: Add relative lib funcs to support RISC-V Add makefile, interrupts.c and boot.c,... functions to support RISC-V arch. Signed-off-by: Rick Chen <rick@andestech.com> Signed-off-by: Rick Chen <rickchen36@gmail.com> Signed-off-by: Greentime Hu <green.hu@gmail.com> Cc: Padmarao Begari <Padmarao.Begari@microsemi.com>
2017-12-26 05:55:49 +00:00
obj-y += interrupts.o
riscv: Move do_reset() to a common place We don't have a reset method on any RISC-V board yet. Instead of adding the same 'unsupported' message for each CPU variant it might make more sense to add a generic do_reset function for all CPU variants to lib/, similar to the one for ARM (arch/arm/lib/reset.c). Suggested-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
2018-09-26 13:55:22 +00:00
obj-y += reset.o
riscv: Add setjmp/longjmp code To support efi_loader we need to have platform support for setjmp/longjmp. Add it here. Signed-off-by: Alexander Graf <agraf@suse.de>
2018-04-23 05:59:43 +00:00
obj-y += setjmp.o
riscv: add infrastructure for calling functions on other harts Harts on RISC-V boot independently, U-Boot is responsible for managing them. Functions are called on other harts with smp_call_function(), which sends inter-processor interrupts (IPIs) to all other available harts. Available harts are those marked as available in the device tree and present in the available_harts mask stored in global data. The available_harts mask is used to register all harts that have entered U-Boot. Functions are specified with their address and two function arguments (argument 2 and 3). The first function argument is always the hart ID of the hart calling the function. On the other harts, the IPI interrupt handler handle_ipi() must be called on software interrupts to handle the request and call the specified function. Functions are stored in the ipi_data data structure. Every hart has its own data structure in global data. While this is not required at the moment (all harts are expected to boot Linux), this does allow future expansion, where other harts may be used for monitoring or other tasks. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2019-03-17 18:28:32 +00:00
obj-$(CONFIG_SMP) += smp.o
riscv: add SPL support U-Boot SPL on the generic RISC-V CPU supports two boot flows, directly jumping to the image and via OpenSBI firmware. In the first case, both U-Boot SPL and proper must be compiled to run in the same privilege mode. Using OpenSBI firmware, U-Boot SPL must be compiled for machine mode and U-Boot proper for supervisor mode. To be able to use SPL, boards have to provide a supported SPL boot device. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Anup Patel <anup.patel@wdc.com>
2019-08-21 19:14:45 +00:00
obj-$(CONFIG_SPL_BUILD) += spl.o
riscv: Add EFI application infrastructure The hello world binary and a few selftests require to build EFI target binaries, not just the EFI host environment. This patch adds all required files to generate an EFI binary for RISC-V. Signed-off-by: Alexander Graf <agraf@suse.de>
2018-04-23 05:59:45 +00:00
# For building EFI apps
CFLAGS_$(EFI_CRT0) := $(CFLAGS_EFI)
CFLAGS_REMOVE_$(EFI_CRT0) := $(CFLAGS_NON_EFI)
CFLAGS_$(EFI_RELOC) := $(CFLAGS_EFI)
CFLAGS_REMOVE_$(EFI_RELOC) := $(CFLAGS_NON_EFI)
extra-$(CONFIG_CMD_BOOTEFI_HELLO_COMPILE) += $(EFI_CRT0) $(EFI_RELOC)
extra-$(CONFIG_CMD_BOOTEFI_SELFTEST) += $(EFI_CRT0) $(EFI_RELOC)
extra-$(CONFIG_EFI) += $(EFI_CRT0) $(EFI_RELOC)
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