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52 lines
1.5 KiB
C
52 lines
1.5 KiB
C
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2018 Renesas Electronics Corp.
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* Copyright (C) 2018 Cogent Embedded, Inc.
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*/
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#ifndef __DT_BINDINGS_CLOCK_R8A77980_CPG_MSSR_H__
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#define __DT_BINDINGS_CLOCK_R8A77980_CPG_MSSR_H__
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#include <dt-bindings/clock/renesas-cpg-mssr.h>
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/* r8a77980 CPG Core Clocks */
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#define R8A77980_CLK_Z2 0
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#define R8A77980_CLK_ZR 1
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#define R8A77980_CLK_ZTR 2
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#define R8A77980_CLK_ZTRD2 3
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#define R8A77980_CLK_ZT 4
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#define R8A77980_CLK_ZX 5
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#define R8A77980_CLK_S0D1 6
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#define R8A77980_CLK_S0D2 7
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#define R8A77980_CLK_S0D3 8
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#define R8A77980_CLK_S0D4 9
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#define R8A77980_CLK_S0D6 10
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#define R8A77980_CLK_S0D12 11
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#define R8A77980_CLK_S0D24 12
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#define R8A77980_CLK_S1D1 13
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#define R8A77980_CLK_S1D2 14
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#define R8A77980_CLK_S1D4 15
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#define R8A77980_CLK_S2D1 16
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#define R8A77980_CLK_S2D2 17
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#define R8A77980_CLK_S2D4 18
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#define R8A77980_CLK_S3D1 19
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#define R8A77980_CLK_S3D2 20
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#define R8A77980_CLK_S3D4 21
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#define R8A77980_CLK_LB 22
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#define R8A77980_CLK_CL 23
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#define R8A77980_CLK_ZB3 24
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#define R8A77980_CLK_ZB3D2 25
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#define R8A77980_CLK_ZB3D4 26
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#define R8A77980_CLK_SD0H 27
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#define R8A77980_CLK_SD0 28
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#define R8A77980_CLK_RPC 29
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#define R8A77980_CLK_RPCD2 30
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#define R8A77980_CLK_MSO 31
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#define R8A77980_CLK_CANFD 32
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#define R8A77980_CLK_CSI0 33
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#define R8A77980_CLK_CP 34
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#define R8A77980_CLK_CPEX 35
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#define R8A77980_CLK_R 36
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#define R8A77980_CLK_OSC 37
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#endif /* __DT_BINDINGS_CLOCK_R8A77980_CPG_MSSR_H__ */
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