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SPDX-License-Identifier: convert PIBS licensed files This commit adapts the files that were derived from PIBS (PowerPC Initialization and Boot Software) codeto using SPDX License Identifiers. So far, SPDX has not assigned an official License ID for the PIBS license yet, so this should be considered preliminary. Note that the following files contained incorrect license information: arch/powerpc/cpu/ppc4xx/4xx_uart.c arch/powerpc/cpu/ppc4xx/start.S arch/powerpc/include/asm/ppc440.h These files included, in addition to the GPL-2.0 / ibm-pibs dual license as inherited from PIBS, a GPL-2.0+ license header which was obviously incorrect. This has been removed. Signed-off-by: Wolfgang Denk <wd@denx.de> Cc: Stefan Roese <sr@denx.de> Signed-off-by: Wolfgang Denk <wd@denx.de> Conflicts: Licenses/README Acked-by: Stefan Roese <sr@denx.de>
2013-07-28 20:12:45 +00:00
/*
SPDX: fix IBM-pibs license identifier The SPDX License List version 1.19 now contains an official entry for the IBM-pibs license. However, instead of our suggestion "ibm-pibs", the SPDX License List uses "IBM-pibs", with the following rationale: "The reason being that all other SPDX License List short identifiers tend towards using capital letters unless spelling a word. I'd prefer to be consistent to this end". Change the license IDs to use the official name. Signed-off-by: Wolfgang Denk <wd@denx.de>
2013-09-17 09:24:06 +00:00
* SPDX-License-Identifier: GPL-2.0 IBM-pibs
SPDX-License-Identifier: convert PIBS licensed files This commit adapts the files that were derived from PIBS (PowerPC Initialization and Boot Software) codeto using SPDX License Identifiers. So far, SPDX has not assigned an official License ID for the PIBS license yet, so this should be considered preliminary. Note that the following files contained incorrect license information: arch/powerpc/cpu/ppc4xx/4xx_uart.c arch/powerpc/cpu/ppc4xx/start.S arch/powerpc/include/asm/ppc440.h These files included, in addition to the GPL-2.0 / ibm-pibs dual license as inherited from PIBS, a GPL-2.0+ license header which was obviously incorrect. This has been removed. Signed-off-by: Wolfgang Denk <wd@denx.de> Cc: Stefan Roese <sr@denx.de> Signed-off-by: Wolfgang Denk <wd@denx.de> Conflicts: Licenses/README Acked-by: Stefan Roese <sr@denx.de>
2013-07-28 20:12:45 +00:00
*/
Initial revision
2002-08-06 20:46:37 +00:00
#ifndef __PPC4XX_H__
#define __PPC4XX_H__
ppc4xx: Consolidate PPC4xx SDRAM/DDR/DDR2 defines, part1 This patch removes all SDRAM related defines from the PPC4xx headers ppc405.h and ppc440.h. This is needed since now some 405 PPC's use the same SDRAM controller as 440 systems do (like 405EX and 440SP). It also introduces new defines for the equipped SDRAM controller based on which PPC variant is used. There new defines are: used on 405GR/CR/EP and some Xilinx Virtex boards. used on 440GP/GX/EP/GR. used on 440EPx/GRx. used on 405EX/r/440SP/SPe/460EX/GT. Signed-off-by: Stefan Roese <sr@denx.de>
2008-06-02 12:57:41 +00:00
/*
ppc4xx: Big header cleanup, mostly PPC440 related This patch starts a bit PPC4xx header cleanup. First patch mostly touches PPC440 files. A later patch will touch the PPC405 files as well. This cleanup is done by creating header files for all SoC versions and moving the SoC specific defines into these special headers. This way the common header ppc405.h and ppc440.h can be cleaned up finally. Signed-off-by: Stefan Roese <sr@denx.de>
2010-09-11 07:31:43 +00:00
* Include SoC specific headers
ppc4xx: Consolidate PPC4xx SDRAM/DDR/DDR2 defines, part1 This patch removes all SDRAM related defines from the PPC4xx headers ppc405.h and ppc440.h. This is needed since now some 405 PPC's use the same SDRAM controller as 440 systems do (like 405EX and 440SP). It also introduces new defines for the equipped SDRAM controller based on which PPC variant is used. There new defines are: used on 405GR/CR/EP and some Xilinx Virtex boards. used on 440GP/GX/EP/GR. used on 440EPx/GRx. used on 405EX/r/440SP/SPe/460EX/GT. Signed-off-by: Stefan Roese <sr@denx.de>
2008-06-02 12:57:41 +00:00
*/
ppc4xx: Big header cleanup, mostly PPC440 related This patch starts a bit PPC4xx header cleanup. First patch mostly touches PPC440 files. A later patch will touch the PPC405 files as well. This cleanup is done by creating header files for all SoC versions and moving the SoC specific defines into these special headers. This way the common header ppc405.h and ppc440.h can be cleaned up finally. Signed-off-by: Stefan Roese <sr@denx.de>
2010-09-11 07:31:43 +00:00
#if defined(CONFIG_405EP)
#include <asm/ppc405ep.h>
#endif
#if defined(CONFIG_405EX)
#include <asm/ppc405ex.h>
#endif
#if defined(CONFIG_405EZ)
#include <asm/ppc405ez.h>
#endif
#if defined(CONFIG_405GP)
#include <asm/ppc405gp.h>
ppc4xx: Consolidate PPC4xx SDRAM/DDR/DDR2 defines, part1 This patch removes all SDRAM related defines from the PPC4xx headers ppc405.h and ppc440.h. This is needed since now some 405 PPC's use the same SDRAM controller as 440 systems do (like 405EX and 440SP). It also introduces new defines for the equipped SDRAM controller based on which PPC variant is used. There new defines are: used on 405GR/CR/EP and some Xilinx Virtex boards. used on 440GP/GX/EP/GR. used on 440EPx/GRx. used on 405EX/r/440SP/SPe/460EX/GT. Signed-off-by: Stefan Roese <sr@denx.de>
2008-06-02 12:57:41 +00:00
#endif
ppc4xx: Big header cleanup, mostly PPC440 related This patch starts a bit PPC4xx header cleanup. First patch mostly touches PPC440 files. A later patch will touch the PPC405 files as well. This cleanup is done by creating header files for all SoC versions and moving the SoC specific defines into these special headers. This way the common header ppc405.h and ppc440.h can be cleaned up finally. Signed-off-by: Stefan Roese <sr@denx.de>
2010-09-11 07:31:43 +00:00
#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
#include <asm/ppc440ep_gr.h>
ppc4xx: Consolidate PPC4xx SDRAM/DDR/DDR2 defines, part1 This patch removes all SDRAM related defines from the PPC4xx headers ppc405.h and ppc440.h. This is needed since now some 405 PPC's use the same SDRAM controller as 440 systems do (like 405EX and 440SP). It also introduces new defines for the equipped SDRAM controller based on which PPC variant is used. There new defines are: used on 405GR/CR/EP and some Xilinx Virtex boards. used on 440GP/GX/EP/GR. used on 440EPx/GRx. used on 405EX/r/440SP/SPe/460EX/GT. Signed-off-by: Stefan Roese <sr@denx.de>
2008-06-02 12:57:41 +00:00
#endif
#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
ppc4xx: Big header cleanup, mostly PPC440 related This patch starts a bit PPC4xx header cleanup. First patch mostly touches PPC440 files. A later patch will touch the PPC405 files as well. This cleanup is done by creating header files for all SoC versions and moving the SoC specific defines into these special headers. This way the common header ppc405.h and ppc440.h can be cleaned up finally. Signed-off-by: Stefan Roese <sr@denx.de>
2010-09-11 07:31:43 +00:00
#include <asm/ppc440epx_grx.h>
#endif
#if defined(CONFIG_440GP)
#include <asm/ppc440gp.h>
#endif
#if defined(CONFIG_440GX)
#include <asm/ppc440gx.h>
ppc4xx: Consolidate PPC4xx SDRAM/DDR/DDR2 defines, part1 This patch removes all SDRAM related defines from the PPC4xx headers ppc405.h and ppc440.h. This is needed since now some 405 PPC's use the same SDRAM controller as 440 systems do (like 405EX and 440SP). It also introduces new defines for the equipped SDRAM controller based on which PPC variant is used. There new defines are: used on 405GR/CR/EP and some Xilinx Virtex boards. used on 440GP/GX/EP/GR. used on 440EPx/GRx. used on 405EX/r/440SP/SPe/460EX/GT. Signed-off-by: Stefan Roese <sr@denx.de>
2008-06-02 12:57:41 +00:00
#endif
ppc4xx: Big header cleanup, mostly PPC440 related This patch starts a bit PPC4xx header cleanup. First patch mostly touches PPC440 files. A later patch will touch the PPC405 files as well. This cleanup is done by creating header files for all SoC versions and moving the SoC specific defines into these special headers. This way the common header ppc405.h and ppc440.h can be cleaned up finally. Signed-off-by: Stefan Roese <sr@denx.de>
2010-09-11 07:31:43 +00:00
#if defined(CONFIG_440SP)
#include <asm/ppc440sp.h>
ppc4xx: Consolidate PPC4xx SDRAM/DDR/DDR2 defines, part1 This patch removes all SDRAM related defines from the PPC4xx headers ppc405.h and ppc440.h. This is needed since now some 405 PPC's use the same SDRAM controller as 440 systems do (like 405EX and 440SP). It also introduces new defines for the equipped SDRAM controller based on which PPC variant is used. There new defines are: used on 405GR/CR/EP and some Xilinx Virtex boards. used on 440GP/GX/EP/GR. used on 440EPx/GRx. used on 405EX/r/440SP/SPe/460EX/GT. Signed-off-by: Stefan Roese <sr@denx.de>
2008-06-02 12:57:41 +00:00
#endif
ppc4xx: Big header cleanup, mostly PPC440 related This patch starts a bit PPC4xx header cleanup. First patch mostly touches PPC440 files. A later patch will touch the PPC405 files as well. This cleanup is done by creating header files for all SoC versions and moving the SoC specific defines into these special headers. This way the common header ppc405.h and ppc440.h can be cleaned up finally. Signed-off-by: Stefan Roese <sr@denx.de>
2010-09-11 07:31:43 +00:00
#if defined(CONFIG_440SPE)
#include <asm/ppc440spe.h>
ppc4xx: Move definition for PPC4xx NAND FLASH controller to header This patch moves the definition for the PPC4xx NAND FLASH controller (NDFC) CONFIG_NAND_NDFC into include/ppc4xx.h. This is needed for the upcoming fix for the ECC byte ordering of the NDFC driver. Signed-off-by: Stefan Roese <sr@denx.de> Acked-by: Scott Wood <scottwood@freescale.com>
2009-05-20 08:58:01 +00:00
#endif
ppc4xx: Big header cleanup, mostly PPC440 related This patch starts a bit PPC4xx header cleanup. First patch mostly touches PPC440 files. A later patch will touch the PPC405 files as well. This cleanup is done by creating header files for all SoC versions and moving the SoC specific defines into these special headers. This way the common header ppc405.h and ppc440.h can be cleaned up finally. Signed-off-by: Stefan Roese <sr@denx.de>
2010-09-11 07:31:43 +00:00
#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
#include <asm/ppc460ex_gt.h>
#endif
#if defined(CONFIG_460SX)
#include <asm/ppc460sx.h>
#endif
APM821xx: Add CPU support APM821XX is a new line of SoCs which are derivatives of PPC44X family of processors. This patch adds support of CPU, cache, tlb, 32k ocm, bootstraps, PLB and AHB bus. Signed-off-by: Tirumala R Marri <tmarri@apm.com> Signed-off-by: Stefan Roese <sr@denx.de>
2010-09-28 21:15:14 +00:00
#if defined(CONFIG_APM821XX)
#include <asm/apm821xx.h>
#endif
ppc4xx: Big header cleanup, mostly PPC440 related This patch starts a bit PPC4xx header cleanup. First patch mostly touches PPC440 files. A later patch will touch the PPC405 files as well. This cleanup is done by creating header files for all SoC versions and moving the SoC specific defines into these special headers. This way the common header ppc405.h and ppc440.h can be cleaned up finally. Signed-off-by: Stefan Roese <sr@denx.de>
2010-09-11 07:31:43 +00:00
/*
* Common registers for all SoC's
*/
/* DCR registers */
#define PLB3A0_ACR 0x0077
#define PLB4A0_ACR 0x0081
#define PLB4A1_ACR 0x0089
ppc4xx: Big header cleanup part 2, mostly PPC405 related This cleanup is done by creating header files for all SoC versions and moving the SoC specific defines into these special headers. This way the common header ppc405.h and ppc440.h can be cleaned up finally. As a part from this cleanup, the GPIO definitions for PPC405EP are corrected. The high and low parts of the registers (for example CONFIG_SYS_GPIO0_OSRL vs. CONFIG_SYS_GPIO0_OSRH) have been defined in the wrong order. This patch now fixes this issue by switching these xxxH and xxxL values. This brings the GPIO 405EP port in sync with all other PPC4xx ports. Signed-off-by: Stefan Roese <sr@denx.de>
2010-09-12 04:21:37 +00:00
/* CPR register declarations */
ppc4xx: Big header cleanup, mostly PPC440 related This patch starts a bit PPC4xx header cleanup. First patch mostly touches PPC440 files. A later patch will touch the PPC405 files as well. This cleanup is done by creating header files for all SoC versions and moving the SoC specific defines into these special headers. This way the common header ppc405.h and ppc440.h can be cleaned up finally. Signed-off-by: Stefan Roese <sr@denx.de>
2010-09-11 07:31:43 +00:00
#define PLB4Ax_ACR_PPM_MASK 0xf0000000
#define PLB4Ax_ACR_PPM_FIXED 0x00000000
#define PLB4Ax_ACR_PPM_FAIR 0xd0000000
#define PLB4Ax_ACR_HBU_MASK 0x08000000
#define PLB4Ax_ACR_HBU_DISABLED 0x00000000
#define PLB4Ax_ACR_HBU_ENABLED 0x08000000
#define PLB4Ax_ACR_RDP_MASK 0x06000000
#define PLB4Ax_ACR_RDP_DISABLED 0x00000000
#define PLB4Ax_ACR_RDP_2DEEP 0x02000000
#define PLB4Ax_ACR_RDP_3DEEP 0x04000000
#define PLB4Ax_ACR_RDP_4DEEP 0x06000000
#define PLB4Ax_ACR_WRP_MASK 0x01000000
#define PLB4Ax_ACR_WRP_DISABLED 0x00000000
#define PLB4Ax_ACR_WRP_2DEEP 0x01000000
ppc4xx: Big header cleanup part 2, mostly PPC405 related This cleanup is done by creating header files for all SoC versions and moving the SoC specific defines into these special headers. This way the common header ppc405.h and ppc440.h can be cleaned up finally. As a part from this cleanup, the GPIO definitions for PPC405EP are corrected. The high and low parts of the registers (for example CONFIG_SYS_GPIO0_OSRL vs. CONFIG_SYS_GPIO0_OSRH) have been defined in the wrong order. This patch now fixes this issue by switching these xxxH and xxxL values. This brings the GPIO 405EP port in sync with all other PPC4xx ports. Signed-off-by: Stefan Roese <sr@denx.de>
2010-09-12 04:21:37 +00:00
/*
* External Bus Controller
*/
/* Values for EBC0_CFGADDR register - indirect addressing of these regs */
#define PB0CR 0x00 /* periph bank 0 config reg */
#define PB1CR 0x01 /* periph bank 1 config reg */
#define PB2CR 0x02 /* periph bank 2 config reg */
#define PB3CR 0x03 /* periph bank 3 config reg */
#define PB4CR 0x04 /* periph bank 4 config reg */
#define PB5CR 0x05 /* periph bank 5 config reg */
#define PB6CR 0x06 /* periph bank 6 config reg */
#define PB7CR 0x07 /* periph bank 7 config reg */
#define PB0AP 0x10 /* periph bank 0 access parameters */
#define PB1AP 0x11 /* periph bank 1 access parameters */
#define PB2AP 0x12 /* periph bank 2 access parameters */
#define PB3AP 0x13 /* periph bank 3 access parameters */
#define PB4AP 0x14 /* periph bank 4 access parameters */
#define PB5AP 0x15 /* periph bank 5 access parameters */
#define PB6AP 0x16 /* periph bank 6 access parameters */
#define PB7AP 0x17 /* periph bank 7 access parameters */
#define PBEAR 0x20 /* periph bus error addr reg */
#define PBESR0 0x21 /* periph bus error status reg 0 */
#define PBESR1 0x22 /* periph bus error status reg 1 */
#define EBC0_CFG 0x23 /* external bus configuration reg */
/*
* GPIO macro register defines
*/
/* todo: merge with gpio.h header */
#define GPIO_BASE GPIO0_BASE
#define GPIO0_OR (GPIO0_BASE + 0x0)
#define GPIO0_TCR (GPIO0_BASE + 0x4)
#define GPIO0_OSRL (GPIO0_BASE + 0x8)
#define GPIO0_OSRH (GPIO0_BASE + 0xC)
#define GPIO0_TSRL (GPIO0_BASE + 0x10)
#define GPIO0_TSRH (GPIO0_BASE + 0x14)
#define GPIO0_ODR (GPIO0_BASE + 0x18)
#define GPIO0_IR (GPIO0_BASE + 0x1C)
#define GPIO0_RR1 (GPIO0_BASE + 0x20)
#define GPIO0_RR2 (GPIO0_BASE + 0x24)
#define GPIO0_RR3 (GPIO0_BASE + 0x28)
#define GPIO0_ISR1L (GPIO0_BASE + 0x30)
#define GPIO0_ISR1H (GPIO0_BASE + 0x34)
#define GPIO0_ISR2L (GPIO0_BASE + 0x38)
#define GPIO0_ISR2H (GPIO0_BASE + 0x3C)
#define GPIO0_ISR3L (GPIO0_BASE + 0x40)
#define GPIO0_ISR3H (GPIO0_BASE + 0x44)
#define GPIO1_OR (GPIO1_BASE + 0x0)
#define GPIO1_TCR (GPIO1_BASE + 0x4)
#define GPIO1_OSRL (GPIO1_BASE + 0x8)
#define GPIO1_OSRH (GPIO1_BASE + 0xC)
#define GPIO1_TSRL (GPIO1_BASE + 0x10)
#define GPIO1_TSRH (GPIO1_BASE + 0x14)
#define GPIO1_ODR (GPIO1_BASE + 0x18)
#define GPIO1_IR (GPIO1_BASE + 0x1C)
#define GPIO1_RR1 (GPIO1_BASE + 0x20)
#define GPIO1_RR2 (GPIO1_BASE + 0x24)
#define GPIO1_RR3 (GPIO1_BASE + 0x28)
#define GPIO1_ISR1L (GPIO1_BASE + 0x30)
#define GPIO1_ISR1H (GPIO1_BASE + 0x34)
#define GPIO1_ISR2L (GPIO1_BASE + 0x38)
#define GPIO1_ISR2H (GPIO1_BASE + 0x3C)
#define GPIO1_ISR3L (GPIO1_BASE + 0x40)
#define GPIO1_ISR3H (GPIO1_BASE + 0x44)
ppc4xx: Big header cleanup, mostly PPC440 related This patch starts a bit PPC4xx header cleanup. First patch mostly touches PPC440 files. A later patch will touch the PPC405 files as well. This cleanup is done by creating header files for all SoC versions and moving the SoC specific defines into these special headers. This way the common header ppc405.h and ppc440.h can be cleaned up finally. Signed-off-by: Stefan Roese <sr@denx.de>
2010-09-11 07:31:43 +00:00
/* General Purpose Timer (GPT) Register Offsets */
#define GPT0_TBC 0x00000000
#define GPT0_IM 0x00000018
#define GPT0_ISS 0x0000001C
#define GPT0_ISC 0x00000020
#define GPT0_IE 0x00000024
#define GPT0_COMP0 0x00000080
#define GPT0_COMP1 0x00000084
#define GPT0_COMP2 0x00000088
#define GPT0_COMP3 0x0000008C
#define GPT0_COMP4 0x00000090
#define GPT0_COMP5 0x00000094
#define GPT0_COMP6 0x00000098
#define GPT0_MASK0 0x000000C0
#define GPT0_MASK1 0x000000C4
#define GPT0_MASK2 0x000000C8
#define GPT0_MASK3 0x000000CC
#define GPT0_MASK4 0x000000D0
#define GPT0_MASK5 0x000000D4
#define GPT0_MASK6 0x000000D8
#define GPT0_DCT0 0x00000110
#define GPT0_DCIS 0x0000011C
ppc4xx: Optimize PLB4 Arbiter and Memory Queue settings for PPC440SP/SPe, PPC405EX and PPC460EX/GT/SX - Read pipeline depth set to 4 for PPC440SP/SPE, PPC405EX, PPC460EX/GT/SX processors - Moved PLB4 Arbiter register definitions to ppc4xx.h since it is shared across processors (405 and 440/460) - Optimize Memory Queue settings for PPC440SP/SPE and PPC460EX/GT/SX processors - Add register bit definitions for Memory Queue Configuration registers Signed-off-by: Prodyut Hazarika <phazarika@amcc.com> Signed-off-by: Stefan Roese <sr@denx.de>
2008-08-20 16:38:51 +00:00
Initial revision
2002-08-06 20:46:37 +00:00
#if defined(CONFIG_440)
ppc4xx: Move ppc4xx headers to powerpc include directory This patch moves some ppc4xx related headers from the common include directory (include/) to the powerpc specific one (arch/powerpc/include/asm/). This way to common include directory is not so cluttered with files. Signed-off-by: Stefan Roese <sr@denx.de>
2010-09-09 17:18:00 +00:00
#include <asm/ppc440.h>
Initial revision
2002-08-06 20:46:37 +00:00
#else
ppc4xx: Move ppc4xx headers to powerpc include directory This patch moves some ppc4xx related headers from the common include directory (include/) to the powerpc specific one (arch/powerpc/include/asm/). This way to common include directory is not so cluttered with files. Signed-off-by: Stefan Roese <sr@denx.de>
2010-09-09 17:18:00 +00:00
#include <asm/ppc405.h>
Initial revision
2002-08-06 20:46:37 +00:00
#endif
ppc4xx: Consolidate PPC4xx SDRAM/DDR/DDR2 defines, part1 This patch removes all SDRAM related defines from the PPC4xx headers ppc405.h and ppc440.h. This is needed since now some 405 PPC's use the same SDRAM controller as 440 systems do (like 405EX and 440SP). It also introduces new defines for the equipped SDRAM controller based on which PPC variant is used. There new defines are: used on 405GR/CR/EP and some Xilinx Virtex boards. used on 440GP/GX/EP/GR. used on 440EPx/GRx. used on 405EX/r/440SP/SPe/460EX/GT. Signed-off-by: Stefan Roese <sr@denx.de>
2008-06-02 12:57:41 +00:00
#include <asm/ppc4xx-sdram.h>
ppc4xx: Consolidate PPC4xx EBC defines This patch removes all EBC related defines from the PPC4xx headers ppc405.h and ppc440.h and introduces a new header include/asm-ppc/ppc4xx-ebc.h with all those defines. Signed-off-by: Stefan Roese <sr@denx.de>
2008-06-24 15:18:50 +00:00
#include <asm/ppc4xx-ebc.h>
ppc4xx: CPU PPC440x5 on Virtex5 FX -This patchs gives support for the embbedded ppc440 on the Virtex5 FPGAs -interrupts.c divided in uic.c and interrupts.c -xilinx_irq.c for xilinx interrupt controller -Include modifications propossed by Stefan Roese Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda@uam.es> Acked-by: Stefan Roese <sr@denx.de>
2008-07-17 09:44:12 +00:00
#if !defined(CONFIG_XILINX_440)
ppc4xx: Consolidate PPC4xx UIC defines This patch is the first step to consolidate the UIC related defines in the 4xx headers. Move header from asm-ppc/ppc4xx-intvec.h to asm-ppc/ppc4xx-uic.h as it will hold all UIC related defines in the next steps. Signed-off-by: Stefan Roese <sr@denx.de>
2008-06-25 08:59:22 +00:00
#include <asm/ppc4xx-uic.h>
ppc4xx: CPU PPC440x5 on Virtex5 FX -This patchs gives support for the embbedded ppc440 on the Virtex5 FPGAs -interrupts.c divided in uic.c and interrupts.c -xilinx_irq.c for xilinx interrupt controller -Include modifications propossed by Stefan Roese Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda@uam.es> Acked-by: Stefan Roese <sr@denx.de>
2008-07-17 09:44:12 +00:00
#endif
ppc4xx: Consolidate PPC4xx SDRAM/DDR/DDR2 defines, part1 This patch removes all SDRAM related defines from the PPC4xx headers ppc405.h and ppc440.h. This is needed since now some 405 PPC's use the same SDRAM controller as 440 systems do (like 405EX and 440SP). It also introduces new defines for the equipped SDRAM controller based on which PPC variant is used. There new defines are: used on 405GR/CR/EP and some Xilinx Virtex boards. used on 440GP/GX/EP/GR. used on 440EPx/GRx. used on 405EX/r/440SP/SPe/460EX/GT. Signed-off-by: Stefan Roese <sr@denx.de>
2008-06-02 12:57:41 +00:00
ppc4xx: Enable Primordial Stack for 40x and Unify ECC Handling This patch (Part 1 of 2): * Rolls up a suite of changes to enable correct primordial stack and global data handling when the data cache is used for such a purpose for PPC40x-variants (i.e. CFG_INIT_DCACHE_CS). * Related to the first, unifies DDR2 SDRAM and ECC initialization by eliminating redundant ECC initialization implementations and moving redundant SDRAM initialization out of board code into shared 4xx code. * Enables MCSR visibility on the 405EX(r). * Enables the use of the data cache for initial RAM on both AMCC's Kilauea and Makalu and removes a redundant CFG_POST_MEMORY flag from each board's CONFIG_POST value. - Removed, per Stefan Roese's request, defunct memory.c file for Makalu and rolled sdram_init from it into makalu.c. With respect to the 4xx DDR initialization and ECC unification, there is certainly more work that can and should be done (file renaming, etc.). However, that can be handled at a later date on a second or third pass. As it stands, this patch moves things forward in an incremental yet positive way for those platforms that utilize this code and the features associated with it. Signed-off-by: Grant Erickson <gerickson@nuovations.com> Signed-off-by: Stefan Roese <sr@denx.de>
2008-05-22 21:44:14 +00:00
/*
* Macro for generating register field mnemonics
*/
#define PPC_REG_BITS 32
#define PPC_REG_VAL(bit, value) ((value) << ((PPC_REG_BITS - 1) - (bit)))
/*
* Elide casts when assembling register mnemonics
*/
#ifndef __ASSEMBLY__
#define static_cast(type, val) (type)(val)
#else
#define static_cast(type, val) (val)
#endif
ppc4xx: Consolidate some of the 405 and 440 macros/structs into 4xx This patch moves some common 4xx macros and the PPC405_SYS_INFO/ PPC440_SYS_INFO structure into the common ppc4xx.h header. Lot's of other macros are good candidates to be consolidated this way in the future. Signed-off-by: Stefan Roese <sr@denx.de>
2007-10-21 06:12:41 +00:00
/*
* Common stuff for 4xx (405 and 440)
*/
ppc4xx: respect 80-chars per line in ppc*.h files After running checkstyle.pl on the three previous patches I noted that in the *.h files there were a lot of long lines. This patch solves this problem. Signed-off-by: Niklaus Giger <niklaus.giger@member.fsf.org> Signed-off-by: Stefan Roese <sr@denx.de>
2009-10-04 18:04:22 +00:00
#define EXC_OFF_SYS_RESET 0x0100 /* System reset */
ppc4xx: Consolidate some of the 405 and 440 macros/structs into 4xx This patch moves some common 4xx macros and the PPC405_SYS_INFO/ PPC440_SYS_INFO structure into the common ppc4xx.h header. Lot's of other macros are good candidates to be consolidated this way in the future. Signed-off-by: Stefan Roese <sr@denx.de>
2007-10-21 06:12:41 +00:00
#define _START_OFFSET (EXC_OFF_SYS_RESET + 0x2000)
#define RESET_VECTOR 0xfffffffc
ppc4xx: respect 80-chars per line in ppc*.h files After running checkstyle.pl on the three previous patches I noted that in the *.h files there were a lot of long lines. This patch solves this problem. Signed-off-by: Niklaus Giger <niklaus.giger@member.fsf.org> Signed-off-by: Stefan Roese <sr@denx.de>
2009-10-04 18:04:22 +00:00
#define CACHELINE_MASK (CONFIG_SYS_CACHELINE_SIZE - 1) /* Address mask for
cache line aligned data. */
ppc4xx: Consolidate some of the 405 and 440 macros/structs into 4xx This patch moves some common 4xx macros and the PPC405_SYS_INFO/ PPC440_SYS_INFO structure into the common ppc4xx.h header. Lot's of other macros are good candidates to be consolidated this way in the future. Signed-off-by: Stefan Roese <sr@denx.de>
2007-10-21 06:12:41 +00:00
#define CPR0_DCR_BASE 0x0C
ppc4xx: Big cleanup of PPC4xx defines This patch cleans up multiple issues of the 4xx register (mostly DCR, SDR, CPR, etc) definitions: - Change lower case defines to upper case (plb4_acr -> PLB4_ACR) - Change the defines to better match the names from the user's manuals (e.g. cprpllc -> CPR0_PLLC) - Removal of some unused defines Please test this patch intensive on your PPC4xx platform. Even though I tried not to break anything and tested successfully on multiple 4xx AMCC platforms, testing on custom platforms is recommended. Signed-off-by: Stefan Roese <sr@denx.de>
2009-09-09 14:25:29 +00:00
#define CPR0_CFGADDR (CPR0_DCR_BASE + 0x0)
#define CPR0_CFGDATA (CPR0_DCR_BASE + 0x1)
ppc4xx: Consolidate some of the 405 and 440 macros/structs into 4xx This patch moves some common 4xx macros and the PPC405_SYS_INFO/ PPC440_SYS_INFO structure into the common ppc4xx.h header. Lot's of other macros are good candidates to be consolidated this way in the future. Signed-off-by: Stefan Roese <sr@denx.de>
2007-10-21 06:12:41 +00:00
#define SDR_DCR_BASE 0x0E
ppc4xx: Big cleanup of PPC4xx defines This patch cleans up multiple issues of the 4xx register (mostly DCR, SDR, CPR, etc) definitions: - Change lower case defines to upper case (plb4_acr -> PLB4_ACR) - Change the defines to better match the names from the user's manuals (e.g. cprpllc -> CPR0_PLLC) - Removal of some unused defines Please test this patch intensive on your PPC4xx platform. Even though I tried not to break anything and tested successfully on multiple 4xx AMCC platforms, testing on custom platforms is recommended. Signed-off-by: Stefan Roese <sr@denx.de>
2009-09-09 14:25:29 +00:00
#define SDR0_CFGADDR (SDR_DCR_BASE + 0x0)
#define SDR0_CFGDATA (SDR_DCR_BASE + 0x1)
ppc4xx: Consolidate some of the 405 and 440 macros/structs into 4xx This patch moves some common 4xx macros and the PPC405_SYS_INFO/ PPC440_SYS_INFO structure into the common ppc4xx.h header. Lot's of other macros are good candidates to be consolidated this way in the future. Signed-off-by: Stefan Roese <sr@denx.de>
2007-10-21 06:12:41 +00:00
#define SDRAM_DCR_BASE 0x10
ppc4xx: Big cleanup of PPC4xx defines This patch cleans up multiple issues of the 4xx register (mostly DCR, SDR, CPR, etc) definitions: - Change lower case defines to upper case (plb4_acr -> PLB4_ACR) - Change the defines to better match the names from the user's manuals (e.g. cprpllc -> CPR0_PLLC) - Removal of some unused defines Please test this patch intensive on your PPC4xx platform. Even though I tried not to break anything and tested successfully on multiple 4xx AMCC platforms, testing on custom platforms is recommended. Signed-off-by: Stefan Roese <sr@denx.de>
2009-09-09 14:25:29 +00:00
#define SDRAM0_CFGADDR (SDRAM_DCR_BASE + 0x0)
#define SDRAM0_CFGDATA (SDRAM_DCR_BASE + 0x1)
ppc4xx: Consolidate some of the 405 and 440 macros/structs into 4xx This patch moves some common 4xx macros and the PPC405_SYS_INFO/ PPC440_SYS_INFO structure into the common ppc4xx.h header. Lot's of other macros are good candidates to be consolidated this way in the future. Signed-off-by: Stefan Roese <sr@denx.de>
2007-10-21 06:12:41 +00:00
#define EBC_DCR_BASE 0x12
ppc4xx: Big cleanup of PPC4xx defines This patch cleans up multiple issues of the 4xx register (mostly DCR, SDR, CPR, etc) definitions: - Change lower case defines to upper case (plb4_acr -> PLB4_ACR) - Change the defines to better match the names from the user's manuals (e.g. cprpllc -> CPR0_PLLC) - Removal of some unused defines Please test this patch intensive on your PPC4xx platform. Even though I tried not to break anything and tested successfully on multiple 4xx AMCC platforms, testing on custom platforms is recommended. Signed-off-by: Stefan Roese <sr@denx.de>
2009-09-09 14:25:29 +00:00
#define EBC0_CFGADDR (EBC_DCR_BASE + 0x0)
#define EBC0_CFGDATA (EBC_DCR_BASE + 0x1)
ppc4xx: Consolidate some of the 405 and 440 macros/structs into 4xx This patch moves some common 4xx macros and the PPC405_SYS_INFO/ PPC440_SYS_INFO structure into the common ppc4xx.h header. Lot's of other macros are good candidates to be consolidated this way in the future. Signed-off-by: Stefan Roese <sr@denx.de>
2007-10-21 06:12:41 +00:00
/*
* Macros for indirect DCR access
*/
ppc4xx: respect 80-chars per line in ppc*.h files After running checkstyle.pl on the three previous patches I noted that in the *.h files there were a lot of long lines. This patch solves this problem. Signed-off-by: Niklaus Giger <niklaus.giger@member.fsf.org> Signed-off-by: Stefan Roese <sr@denx.de>
2009-10-04 18:04:22 +00:00
#define mtcpr(reg, d) \
do { mtdcr(CPR0_CFGADDR, reg); mtdcr(CPR0_CFGDATA, d); } while (0)
#define mfcpr(reg, d) \
do { mtdcr(CPR0_CFGADDR, reg); d = mfdcr(CPR0_CFGDATA); } while (0)
#define mtebc(reg, d) \
do { mtdcr(EBC0_CFGADDR, reg); mtdcr(EBC0_CFGDATA, d); } while (0)
#define mfebc(reg, d) \
do { mtdcr(EBC0_CFGADDR, reg); d = mfdcr(EBC0_CFGDATA); } while (0)
#define mtsdram(reg, d) \
do { mtdcr(SDRAM0_CFGADDR, reg); mtdcr(SDRAM0_CFGDATA, d); } while (0)
#define mfsdram(reg, d) \
do { mtdcr(SDRAM0_CFGADDR, reg); d = mfdcr(SDRAM0_CFGDATA); } while (0)
#define mtsdr(reg, d) \
do { mtdcr(SDR0_CFGADDR, reg); mtdcr(SDR0_CFGDATA, d); } while (0)
#define mfsdr(reg, d) \
do { mtdcr(SDR0_CFGADDR, reg); d = mfdcr(SDR0_CFGDATA); } while (0)
ppc4xx: Consolidate some of the 405 and 440 macros/structs into 4xx This patch moves some common 4xx macros and the PPC405_SYS_INFO/ PPC440_SYS_INFO structure into the common ppc4xx.h header. Lot's of other macros are good candidates to be consolidated this way in the future. Signed-off-by: Stefan Roese <sr@denx.de>
2007-10-21 06:12:41 +00:00
#ifndef __ASSEMBLY__
typedef struct
{
unsigned long freqDDR;
unsigned long freqEBC;
unsigned long freqOPB;
unsigned long freqPCI;
unsigned long freqPLB;
unsigned long freqTmrClk;
unsigned long freqUART;
unsigned long freqProcessor;
unsigned long freqVCOHz;
unsigned long freqVCOMhz; /* in MHz */
unsigned long pciClkSync; /* PCI clock is synchronous */
unsigned long pciIntArbEn; /* Internal PCI arbiter is enabled */
unsigned long pllExtBusDiv;
unsigned long pllFbkDiv;
unsigned long pllFwdDiv;
unsigned long pllFwdDivA;
unsigned long pllFwdDivB;
unsigned long pllOpbDiv;
unsigned long pllPciDiv;
unsigned long pllPlbDiv;
} PPC4xx_SYS_INFO;
ppc4xx: Update Kilauea to use PPC4xx DDR autocalibration routines Signed-off-by: Adam Graham <agraham@amcc.com> Signed-off-by: Stefan Roese <sr@denx.de>
2008-09-03 19:26:59 +00:00
static inline u32 get_mcsr(void)
{
u32 val;
asm volatile("mfspr %0, 0x23c" : "=r" (val) :);
return val;
}
static inline void set_mcsr(u32 val)
{
asm volatile("mtspr 0x23c, %0" : "=r" (val) :);
}
ppc4xx: Add function to check and dynamically change PCI sync clock PPC440EP(x)/PPC440GR(x): In asynchronous PCI mode, the synchronous PCI clock must meet certain requirements. The following equation describes the relationship that must be maintained between the asynchronous PCI clock and synchronous PCI clock. Select an appropriate PCI:PLB ratio to maintain the relationship: AsyncPCIClk - 1MHz <= SyncPCIclock <= (2 * AsyncPCIClk) - 1MHz This patch now adds a function to check and reconfigure the sync PCI clock to meet this requirement. This is in preparation for some AMCC boards (Sequoia/Rainier and Yosemite/Yellowstone) using this function to not violate the PCI clocking rules. Signed-off-by: Stefan Roese <sr@denx.de>
2009-10-19 12:06:23 +00:00
int ppc4xx_pci_sync_clock_config(u32 async);
ppc4xx: Consolidate some of the 405 and 440 macros/structs into 4xx This patch moves some common 4xx macros and the PPC405_SYS_INFO/ PPC440_SYS_INFO structure into the common ppc4xx.h header. Lot's of other macros are good candidates to be consolidated this way in the future. Signed-off-by: Stefan Roese <sr@denx.de>
2007-10-21 06:12:41 +00:00
#endif /* __ASSEMBLY__ */
ppc4xx: Add routine to retrieve CPU number Provide a weak defined routine to retrieve the CPU number for reference boards that have multiple CPU's. Default behavior is the existing single CPU print output. Reference boards with multiple CPU's need to provide a board specific routine. See board/amcc/arches/arches.c for an example. Signed-off-by: Adam Graham <agraham@amcc.com> Signed-off-by: Victor Gallardo <vgallardo@amcc.com> Signed-off-by: Stefan Roese <sr@denx.de>
2008-10-08 17:13:19 +00:00
/* for multi-cpu support */
#define NA_OR_UNKNOWN_CPU -1
Initial revision
2002-08-06 20:46:37 +00:00
#endif /* __PPC4XX_H__ */
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