2022-12-14 17:51:05 +00:00
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* (C) Copyright 2019 Rockchip Electronics Co., Ltd
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* Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd.
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*/
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#ifndef __CONFIG_RV1126_COMMON_H
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#define __CONFIG_RV1126_COMMON_H
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#include "rockchip-common.h"
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#define CFG_SYS_HZ_CLOCK 24000000
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#define CFG_IRAM_BASE 0xff700000
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#define GICD_BASE 0xfeff1000
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#define GICC_BASE 0xfeff2000
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#define CFG_SYS_SDRAM_BASE 0
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#define SDRAM_MAX_SIZE 0xfd000000
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/* memory size > 128MB */
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#define ENV_MEM_LAYOUT_SETTINGS \
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"scriptaddr=0x00000000\0" \
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"pxefile_addr_r=0x00100000\0" \
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"fdt_addr_r=0x08300000\0" \
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2023-07-29 13:41:42 +00:00
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"fdtoverlay_addr_r=0x02000000\0" \
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2022-12-14 17:51:05 +00:00
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"kernel_addr_r=0x02008000\0" \
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"ramdisk_addr_r=0x0a200000\0"
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#include <config_distro_bootcmd.h>
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#define CFG_EXTRA_ENV_SETTINGS \
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"fdt_high=0x0fffffff\0" \
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"initrd_high=0x0fffffff\0" \
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"fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
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"partitions=" PARTS_DEFAULT \
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ENV_MEM_LAYOUT_SETTINGS \
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ROCKCHIP_DEVICE_SETTINGS \
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BOOTENV
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#endif /* __CONFIG_RV1126_COMMON_H */
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