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u-boot/drivers/ram/Makefile

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drivers: cosmetic: Convert SPDX license tags to Linux Kernel style Complete in the drivers directory the work started with commit 83d290c56fab ("SPDX: Convert all of our single license tags to Linux Kernel style"). Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2018-10-26 07:02:52 +00:00
# SPDX-License-Identifier: GPL-2.0+
dm: Add support for RAM drivers Add support for a driver which sets up DRAM and can return information about the amount of RAM available. This is a first step towards moving RAM init to driver model. Signed-off-by: Simon Glass <sjg@chromium.org>
2015-06-23 21:39:04 +00:00
#
# Copyright (c) 2015 Google, Inc
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
ram: Mark ram-uclass depend on TPL_DM or SPL_DM ram-uclass is building irrespective of whether TPL_DM or SPL_DM is enabled. So control the ram uclass build based on TPL/SPL_DM. Signed-off-by: Jagan Teki <jagan@edgeble.ai> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2022-12-14 17:50:47 +00:00
obj-$(CONFIG_$(SPL_TPL_)DM) += ram-uclass.o
ram: Add driver for MPC83xx Add a RAM driver for the MPC83xx architecture. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Mario Six <mario.six@gdsys.cc>
2018-08-06 08:23:30 +00:00
obj-$(CONFIG_MPC83XX_SDRAM) += mpc83xx_sdram.o
dm: test: Add a test for the ram uclass Add a test to confirm that we can probe this device and get information on the available RAM. Signed-off-by: Simon Glass <sjg@chromium.org>
2015-07-06 18:54:31 +00:00
obj-$(CONFIG_SANDBOX) += sandbox_ram.o
ram: stm32mp1: add driver Add driver and binding for stm32mp1 ddr controller and phy Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2018-03-12 09:46:11 +00:00
obj-$(CONFIG_STM32MP1_DDR) += stm32mp1/
stm32f7: sdram: move sdram driver code to ram drivers area Signed-off-by: Vikas Manocha <vikas.manocha@st.com> cc: Christophe KERELLO <christophe.kerello@st.com>
2017-04-10 22:02:51 +00:00
obj-$(CONFIG_STM32_SDRAM) += stm32_sdram.o
ram: add RAM driver for Broadcom MIPS SoCs Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-24 22:39:19 +00:00
obj-$(CONFIG_ARCH_BMIPS) += bmips_ram.o
rockchip: rk3368: add DRAM controller driver with DRAM initialisation This adds a DRAM controller driver for the RK3368 and places it in drivers/ram/rockchip (where the other DM-enabled DRAM controller drivers for rockchip devices should also be moved eventually). At this stage, only the following feature-set is supported: - DDR3 - 32-bit configuration (i.e. fully populated) - dual-rank (i.e. no auto-detection of ranks) - DDR3-1600K speed-bin This driver expects to run from a TPL stage that will later return to the RK3368 BROM. It communicates with later stages through the os_reg2 in the pmugrf (i.e. using the same mechanism as Rockchip's DDR init code). Unlike other DMC drivers for RK32xx and RK33xx parts, the required timings are calculated within the driver based on a target frequency and a DDR3 speed-bin (only the DDR3-1600K speed-bin is support at this time). The RK3368 also has the DDRC0_CON0 (DDR ch. 0, control-register 0) register for controlling the operation of its (single-channel) DRAM controller in the GRF block. This provides for selecting DDR3, mobile DDR modes, and control low-power operation. As part of this change, DDRC0_CON0 is also added to the GRF structure definition (at offset 0x600). Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-06-22 22:12:05 +00:00
obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/
ram: Introduce K3 AM654 DDR Sub System driver K3 based AM654 devices has DDR memory subsystem that comprises Synopys DDR controller, Synopsis DDR phy and wrapper logic to intergrate these blocks into the device. This DDR subsystem provides an interface to external SDRAM devices. Adding support for the initialization of the external SDRAM devices by configuring the DDRSS registers and using the buitin PHY routines. Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Andreas Dannenberg <dannenberg@ti.com> Signed-off-by: Keerthy <j-keerthy@ti.com> Signed-off-by: Schuyler Patton <spatton@ti.com> Signed-off-by: James Doublesin <doublesin@ti.com>
2018-11-02 14:21:02 +00:00
obj-$(CONFIG_K3_AM654_DDRSS) += k3-am654-ddrss.o
ram: MediaTek: add DDR3 driver for MT7629 SoC This patch adds a DDR3 driver for MT7629 SoC. Signed-off-by: Wu Zou <wu.zou@mediatek.com> Signed-off-by: Ryder Lee <ryder.lee@mediatek.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2018-11-15 02:08:03 +00:00
obj-$(CONFIG_ARCH_MEDIATEK) += mediatek/
ram: move aspeed ram driver into drivers/ directory to improve the maintainability. It is more easier to modify and add configurations of the driver in the centralized ram driver directory. Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.com> Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>
2020-09-07 08:25:06 +00:00
obj-$(CONFIG_ARCH_ASPEED) += aspeed/
ram: k3-ddrss: Introduce top-level CONFIG_K3_DDRSS Create a new CONFIG_K3_DDRSS option to select the common parts of the k3-ddrss driver. Also introduce a choice that depends on the top level option to select CONFIG_K3_J721E_DDRSS for j721e support, and update corresponding Kconfig as required. Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2021-05-11 15:22:10 +00:00
obj-$(CONFIG_K3_DDRSS) += k3-ddrss/
ram: add SDRAM driver for i.MXRT SoCs Add SDRAM driver for i.MXRT SoCs. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
2020-01-10 14:51:44 +00:00
obj-$(CONFIG_IMXRT_SDRAM) += imxrt_sdram.o
sifive: fu540: add ddr driver Add driver for fu540 to support ddr initialization in SPL. This driver is based on FSBL (https://github.com/sifive/freedom-u540-c000-bootloader.git) Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2020-05-29 06:03:26 +00:00
obj-$(CONFIG_RAM_SIFIVE) += sifive/
ram: starfive: add ddr driver Add driver for StarFive JH7110 to support ddr initialization in SPL. Signed-off-by: Yanhong Wang <yanhong.wang@starfivetech.com> Tested-by: Conor Dooley <conor.dooley@microchip.com>
2023-03-29 03:42:16 +00:00
ifdef CONFIG_SPL_BUILD
obj-$(CONFIG_SPL_STARFIVE_DDR) += starfive/
endif
sunxi: add R528/T113-s3/D1(s) DRAM initialisation code The Allwinner R528/T113-s/D1/D1s SoCs all share the same die, so use the same DRAM initialisation code. Make use of prior art here and lift some code from awboot[1], which carried init code based on earlier decompilation efforts, but with a GPL2 license tag. This code has been heavily reworked and cleaned up, to match previous DRAM routines for other SoCs, and also to be closer to U-Boot's coding style and support routines. The actual DRAM chip timing parameters are included in the main file, since they cover all DRAM types, and are protected by a new Kconfig CONFIG_SUNXI_DRAM_TYPE symbol, which allows the compiler to pick only the relevant settings, at build time. The relevant DRAM chips/board specific configuration parameters are delivered via Kconfig, so this code here should work for all supported SoCs and DRAM chips combinations. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Tested-by: Sam Edwards <CFSworks@gmail.com>
2022-12-31 18:38:21 +00:00
obj-$(CONFIG_DRAM_SUN20I_D1) += sunxi/
ram: octeon: Add MIPS Octeon3 DDR4 support (part 3/3) This Octeon 3 DDR driver is ported from the 2013 Cavium / Marvell U-Boot repository. It currently supports DDR4 on Octeon 3. It can be later extended to support also DDR3 and Octeon 2 platforms. Part 3 includes the DIMM SPD handling code and the Kconfig / Makefile integration. Signed-off-by: Aaron Williams <awilliams@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
2020-09-02 06:29:08 +00:00
obj-$(CONFIG_ARCH_OCTEON) += octeon/
ram: cadence: add driver for Cadence EDAC Driver for Cadence EDAC DDR controller, as found in the Renesas RZ/N1. Signed-off-by: Ralph Siemsen <ralph.siemsen@linaro.org> Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-05-13 01:36:53 +00:00
board: schneider: add RZN1 board support Add support for Schneider Electric RZ/N1D and RZ/N1S boards, which are based on the Reneasas RZ/N1 SoC devices. The intention is to support both boards using a single defconfig, and to handle the differences at runtime. Signed-off-by: Ralph Siemsen <ralph.siemsen@linaro.org> Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-05-13 01:36:56 +00:00
obj-$(CONFIG_ARCH_RMOBILE) += renesas/
ram: cadence: add driver for Cadence EDAC Driver for Cadence EDAC DDR controller, as found in the Renesas RZ/N1. Signed-off-by: Ralph Siemsen <ralph.siemsen@linaro.org> Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-05-13 01:36:53 +00:00
obj-$(CONFIG_CADENCE_DDR_CTRL) += cadence/
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