2018-04-27 12:53:15 +00:00
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2017
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* Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc
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*
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* based on the gdsys osd driver, which is
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*
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* (C) Copyright 2010
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* Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
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*/
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#include <common.h>
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#include <dm.h>
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#include <clk-uclass.h>
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#include <i2c.h>
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2020-05-10 17:40:05 +00:00
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#include <log.h>
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2018-04-27 12:53:15 +00:00
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const long long ICS8N3QV01_FREF = 114285000;
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const long long ICS8N3QV01_FREF_LL = 114285000LL;
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const long long ICS8N3QV01_F_DEFAULT_0 = 156250000LL;
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const long long ICS8N3QV01_F_DEFAULT_1 = 125000000LL;
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const long long ICS8N3QV01_F_DEFAULT_2 = 100000000LL;
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const long long ICS8N3QV01_F_DEFAULT_3 = 25175000LL;
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const uint MAX_FREQ_INDEX = 3;
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struct ics8n3qv01_priv {
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ulong rate;
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};
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static int ics8n3qv01_get_fout_calc(struct udevice *dev, uint index,
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uint *fout_calc)
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{
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u64 n, mint, mfrac;
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u8 reg_a, reg_b, reg_c, reg_d, reg_f;
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int val[6];
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int i;
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if (index > MAX_FREQ_INDEX)
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return -EINVAL;
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for (i = 0; i <= 5; ++i) {
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u8 tmp = dm_i2c_reg_read(dev, 4 * i + index);
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if (tmp < 0) {
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debug("%s: Error while reading i2c register %d.\n",
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dev->name, 4 * i + index);
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return tmp;
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}
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val[i] = tmp;
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}
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reg_a = val[0]; /* Register 0 + index */
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reg_b = val[1]; /* Register 4 + index */
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reg_c = val[2]; /* Register 8 + index */
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reg_d = val[3]; /* Register 12 + index */
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reg_f = val[5]; /* Register 20 + index */
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mint = ((reg_a >> 1) & 0x1f) | /* MINTi[4-0]*/
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(reg_f & 0x20); /* MINTi[5] */
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mfrac = ((reg_a & 0x01) << 17) | /* MFRACi[17] */
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(reg_b << 9) | /* MFRACi[16-9] */
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(reg_c << 1) | /* MFRACi[8-1] */
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(reg_d >> 7); /* MFRACi[0] */
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n = reg_d & 0x7f; /* Ni[6-0] */
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*fout_calc = (mint * ICS8N3QV01_FREF_LL
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+ mfrac * ICS8N3QV01_FREF_LL / 262144LL
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+ ICS8N3QV01_FREF_LL / 524288LL
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+ n / 2)
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/ n
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* 1000000
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/ (1000000 - 100);
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return 0;
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}
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static int ics8n3qv01_calc_parameters(uint fout, uint *_mint, uint *_mfrac,
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uint *_n)
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{
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uint n, foutiic, fvcoiic, mint;
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u64 mfrac;
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if (fout < 417000000U)
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n = 2 * ((2215000000U / 2 + fout / 2) / fout);
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else
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n = (2215000000U + fout / 2) / fout;
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if ((n & 1) && n > 5)
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n -= 1;
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foutiic = fout - (fout / 10000);
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fvcoiic = foutiic * n;
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mint = fvcoiic / 114285000;
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if (mint < 17 || mint > 63)
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return -EINVAL;
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mfrac = ((u64)fvcoiic % 114285000LL) * 262144LL
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/ 114285000LL;
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*_mint = mint;
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*_mfrac = mfrac;
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*_n = n;
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return 0;
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}
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static ulong ics8n3qv01_set_rate(struct clk *clk, ulong fout)
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{
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struct ics8n3qv01_priv *priv = dev_get_priv(clk->dev);
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uint n, mint, mfrac;
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uint fout_calc = 0;
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u64 fout_prog;
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long long off_ppm;
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int res, i;
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u8 reg[6];
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int tmp;
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int addr[] = {0, 4, 8, 12, 18, 20};
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priv->rate = fout;
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res = ics8n3qv01_get_fout_calc(clk->dev, 1, &fout_calc);
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if (res) {
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debug("%s: Error during output frequency calculation.\n",
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clk->dev->name);
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return res;
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}
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off_ppm = (fout_calc - ICS8N3QV01_F_DEFAULT_1) * 1000000
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/ ICS8N3QV01_F_DEFAULT_1;
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printf("%s: PLL is off by %lld ppm\n", clk->dev->name, off_ppm);
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fout_prog = (u64)fout * (u64)fout_calc
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/ ICS8N3QV01_F_DEFAULT_1;
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res = ics8n3qv01_calc_parameters(fout_prog, &mint, &mfrac, &n);
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if (res) {
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debug("%s: Cannot determine mint parameter.\n",
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clk->dev->name);
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return res;
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}
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/* Register 0 */
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tmp = dm_i2c_reg_read(clk->dev, 0) & 0xc0;
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if (tmp < 0)
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return tmp;
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reg[0] = tmp | (mint & 0x1f) << 1;
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reg[0] |= (mfrac >> 17) & 0x01;
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/* Register 4 */
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reg[1] = mfrac >> 9;
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/* Register 8 */
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reg[2] = mfrac >> 1;
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/* Register 12 */
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reg[3] = mfrac << 7;
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reg[3] |= n & 0x7f;
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/* Register 18 */
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tmp = dm_i2c_reg_read(clk->dev, 18) & 0x03;
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if (tmp < 0)
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return tmp;
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reg[4] = tmp | 0x20;
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/* Register 20 */
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tmp = dm_i2c_reg_read(clk->dev, 20) & 0x1f;
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if (tmp < 0)
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return tmp;
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reg[5] = tmp | (mint & (1 << 5));
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for (i = 0; i <= 5; ++i) {
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res = dm_i2c_reg_write(clk->dev, addr[i], reg[i]);
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if (res < 0)
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return res;
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}
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return 0;
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}
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static int ics8n3qv01_request(struct clk *clock)
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{
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return 0;
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}
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static ulong ics8n3qv01_get_rate(struct clk *clk)
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{
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struct ics8n3qv01_priv *priv = dev_get_priv(clk->dev);
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return priv->rate;
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}
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static int ics8n3qv01_enable(struct clk *clk)
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{
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return 0;
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}
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static int ics8n3qv01_disable(struct clk *clk)
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{
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return 0;
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}
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static const struct clk_ops ics8n3qv01_ops = {
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.request = ics8n3qv01_request,
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.get_rate = ics8n3qv01_get_rate,
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.set_rate = ics8n3qv01_set_rate,
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.enable = ics8n3qv01_enable,
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.disable = ics8n3qv01_disable,
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};
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static const struct udevice_id ics8n3qv01_ids[] = {
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{ .compatible = "idt,ics8n3qv01" },
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{ /* sentinel */ }
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};
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int ics8n3qv01_probe(struct udevice *dev)
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{
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return 0;
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}
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U_BOOT_DRIVER(ics8n3qv01) = {
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.name = "ics8n3qv01",
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.id = UCLASS_CLK,
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.ops = &ics8n3qv01_ops,
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.of_match = ics8n3qv01_ids,
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.probe = ics8n3qv01_probe,
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.priv_auto_alloc_size = sizeof(struct ics8n3qv01_priv),
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};
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