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https://github.com/AsahiLinux/u-boot
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87 lines
1.7 KiB
Text
87 lines
1.7 KiB
Text
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// SPDX-License-Identifier: GPL-2.0
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/*
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* dts file for Xilinx ZynqMP System Controller X-PRC-05 revA (SE5)
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*
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* (C) Copyright 2019 - 2022, Xilinx, Inc.
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* (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
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*
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* Michal Simek <michal.simek@amd.com>
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*/
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/dts-v1/;
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/plugin/;
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/{
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compatible = "xlnx,zynqmp-x-prc-05-revA", "xlnx,zynqmp-x-prc-05";
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fragment@0 {
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target = <&dc_i2c>;
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__overlay__ {
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#address-cells = <1>;
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#size-cells = <0>;
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x_prc_eeprom: eeprom@52 { /* u120 */
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compatible = "atmel,24c02";
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reg = <0x52>;
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};
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x_prc_tca9534: gpio@22 { /* u121 tca9534 */
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compatible = "nxp,pca9534";
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reg = <0x22>;
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gpio-controller; /* IRQ not connected */
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#gpio-cells = <2>;
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gpio-line-names = "sw4_1", "sw4_2", "sw4_3", "sw4_4",
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"", "", "", "";
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gtr-sel0 {
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gpio-hog;
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gpios = <0 0>;
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input; /* FIXME add meaning */
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line-name = "sw4_1";
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};
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gtr-sel1 {
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gpio-hog;
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gpios = <1 0>;
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input; /* FIXME add meaning */
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line-name = "sw4_2";
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};
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gtr-sel2 {
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gpio-hog;
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gpios = <2 0>;
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input; /* FIXME add meaning */
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line-name = "sw4_3";
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};
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gtr-sel3 {
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gpio-hog;
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gpios = <3 0>;
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input; /* FIXME add meaning */
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line-name = "sw4_4";
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};
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};
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si570_gem_tsu: clock-generator@5d { /* u164 */
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#clock-cells = <0>;
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compatible = "silabs,si570";
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reg = <0x5d>;
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temperature-stability = <50>;
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factory-fout = <300000000>; /* FIXME */
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clock-frequency = <300000000>;
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clock-output-names = "si570_gem_tsu_clk";
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};
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};
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};
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fragment@1 {
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target = <&i2c1>;
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__overlay__ {
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#address-cells = <1>;
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#size-cells = <0>;
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eeprom_versal: eeprom@51 { /* u153 */
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compatible = "atmel,24c02";
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reg = <0x51>;
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};
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};
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};
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};
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