u-boot/arch/arm/include/asm/utils.h

/* SPDX-License-Identifier: GPL-2.0+ */
/*
 * (C) Copyright 2010
 * Texas Instruments, <www.ti.com>
 * Aneesh V <aneesh@ti.com>
 */
#ifndef _UTILS_H_
#define _UTILS_H_

static inline s32 log_2_n_round_up(u32 n)
{
	s32 log2n = -1;
	u32 temp = n;

	while (temp) {
		log2n++;
		temp >>= 1;
	}

	if (n & (n - 1))
		return log2n + 1; /* not power of 2 - round up */
	else
		return log2n; /* power of 2 */
}

static inline s32 log_2_n_round_down(u32 n)
{
	s32 log2n = -1;
	u32 temp = n;

	while (temp) {
		log2n++;
		temp >>= 1;
	}

	return log2n;
}

#endif
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com> 2018-05-06 21:58:06 +00:00			`/* SPDX-License-Identifier: GPL-2.0+ */`
armv7: cache maintenance operations for armv7 - Add a framework for layered cache maintenance - separate out SOC specific outer cache maintenance from maintenance of caches known to CPU - Add generic ARMv7 cache maintenance operations that affect all caches known to ARMv7 CPUs. For instance in Cortex-A8 these opertions will affect both L1 and L2 caches. In Cortex-A9 these will affect only L1 cache - D-cache operations supported: - Invalidate entire D-cache - Invalidate D-cache range - Flush(clean & invalidate) entire D-cache - Flush D-cache range - I-cache operations supported: - Invalidate entire I-cache - Add maintenance functions for TLB, branch predictor array etc. - Enable -march=armv7-a so that armv7 assembly instructions can be used Signed-off-by: Aneesh V <aneesh@ti.com> 2011-06-16 23:30:47 +00:00			`/*`
			`* (C) Copyright 2010`
			`* Texas Instruments, <www.ti.com>`
			`* Aneesh V <aneesh@ti.com>`
			`*/`
			`#ifndef _UTILS_H_`
			`#define _UTILS_H_`

			`static inline s32 log_2_n_round_up(u32 n)`
			`{`
			`s32 log2n = -1;`
			`u32 temp = n;`

			`while (temp) {`
			`log2n++;`
			`temp >>= 1;`
			`}`

			`if (n & (n - 1))`
			`return log2n + 1; /* not power of 2 - round up */`
			`else`
			`return log2n; /* power of 2 */`
			`}`

			`static inline s32 log_2_n_round_down(u32 n)`
			`{`
			`s32 log2n = -1;`
			`u32 temp = n;`

			`while (temp) {`
			`log2n++;`
			`temp >>= 1;`
			`}`

			`return log2n;`
			`}`

			`#endif`