2018-10-18 12:28:07 +00:00
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright 2018 NXP
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*/
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#ifndef _SC_SCI_H
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#define _SC_SCI_H
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#include <asm/arch/sci/types.h>
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#include <asm/arch/sci/svc/misc/api.h>
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#include <asm/arch/sci/svc/pad/api.h>
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#include <asm/arch/sci/svc/pm/api.h>
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#include <asm/arch/sci/svc/rm/api.h>
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#include <asm/arch/sci/rpc.h>
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#include <dt-bindings/soc/imx_rsrc.h>
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#include <linux/errno.h>
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static inline int sc_err_to_linux(sc_err_t err)
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{
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int ret;
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switch (err) {
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case SC_ERR_NONE:
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return 0;
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case SC_ERR_VERSION:
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case SC_ERR_CONFIG:
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case SC_ERR_PARM:
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ret = -EINVAL;
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break;
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case SC_ERR_NOACCESS:
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case SC_ERR_LOCKED:
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case SC_ERR_UNAVAILABLE:
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ret = -EACCES;
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break;
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case SC_ERR_NOTFOUND:
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case SC_ERR_NOPOWER:
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ret = -ENODEV;
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break;
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case SC_ERR_IPC:
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ret = -EIO;
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break;
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case SC_ERR_BUSY:
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ret = -EBUSY;
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break;
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case SC_ERR_FAIL:
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ret = -EIO;
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break;
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default:
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ret = 0;
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break;
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}
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debug("%s %d %d\n", __func__, err, ret);
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return ret;
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}
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2018-10-18 12:28:12 +00:00
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/* PM API*/
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int sc_pm_set_resource_power_mode(sc_ipc_t ipc, sc_rsrc_t resource,
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sc_pm_power_mode_t mode);
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int sc_pm_set_clock_rate(sc_ipc_t ipc, sc_rsrc_t resource, sc_pm_clk_t clk,
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sc_pm_clock_rate_t *rate);
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int sc_pm_get_clock_rate(sc_ipc_t ipc, sc_rsrc_t resource, sc_pm_clk_t clk,
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sc_pm_clock_rate_t *rate);
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int sc_pm_clock_enable(sc_ipc_t ipc, sc_rsrc_t resource, sc_pm_clk_t clk,
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sc_bool_t enable, sc_bool_t autog);
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/* MISC API */
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int sc_misc_get_control(sc_ipc_t ipc, sc_rsrc_t resource, sc_ctrl_t ctrl,
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u32 *val);
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void sc_misc_get_boot_dev(sc_ipc_t ipc, sc_rsrc_t *boot_dev);
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void sc_misc_boot_status(sc_ipc_t ipc, sc_misc_boot_status_t status);
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void sc_misc_build_info(sc_ipc_t ipc, u32 *build, u32 *commit);
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int sc_misc_otp_fuse_read(sc_ipc_t ipc, u32 word, u32 *val);
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/* RM API */
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sc_bool_t sc_rm_is_memreg_owned(sc_ipc_t ipc, sc_rm_mr_t mr);
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int sc_rm_get_memreg_info(sc_ipc_t ipc, sc_rm_mr_t mr, sc_faddr_t *addr_start,
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sc_faddr_t *addr_end);
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sc_bool_t sc_rm_is_resource_owned(sc_ipc_t ipc, sc_rsrc_t resource);
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/* PAD API */
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int sc_pad_set(sc_ipc_t ipc, sc_pad_t pad, u32 val);
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2018-10-18 12:28:07 +00:00
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#endif
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