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SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
2018-05-06 21:58:06 +00:00
// SPDX-License-Identifier: GPL-2.0+
dm: pci: Use driver model PCI API in auto-config At present we are using legacy functions even in the auto-configuration code used by driver model. Add a new pci_auto.c version which uses the correct API. Create a new pci_internal.h header to hold functions that are used within the PCI subsystem, but are not exported to other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2015-11-29 20:17:49 +00:00
/*
* PCI autoconfiguration library
*
* Author: Matt Porter <mporter@mvista.com>
*
* Copyright 2000 MontaVista Software Inc.
pci: Work around PCIe link training failures Attempt to handle cases with a downstream port of a PCIe switch where link training never completes and the link continues switching between speeds indefinitely with the data link layer never reaching the active state. It has been observed with a downstream port of the ASMedia ASM2824 Gen 3 switch wired to the upstream port of the Pericom PI7C9X2G304 Gen 2 switch, using a Delock Riser Card PCI Express x1 > 2 x PCIe x1 device, P/N 41433, wired to a SiFive HiFive Unmatched board. In this setup the switches are supposed to negotiate the link speed of preferably 5.0GT/s, falling back to 2.5GT/s. However the link continues oscillating between the two speeds, at the rate of 34-35 times per second, with link training reported repeatedly active ~84% of the time, e.g.: 02:03.0 PCI bridge [0604]: ASMedia Technology Inc. ASM2824 PCIe Gen3 Packet Switch [1b21:2824] (rev 01) (prog-if 00 [Normal decode]) [...] Bus: primary=02, secondary=05, subordinate=05, sec-latency=0 [...] Capabilities: [80] Express (v2) Downstream Port (Slot+), MSI 00 [...] LnkSta: Speed 5GT/s (downgraded), Width x1 (ok) TrErr- Train+ SlotClk+ DLActive- BWMgmt+ ABWMgmt- [...] LnkCtl2: Target Link Speed: 8GT/s, EnterCompliance- SpeedDis+, Selectable De-emphasis: -3.5dB Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS- Compliance De-emphasis: -6dB [...] Forcibly limiting the target link speed to 2.5GT/s with the upstream ASM2824 device makes the two switches communicate correctly however: 02:03.0 PCI bridge [0604]: ASMedia Technology Inc. ASM2824 PCIe Gen3 Packet Switch [1b21:2824] (rev 01) (prog-if 00 [Normal decode]) [...] Bus: primary=02, secondary=05, subordinate=09, sec-latency=0 [...] Capabilities: [80] Express (v2) Downstream Port (Slot+), MSI 00 [...] LnkSta: Speed 2.5GT/s (downgraded), Width x1 (ok) TrErr- Train- SlotClk+ DLActive+ BWMgmt- ABWMgmt- [...] LnkCtl2: Target Link Speed: 2.5GT/s, EnterCompliance- SpeedDis+, Selectable De-emphasis: -3.5dB Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS- Compliance De-emphasis: -6dB [...] and then: 05:00.0 PCI bridge [0604]: Pericom Semiconductor PI7C9X2G304 EL/SL PCIe2 3-Port/4-Lane Packet Switch [12d8:2304] (rev 05) (prog-if 00 [Normal decode]) [...] Bus: primary=05, secondary=06, subordinate=09, sec-latency=0 [...] Capabilities: [c0] Express (v2) Upstream Port, MSI 00 [...] LnkSta: Speed 2.5GT/s (downgraded), Width x1 (downgraded) TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt- [...] LnkCtl2: Target Link Speed: 5GT/s, EnterCompliance- SpeedDis- Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS- Compliance De-emphasis: -6dB [...] Make use of this observation then and attempt to detect the inability to negotiate the link speed automatically, and then handle it by hand. Use the Data Link Layer Link Active status flag as the primary indicator of successful link speed negotiation, but given that the flag is optional by hardware to implement (the ASM2824 does have it though), resort to checking for the mandatory Link Bandwidth Management Status flag showing that the link speed or width has been changed in an attempt to correct unreliable link operation (the ASM2824 does set it too). If these checks indicate that link may not operate correctly, then poll the Data Link Layer Link Active status flag along with the Link Training flag for the duration of 200ms to see if the link has stabilised, that is either that the Data Link Layer Link Active status flag has been set or that Link Training has been inactive during at least the second half of the interval. If that has indicated failure, restrict the target speed to 2.5GT/s, request a link retrain and check again if the link has stabilised. If that does not work either, then restore the original speed setting and claim defeat, otherwise we are done. NB interestingly enough with the ASM2824 vs PI7C9X2G304 configuration referred above asking the ASM2824 to retrain with a higher target link speed once the 2.5GT/s speed has been negotiated makes the two devices successfully negotiate 5.0GT/s. Lifting the 2.5GT/s speed restriction would however prevent our workaround from working with an OS that issues a reset and that is unaware of the problem. This is because the devices would then try to negotiate a higher link speed from scratch and fail, while the sticky property of the Target Link Speed setting will keep the 2.5GT/s speed restriction across a reset. Keep the 2.5GT/s speed restriction then, conservatively, if functional once applied. Signed-off-by: Maciej W. Rozycki <macro@orcam.me.uk> Reviewed-by: Stefan Roese <sr@denx.de>
2021-11-20 23:03:30 +00:00
* Copyright (c) 2021 Maciej W. Rozycki <macro@orcam.me.uk>
dm: pci: Use driver model PCI API in auto-config At present we are using legacy functions even in the auto-configuration code used by driver model. Add a new pci_auto.c version which uses the correct API. Create a new pci_internal.h header to hold functions that are used within the PCI subsystem, but are not exported to other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2015-11-29 20:17:49 +00:00
*/
#include <common.h>
dm: pci: Avoid using pci_bus_to_hose() in the uclass This function is only available for compatibility with old code. Avoid using it in the uclass. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-19 03:19:16 +00:00
#include <dm.h>
dm: pci: Use driver model PCI API in auto-config At present we are using legacy functions even in the auto-configuration code used by driver model. Add a new pci_auto.c version which uses the correct API. Create a new pci_internal.h header to hold functions that are used within the PCI subsystem, but are not exported to other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2015-11-29 20:17:49 +00:00
#include <errno.h>
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-10 17:40:05 +00:00
#include <log.h>
dm: pci: Use driver model PCI API in auto-config At present we are using legacy functions even in the auto-configuration code used by driver model. Add a new pci_auto.c version which uses the correct API. Create a new pci_internal.h header to hold functions that are used within the PCI subsystem, but are not exported to other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2015-11-29 20:17:49 +00:00
#include <pci.h>
pci: Work around PCIe link training failures Attempt to handle cases with a downstream port of a PCIe switch where link training never completes and the link continues switching between speeds indefinitely with the data link layer never reaching the active state. It has been observed with a downstream port of the ASMedia ASM2824 Gen 3 switch wired to the upstream port of the Pericom PI7C9X2G304 Gen 2 switch, using a Delock Riser Card PCI Express x1 > 2 x PCIe x1 device, P/N 41433, wired to a SiFive HiFive Unmatched board. In this setup the switches are supposed to negotiate the link speed of preferably 5.0GT/s, falling back to 2.5GT/s. However the link continues oscillating between the two speeds, at the rate of 34-35 times per second, with link training reported repeatedly active ~84% of the time, e.g.: 02:03.0 PCI bridge [0604]: ASMedia Technology Inc. ASM2824 PCIe Gen3 Packet Switch [1b21:2824] (rev 01) (prog-if 00 [Normal decode]) [...] Bus: primary=02, secondary=05, subordinate=05, sec-latency=0 [...] Capabilities: [80] Express (v2) Downstream Port (Slot+), MSI 00 [...] LnkSta: Speed 5GT/s (downgraded), Width x1 (ok) TrErr- Train+ SlotClk+ DLActive- BWMgmt+ ABWMgmt- [...] LnkCtl2: Target Link Speed: 8GT/s, EnterCompliance- SpeedDis+, Selectable De-emphasis: -3.5dB Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS- Compliance De-emphasis: -6dB [...] Forcibly limiting the target link speed to 2.5GT/s with the upstream ASM2824 device makes the two switches communicate correctly however: 02:03.0 PCI bridge [0604]: ASMedia Technology Inc. ASM2824 PCIe Gen3 Packet Switch [1b21:2824] (rev 01) (prog-if 00 [Normal decode]) [...] Bus: primary=02, secondary=05, subordinate=09, sec-latency=0 [...] Capabilities: [80] Express (v2) Downstream Port (Slot+), MSI 00 [...] LnkSta: Speed 2.5GT/s (downgraded), Width x1 (ok) TrErr- Train- SlotClk+ DLActive+ BWMgmt- ABWMgmt- [...] LnkCtl2: Target Link Speed: 2.5GT/s, EnterCompliance- SpeedDis+, Selectable De-emphasis: -3.5dB Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS- Compliance De-emphasis: -6dB [...] and then: 05:00.0 PCI bridge [0604]: Pericom Semiconductor PI7C9X2G304 EL/SL PCIe2 3-Port/4-Lane Packet Switch [12d8:2304] (rev 05) (prog-if 00 [Normal decode]) [...] Bus: primary=05, secondary=06, subordinate=09, sec-latency=0 [...] Capabilities: [c0] Express (v2) Upstream Port, MSI 00 [...] LnkSta: Speed 2.5GT/s (downgraded), Width x1 (downgraded) TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt- [...] LnkCtl2: Target Link Speed: 5GT/s, EnterCompliance- SpeedDis- Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS- Compliance De-emphasis: -6dB [...] Make use of this observation then and attempt to detect the inability to negotiate the link speed automatically, and then handle it by hand. Use the Data Link Layer Link Active status flag as the primary indicator of successful link speed negotiation, but given that the flag is optional by hardware to implement (the ASM2824 does have it though), resort to checking for the mandatory Link Bandwidth Management Status flag showing that the link speed or width has been changed in an attempt to correct unreliable link operation (the ASM2824 does set it too). If these checks indicate that link may not operate correctly, then poll the Data Link Layer Link Active status flag along with the Link Training flag for the duration of 200ms to see if the link has stabilised, that is either that the Data Link Layer Link Active status flag has been set or that Link Training has been inactive during at least the second half of the interval. If that has indicated failure, restrict the target speed to 2.5GT/s, request a link retrain and check again if the link has stabilised. If that does not work either, then restore the original speed setting and claim defeat, otherwise we are done. NB interestingly enough with the ASM2824 vs PI7C9X2G304 configuration referred above asking the ASM2824 to retrain with a higher target link speed once the 2.5GT/s speed has been negotiated makes the two devices successfully negotiate 5.0GT/s. Lifting the 2.5GT/s speed restriction would however prevent our workaround from working with an OS that issues a reset and that is unaware of the problem. This is because the devices would then try to negotiate a higher link speed from scratch and fail, while the sticky property of the Target Link Speed setting will keep the 2.5GT/s speed restriction across a reset. Keep the 2.5GT/s speed restriction then, conservatively, if functional once applied. Signed-off-by: Maciej W. Rozycki <macro@orcam.me.uk> Reviewed-by: Stefan Roese <sr@denx.de>
2021-11-20 23:03:30 +00:00
#include <time.h>
pci: include pci_internal.h inside pci_auto.c To avoid a build warning with W=1, provide a function prototype for dm_pciauto_prescan_setup_bridge, which is a non-static function whose definition is inside pci_auto.c. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2021-09-17 12:11:21 +00:00
#include "pci_internal.h"
dm: pci: Use driver model PCI API in auto-config At present we are using legacy functions even in the auto-configuration code used by driver model. Add a new pci_auto.c version which uses the correct API. Create a new pci_internal.h header to hold functions that are used within the PCI subsystem, but are not exported to other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2015-11-29 20:17:49 +00:00
global: Move remaining CONFIG_SYS_PCI* to CFG_SYS_PCI* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_PCI and CONFIG_SYS_PCIE namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2022-11-16 18:10:33 +00:00
/* the user can define CFG_SYS_PCI_CACHE_LINE_SIZE to avoid problems */
#ifndef CFG_SYS_PCI_CACHE_LINE_SIZE
#define CFG_SYS_PCI_CACHE_LINE_SIZE 8
dm: pci: Use driver model PCI API in auto-config At present we are using legacy functions even in the auto-configuration code used by driver model. Add a new pci_auto.c version which uses the correct API. Create a new pci_internal.h header to hold functions that are used within the PCI subsystem, but are not exported to other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2015-11-29 20:17:49 +00:00
#endif
pci: Fix configuring BARs Number of BARs is defined by header type, not by class code. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Stefan Roese <sr@denx.de>
2021-10-07 12:50:59 +00:00
static void dm_pciauto_setup_device(struct udevice *dev,
pci: Remove CONFIG_PCI_ENUM_ONLY as it's not used (any more) This patch completely removes CONFIG_PCI_ENUM_ONLY from the PCI code as it is not configured for any board (any more). With this removal, some PCI related files get cleaned up a bit. Additional, dm_pciauto_setup_device() is now static, as it's not referenced from any code outside of this C file. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-01-12 11:03:43 +00:00
struct pci_region *mem,
struct pci_region *prefetch,
struct pci_region *io)
dm: pci: Use driver model PCI API in auto-config At present we are using legacy functions even in the auto-configuration code used by driver model. Add a new pci_auto.c version which uses the correct API. Create a new pci_internal.h header to hold functions that are used within the PCI subsystem, but are not exported to other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2015-11-29 20:17:49 +00:00
{
u32 bar_response;
pci_size_t bar_size;
u16 cmdstat = 0;
int bar, bar_nr = 0;
pci: Fix configuring BARs Number of BARs is defined by header type, not by class code. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Stefan Roese <sr@denx.de>
2021-10-07 12:50:59 +00:00
int bars_num;
dm: pci: Use driver model PCI API in auto-config At present we are using legacy functions even in the auto-configuration code used by driver model. Add a new pci_auto.c version which uses the correct API. Create a new pci_internal.h header to hold functions that are used within the PCI subsystem, but are not exported to other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2015-11-29 20:17:49 +00:00
u8 header_type;
int rom_addr;
pci_addr_t bar_value;
pci: Fix compiler warnings in dm_pciauto_setup_device() Fix the following compiler warnings when DEBUG is on. warning: 'bar_res' may be used uninitialized in this function. drivers/pci/pci_auto.c:101:21: if (!enum_only && pciauto_region_allocate(bar_res, bar_size, ^ Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2016-02-18 07:14:47 +00:00
struct pci_region *bar_res = NULL;
dm: pci: Use driver model PCI API in auto-config At present we are using legacy functions even in the auto-configuration code used by driver model. Add a new pci_auto.c version which uses the correct API. Create a new pci_internal.h header to hold functions that are used within the PCI subsystem, but are not exported to other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2015-11-29 20:17:49 +00:00
int found_mem64 = 0;
u16 class;
dm_pci_read_config16(dev, PCI_COMMAND, &cmdstat);
cmdstat = (cmdstat & ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) |
PCI_COMMAND_MASTER;
pci: Fix configuring BARs Number of BARs is defined by header type, not by class code. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Stefan Roese <sr@denx.de>
2021-10-07 12:50:59 +00:00
dm_pci_read_config8(dev, PCI_HEADER_TYPE, &header_type);
header_type &= 0x7f;
switch (header_type) {
case PCI_HEADER_TYPE_NORMAL:
bars_num = 6;
break;
case PCI_HEADER_TYPE_BRIDGE:
bars_num = 2;
break;
case PCI_HEADER_TYPE_CARDBUS:
/* CardBus header does not have any BAR */
bars_num = 0;
break;
default:
/* Skip configuring BARs for unknown header types */
bars_num = 0;
break;
}
dm: pci: Use driver model PCI API in auto-config At present we are using legacy functions even in the auto-configuration code used by driver model. Add a new pci_auto.c version which uses the correct API. Create a new pci_internal.h header to hold functions that are used within the PCI subsystem, but are not exported to other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2015-11-29 20:17:49 +00:00
for (bar = PCI_BASE_ADDRESS_0;
bar < PCI_BASE_ADDRESS_0 + (bars_num * 4); bar += 4) {
pci: Show a message if PCI autoconfig fails At present this fails silently which can be confusing since some devices on the PCI bus may not work correctly. Show a message in this case. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: add a '\n' in the PCI autoconfig fail message] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2019-09-25 14:56:16 +00:00
int ret = 0;
dm: pci: Use driver model PCI API in auto-config At present we are using legacy functions even in the auto-configuration code used by driver model. Add a new pci_auto.c version which uses the correct API. Create a new pci_internal.h header to hold functions that are used within the PCI subsystem, but are not exported to other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2015-11-29 20:17:49 +00:00
/* Tickle the BAR and get the response */
pci: Remove CONFIG_PCI_ENUM_ONLY as it's not used (any more) This patch completely removes CONFIG_PCI_ENUM_ONLY from the PCI code as it is not configured for any board (any more). With this removal, some PCI related files get cleaned up a bit. Additional, dm_pciauto_setup_device() is now static, as it's not referenced from any code outside of this C file. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-01-12 11:03:43 +00:00
dm_pci_write_config32(dev, bar, 0xffffffff);
dm: pci: Use driver model PCI API in auto-config At present we are using legacy functions even in the auto-configuration code used by driver model. Add a new pci_auto.c version which uses the correct API. Create a new pci_internal.h header to hold functions that are used within the PCI subsystem, but are not exported to other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2015-11-29 20:17:49 +00:00
dm_pci_read_config32(dev, bar, &bar_response);
pci: Make auto-config code a little more robust On my DS414, some PCI devices return odd values when probing BAR sizes. An obvious case is all-ones response, the Linux driver (drivers/pci/probe.c) catches those explicitly and a comment explains that either bit 0 or bit 1 must be clear (depending on MEM or IO type). Other BARs return e.g. 0xfff0000f or 0xfff00004 and thus manage to break size calculation due to the "middle" zeroes. Mitigate that copying more or less what Linux does and do a "find least bit set". Signed-off-by: Phil Sutter <phil@nwl.cc> Reviewed-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-01-03 22:06:45 +00:00
/* If BAR is not implemented (or invalid) go to the next BAR */
if (!bar_response || bar_response == 0xffffffff)
dm: pci: Use driver model PCI API in auto-config At present we are using legacy functions even in the auto-configuration code used by driver model. Add a new pci_auto.c version which uses the correct API. Create a new pci_internal.h header to hold functions that are used within the PCI subsystem, but are not exported to other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2015-11-29 20:17:49 +00:00
continue;
found_mem64 = 0;
/* Check the BAR type and set our address mask */
if (bar_response & PCI_BASE_ADDRESS_SPACE) {
pci: Make auto-config code a little more robust On my DS414, some PCI devices return odd values when probing BAR sizes. An obvious case is all-ones response, the Linux driver (drivers/pci/probe.c) catches those explicitly and a comment explains that either bit 0 or bit 1 must be clear (depending on MEM or IO type). Other BARs return e.g. 0xfff0000f or 0xfff00004 and thus manage to break size calculation due to the "middle" zeroes. Mitigate that copying more or less what Linux does and do a "find least bit set". Signed-off-by: Phil Sutter <phil@nwl.cc> Reviewed-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-01-03 22:06:45 +00:00
bar_size = bar_response & PCI_BASE_ADDRESS_IO_MASK;
bar_size &= ~(bar_size - 1);
pci: Remove CONFIG_PCI_ENUM_ONLY as it's not used (any more) This patch completely removes CONFIG_PCI_ENUM_ONLY from the PCI code as it is not configured for any board (any more). With this removal, some PCI related files get cleaned up a bit. Additional, dm_pciauto_setup_device() is now static, as it's not referenced from any code outside of this C file. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-01-12 11:03:43 +00:00
bar_res = io;
dm: pci: Use driver model PCI API in auto-config At present we are using legacy functions even in the auto-configuration code used by driver model. Add a new pci_auto.c version which uses the correct API. Create a new pci_internal.h header to hold functions that are used within the PCI subsystem, but are not exported to other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2015-11-29 20:17:49 +00:00
debug("PCI Autoconfig: BAR %d, I/O, size=0x%llx, ",
bar_nr, (unsigned long long)bar_size);
} else {
if ((bar_response & PCI_BASE_ADDRESS_MEM_TYPE_MASK) ==
PCI_BASE_ADDRESS_MEM_TYPE_64) {
u32 bar_response_upper;
u64 bar64;
pci: Remove CONFIG_PCI_ENUM_ONLY as it's not used (any more) This patch completely removes CONFIG_PCI_ENUM_ONLY from the PCI code as it is not configured for any board (any more). With this removal, some PCI related files get cleaned up a bit. Additional, dm_pciauto_setup_device() is now static, as it's not referenced from any code outside of this C file. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-01-12 11:03:43 +00:00
dm_pci_write_config32(dev, bar + 4, 0xffffffff);
dm: pci: Use driver model PCI API in auto-config At present we are using legacy functions even in the auto-configuration code used by driver model. Add a new pci_auto.c version which uses the correct API. Create a new pci_internal.h header to hold functions that are used within the PCI subsystem, but are not exported to other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2015-11-29 20:17:49 +00:00
dm_pci_read_config32(dev, bar + 4,
&bar_response_upper);
bar64 = ((u64)bar_response_upper << 32) |
bar_response;
bar_size = ~(bar64 & PCI_BASE_ADDRESS_MEM_MASK)
+ 1;
pci: Remove CONFIG_PCI_ENUM_ONLY as it's not used (any more) This patch completely removes CONFIG_PCI_ENUM_ONLY from the PCI code as it is not configured for any board (any more). With this removal, some PCI related files get cleaned up a bit. Additional, dm_pciauto_setup_device() is now static, as it's not referenced from any code outside of this C file. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-01-12 11:03:43 +00:00
found_mem64 = 1;
dm: pci: Use driver model PCI API in auto-config At present we are using legacy functions even in the auto-configuration code used by driver model. Add a new pci_auto.c version which uses the correct API. Create a new pci_internal.h header to hold functions that are used within the PCI subsystem, but are not exported to other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2015-11-29 20:17:49 +00:00
} else {
bar_size = (u32)(~(bar_response &
PCI_BASE_ADDRESS_MEM_MASK) + 1);
}
pci: Remove CONFIG_PCI_ENUM_ONLY as it's not used (any more) This patch completely removes CONFIG_PCI_ENUM_ONLY from the PCI code as it is not configured for any board (any more). With this removal, some PCI related files get cleaned up a bit. Additional, dm_pciauto_setup_device() is now static, as it's not referenced from any code outside of this C file. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-01-12 11:03:43 +00:00
if (prefetch &&
(bar_response & PCI_BASE_ADDRESS_MEM_PREFETCH))
bar_res = prefetch;
else
bar_res = mem;
dm: pci: Use driver model PCI API in auto-config At present we are using legacy functions even in the auto-configuration code used by driver model. Add a new pci_auto.c version which uses the correct API. Create a new pci_internal.h header to hold functions that are used within the PCI subsystem, but are not exported to other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2015-11-29 20:17:49 +00:00
pci: Mark 64bit Memory BARs as such Just a bit more info to the reader. Signed-off-by: Phil Sutter <phil@nwl.cc> Reviewed-by: Stefan Roese <sr@denx.de>
2021-03-03 00:57:35 +00:00
debug("PCI Autoconfig: BAR %d, %s%s, size=0x%llx, ",
dm: pci: Use driver model PCI API in auto-config At present we are using legacy functions even in the auto-configuration code used by driver model. Add a new pci_auto.c version which uses the correct API. Create a new pci_internal.h header to hold functions that are used within the PCI subsystem, but are not exported to other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2015-11-29 20:17:49 +00:00
bar_nr, bar_res == prefetch ? "Prf" : "Mem",
pci: Mark 64bit Memory BARs as such Just a bit more info to the reader. Signed-off-by: Phil Sutter <phil@nwl.cc> Reviewed-by: Stefan Roese <sr@denx.de>
2021-03-03 00:57:35 +00:00
found_mem64 ? "64" : "",
dm: pci: Use driver model PCI API in auto-config At present we are using legacy functions even in the auto-configuration code used by driver model. Add a new pci_auto.c version which uses the correct API. Create a new pci_internal.h header to hold functions that are used within the PCI subsystem, but are not exported to other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2015-11-29 20:17:49 +00:00
(unsigned long long)bar_size);
}
pci: Remove CONFIG_PCI_ENUM_ONLY as it's not used (any more) This patch completely removes CONFIG_PCI_ENUM_ONLY from the PCI code as it is not configured for any board (any more). With this removal, some PCI related files get cleaned up a bit. Additional, dm_pciauto_setup_device() is now static, as it's not referenced from any code outside of this C file. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-01-12 11:03:43 +00:00
ret = pciauto_region_allocate(bar_res, bar_size,
&bar_value, found_mem64);
if (ret)
printf("PCI: Failed autoconfig bar %x\n", bar);
if (!ret) {
dm: pci: Use driver model PCI API in auto-config At present we are using legacy functions even in the auto-configuration code used by driver model. Add a new pci_auto.c version which uses the correct API. Create a new pci_internal.h header to hold functions that are used within the PCI subsystem, but are not exported to other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2015-11-29 20:17:49 +00:00
/* Write it out and update our limit */
dm_pci_write_config32(dev, bar, (u32)bar_value);
if (found_mem64) {
bar += 4;
#ifdef CONFIG_SYS_PCI_64BIT
dm_pci_write_config32(dev, bar,
(u32)(bar_value >> 32));
#else
/*
* If we are a 64-bit decoder then increment to
* the upper 32 bits of the bar and force it to
* locate in the lower 4GB of memory.
*/
dm_pci_write_config32(dev, bar, 0x00000000);
#endif
}
}
cmdstat |= (bar_response & PCI_BASE_ADDRESS_SPACE) ?
PCI_COMMAND_IO : PCI_COMMAND_MEMORY;
debug("\n");
bar_nr++;
}
pci: Remove CONFIG_PCI_ENUM_ONLY as it's not used (any more) This patch completely removes CONFIG_PCI_ENUM_ONLY from the PCI code as it is not configured for any board (any more). With this removal, some PCI related files get cleaned up a bit. Additional, dm_pciauto_setup_device() is now static, as it's not referenced from any code outside of this C file. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-01-12 11:03:43 +00:00
/* Configure the expansion ROM address */
pci: Skip configuring PCI Rom Address for unsupported header types PCI Rom Address is currently supported only for Normal (0x00) and Bridge (0x01) header types. Fix code accordingly. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Stefan Roese <sr@denx.de>
2021-10-07 12:50:57 +00:00
if (header_type == PCI_HEADER_TYPE_NORMAL ||
header_type == PCI_HEADER_TYPE_BRIDGE) {
pci: Remove CONFIG_PCI_ENUM_ONLY as it's not used (any more) This patch completely removes CONFIG_PCI_ENUM_ONLY from the PCI code as it is not configured for any board (any more). With this removal, some PCI related files get cleaned up a bit. Additional, dm_pciauto_setup_device() is now static, as it's not referenced from any code outside of this C file. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-01-12 11:03:43 +00:00
rom_addr = (header_type == PCI_HEADER_TYPE_NORMAL) ?
PCI_ROM_ADDRESS : PCI_ROM_ADDRESS1;
dm_pci_write_config32(dev, rom_addr, 0xfffffffe);
dm_pci_read_config32(dev, rom_addr, &bar_response);
if (bar_response) {
bar_size = -(bar_response & ~1);
debug("PCI Autoconfig: ROM, size=%#x, ",
(unsigned int)bar_size);
if (pciauto_region_allocate(mem, bar_size, &bar_value,
false) == 0) {
dm_pci_write_config32(dev, rom_addr, bar_value);
dm: pci: Use driver model PCI API in auto-config At present we are using legacy functions even in the auto-configuration code used by driver model. Add a new pci_auto.c version which uses the correct API. Create a new pci_internal.h header to hold functions that are used within the PCI subsystem, but are not exported to other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2015-11-29 20:17:49 +00:00
}
pci: Remove CONFIG_PCI_ENUM_ONLY as it's not used (any more) This patch completely removes CONFIG_PCI_ENUM_ONLY from the PCI code as it is not configured for any board (any more). With this removal, some PCI related files get cleaned up a bit. Additional, dm_pciauto_setup_device() is now static, as it's not referenced from any code outside of this C file. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-01-12 11:03:43 +00:00
cmdstat |= PCI_COMMAND_MEMORY;
debug("\n");
dm: pci: Use driver model PCI API in auto-config At present we are using legacy functions even in the auto-configuration code used by driver model. Add a new pci_auto.c version which uses the correct API. Create a new pci_internal.h header to hold functions that are used within the PCI subsystem, but are not exported to other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2015-11-29 20:17:49 +00:00
}
}
/* PCI_COMMAND_IO must be set for VGA device */
dm_pci_read_config16(dev, PCI_CLASS_DEVICE, &class);
if (class == PCI_CLASS_DISPLAY_VGA)
cmdstat |= PCI_COMMAND_IO;
dm_pci_write_config16(dev, PCI_COMMAND, cmdstat);
dm_pci_write_config8(dev, PCI_CACHE_LINE_SIZE,
global: Move remaining CONFIG_SYS_PCI* to CFG_SYS_PCI* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_PCI and CONFIG_SYS_PCIE namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2022-11-16 18:10:33 +00:00
CFG_SYS_PCI_CACHE_LINE_SIZE);
dm: pci: Use driver model PCI API in auto-config At present we are using legacy functions even in the auto-configuration code used by driver model. Add a new pci_auto.c version which uses the correct API. Create a new pci_internal.h header to hold functions that are used within the PCI subsystem, but are not exported to other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2015-11-29 20:17:49 +00:00
dm_pci_write_config8(dev, PCI_LATENCY_TIMER, 0x80);
}
pci: Work around PCIe link training failures Attempt to handle cases with a downstream port of a PCIe switch where link training never completes and the link continues switching between speeds indefinitely with the data link layer never reaching the active state. It has been observed with a downstream port of the ASMedia ASM2824 Gen 3 switch wired to the upstream port of the Pericom PI7C9X2G304 Gen 2 switch, using a Delock Riser Card PCI Express x1 > 2 x PCIe x1 device, P/N 41433, wired to a SiFive HiFive Unmatched board. In this setup the switches are supposed to negotiate the link speed of preferably 5.0GT/s, falling back to 2.5GT/s. However the link continues oscillating between the two speeds, at the rate of 34-35 times per second, with link training reported repeatedly active ~84% of the time, e.g.: 02:03.0 PCI bridge [0604]: ASMedia Technology Inc. ASM2824 PCIe Gen3 Packet Switch [1b21:2824] (rev 01) (prog-if 00 [Normal decode]) [...] Bus: primary=02, secondary=05, subordinate=05, sec-latency=0 [...] Capabilities: [80] Express (v2) Downstream Port (Slot+), MSI 00 [...] LnkSta: Speed 5GT/s (downgraded), Width x1 (ok) TrErr- Train+ SlotClk+ DLActive- BWMgmt+ ABWMgmt- [...] LnkCtl2: Target Link Speed: 8GT/s, EnterCompliance- SpeedDis+, Selectable De-emphasis: -3.5dB Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS- Compliance De-emphasis: -6dB [...] Forcibly limiting the target link speed to 2.5GT/s with the upstream ASM2824 device makes the two switches communicate correctly however: 02:03.0 PCI bridge [0604]: ASMedia Technology Inc. ASM2824 PCIe Gen3 Packet Switch [1b21:2824] (rev 01) (prog-if 00 [Normal decode]) [...] Bus: primary=02, secondary=05, subordinate=09, sec-latency=0 [...] Capabilities: [80] Express (v2) Downstream Port (Slot+), MSI 00 [...] LnkSta: Speed 2.5GT/s (downgraded), Width x1 (ok) TrErr- Train- SlotClk+ DLActive+ BWMgmt- ABWMgmt- [...] LnkCtl2: Target Link Speed: 2.5GT/s, EnterCompliance- SpeedDis+, Selectable De-emphasis: -3.5dB Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS- Compliance De-emphasis: -6dB [...] and then: 05:00.0 PCI bridge [0604]: Pericom Semiconductor PI7C9X2G304 EL/SL PCIe2 3-Port/4-Lane Packet Switch [12d8:2304] (rev 05) (prog-if 00 [Normal decode]) [...] Bus: primary=05, secondary=06, subordinate=09, sec-latency=0 [...] Capabilities: [c0] Express (v2) Upstream Port, MSI 00 [...] LnkSta: Speed 2.5GT/s (downgraded), Width x1 (downgraded) TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt- [...] LnkCtl2: Target Link Speed: 5GT/s, EnterCompliance- SpeedDis- Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS- Compliance De-emphasis: -6dB [...] Make use of this observation then and attempt to detect the inability to negotiate the link speed automatically, and then handle it by hand. Use the Data Link Layer Link Active status flag as the primary indicator of successful link speed negotiation, but given that the flag is optional by hardware to implement (the ASM2824 does have it though), resort to checking for the mandatory Link Bandwidth Management Status flag showing that the link speed or width has been changed in an attempt to correct unreliable link operation (the ASM2824 does set it too). If these checks indicate that link may not operate correctly, then poll the Data Link Layer Link Active status flag along with the Link Training flag for the duration of 200ms to see if the link has stabilised, that is either that the Data Link Layer Link Active status flag has been set or that Link Training has been inactive during at least the second half of the interval. If that has indicated failure, restrict the target speed to 2.5GT/s, request a link retrain and check again if the link has stabilised. If that does not work either, then restore the original speed setting and claim defeat, otherwise we are done. NB interestingly enough with the ASM2824 vs PI7C9X2G304 configuration referred above asking the ASM2824 to retrain with a higher target link speed once the 2.5GT/s speed has been negotiated makes the two devices successfully negotiate 5.0GT/s. Lifting the 2.5GT/s speed restriction would however prevent our workaround from working with an OS that issues a reset and that is unaware of the problem. This is because the devices would then try to negotiate a higher link speed from scratch and fail, while the sticky property of the Target Link Speed setting will keep the 2.5GT/s speed restriction across a reset. Keep the 2.5GT/s speed restriction then, conservatively, if functional once applied. Signed-off-by: Maciej W. Rozycki <macro@orcam.me.uk> Reviewed-by: Stefan Roese <sr@denx.de>
2021-11-20 23:03:30 +00:00
/*
* Check if the link of a downstream PCIe port operates correctly.
*
* For that check if the optional Data Link Layer Link Active status gets
* on within a 200ms period or failing that wait until the completion of
* that period and check if link training has shown the completed status
* continuously throughout the second half of that period.
*
* Observation with the ASMedia ASM2824 Gen 3 switch indicates it takes
* 11-44ms to indicate the Data Link Layer Link Active status at 2.5GT/s,
* though it may take a couple of link training iterations.
*/
static bool dm_pciauto_exp_link_stable(struct udevice *dev, int pcie_off)
{
u64 loops = 0, trcount = 0, ntrcount = 0, flips = 0;
bool dllla, lnktr, plnktr;
u16 exp_lnksta;
pci_dev_t bdf;
u64 end;
dm_pci_read_config16(dev, pcie_off + PCI_EXP_LNKSTA, &exp_lnksta);
plnktr = !!(exp_lnksta & PCI_EXP_LNKSTA_LT);
end = get_ticks() + usec_to_tick(200000);
do {
dm_pci_read_config16(dev, pcie_off + PCI_EXP_LNKSTA,
&exp_lnksta);
dllla = !!(exp_lnksta & PCI_EXP_LNKSTA_DLLLA);
lnktr = !!(exp_lnksta & PCI_EXP_LNKSTA_LT);
flips += plnktr ^ lnktr;
if (lnktr) {
ntrcount = 0;
trcount++;
} else {
ntrcount++;
}
loops++;
plnktr = lnktr;
} while (!dllla && get_ticks() < end);
bdf = dm_pci_get_bdf(dev);
debug("PCI Autoconfig: %02x.%02x.%02x: Fixup link: DL active: %u; "
"%3llu flips, %6llu loops of which %6llu while training, "
"final %6llu stable\n",
PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf),
(unsigned int)dllla,
(unsigned long long)flips, (unsigned long long)loops,
(unsigned long long)trcount, (unsigned long long)ntrcount);
return dllla || ntrcount >= loops / 2;
}
/*
* Retrain the link of a downstream PCIe port by hand if necessary.
*
* This is needed at least where a downstream port of the ASMedia ASM2824
* Gen 3 switch is wired to the upstream port of the Pericom PI7C9X2G304
* Gen 2 switch, and observed with the Delock Riser Card PCI Express x1 >
* 2 x PCIe x1 device, P/N 41433, plugged into the SiFive HiFive Unmatched
* board.
*
* In such a configuration the switches are supposed to negotiate the link
* speed of preferably 5.0GT/s, falling back to 2.5GT/s. However the link
* continues switching between the two speeds indefinitely and the data
* link layer never reaches the active state, with link training reported
* repeatedly active ~84% of the time. Forcing the target link speed to
* 2.5GT/s with the upstream ASM2824 device makes the two switches talk to
* each other correctly however. And more interestingly retraining with a
* higher target link speed afterwards lets the two successfully negotiate
* 5.0GT/s.
*
* As this can potentially happen with any device and is cheap in the case
* of correctly operating hardware, let's do it for all downstream ports,
* for root complexes, PCIe switches and PCI/PCI-X to PCIe bridges.
*
* First check if automatic link training may have failed to complete, as
* indicated by the optional Data Link Layer Link Active status being off
* and the Link Bandwidth Management Status indicating that hardware has
* changed the link speed or width in an attempt to correct unreliable
* link operation. If this is the case, then check if the link operates
* correctly by seeing whether it is being trained excessively. If it is,
* then conclude the link is broken.
*
* In that case restrict the speed to 2.5GT/s, observing that the Target
* Link Speed field is sticky and therefore the link will stay restricted
* even after a device reset is later made by an OS that is unaware of the
* problem. With the speed restricted request that the link be retrained
* and check again if the link operates correctly. If not, then set the
* Target Link Speed back to the original value.
*
* This requires the presence of the Link Control 2 register, so make sure
* the PCI Express Capability Version is at least 2. Also don't try, for
* obvious reasons, to limit the speed if 2.5GT/s is the only link speed
* supported.
*/
static void dm_pciauto_exp_fixup_link(struct udevice *dev, int pcie_off)
{
u16 exp_lnksta, exp_lnkctl, exp_lnkctl2;
u16 exp_flags, exp_type, exp_version;
u32 exp_lnkcap;
pci_dev_t bdf;
dm_pci_read_config16(dev, pcie_off + PCI_EXP_FLAGS, &exp_flags);
exp_version = exp_flags & PCI_EXP_FLAGS_VERS;
if (exp_version < 2)
return;
exp_type = (exp_flags & PCI_EXP_FLAGS_TYPE) >> 4;
switch (exp_type) {
case PCI_EXP_TYPE_ROOT_PORT:
case PCI_EXP_TYPE_DOWNSTREAM:
case PCI_EXP_TYPE_PCIE_BRIDGE:
break;
default:
return;
}
dm_pci_read_config32(dev, pcie_off + PCI_EXP_LNKCAP, &exp_lnkcap);
if ((exp_lnkcap & PCI_EXP_LNKCAP_SLS) <= PCI_EXP_LNKCAP_SLS_2_5GB)
return;
dm_pci_read_config16(dev, pcie_off + PCI_EXP_LNKSTA, &exp_lnksta);
if ((exp_lnksta & (PCI_EXP_LNKSTA_LBMS | PCI_EXP_LNKSTA_DLLLA)) !=
PCI_EXP_LNKSTA_LBMS)
return;
if (dm_pciauto_exp_link_stable(dev, pcie_off))
return;
bdf = dm_pci_get_bdf(dev);
printf("PCI Autoconfig: %02x.%02x.%02x: "
"Downstream link non-functional\n",
PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf));
printf("PCI Autoconfig: %02x.%02x.%02x: "
"Retrying with speed restricted to 2.5GT/s...\n",
PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf));
dm_pci_read_config16(dev, pcie_off + PCI_EXP_LNKCTL, &exp_lnkctl);
dm_pci_read_config16(dev, pcie_off + PCI_EXP_LNKCTL2, &exp_lnkctl2);
dm_pci_write_config16(dev, pcie_off + PCI_EXP_LNKCTL2,
(exp_lnkctl2 & ~PCI_EXP_LNKCTL2_TLS) |
PCI_EXP_LNKCTL2_TLS_2_5GT);
dm_pci_write_config16(dev, pcie_off + PCI_EXP_LNKCTL,
exp_lnkctl | PCI_EXP_LNKCTL_RL);
if (dm_pciauto_exp_link_stable(dev, pcie_off)) {
printf("PCI Autoconfig: %02x.%02x.%02x: Succeeded!\n",
PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf));
} else {
printf("PCI Autoconfig: %02x.%02x.%02x: Failed!\n",
PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf));
dm_pci_write_config16(dev, pcie_off + PCI_EXP_LNKCTL2,
exp_lnkctl2);
dm_pci_write_config16(dev, pcie_off + PCI_EXP_LNKCTL,
exp_lnkctl | PCI_EXP_LNKCTL_RL);
}
}
dm: pci: Use driver model PCI API in auto-config At present we are using legacy functions even in the auto-configuration code used by driver model. Add a new pci_auto.c version which uses the correct API. Create a new pci_internal.h header to hold functions that are used within the PCI subsystem, but are not exported to other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2015-11-29 20:17:49 +00:00
void dm_pciauto_prescan_setup_bridge(struct udevice *dev, int sub_bus)
{
struct pci_region *pci_mem;
struct pci_region *pci_prefetch;
struct pci_region *pci_io;
u16 cmdstat, prefechable_64;
pci: Fix configuring io/memory base and limit registers of PCI bridges Lower 4 bits of PCI_MEMORY_BASE and PCI_MEMORY_LIMIT registers are reserved and should be zero. So do not set them to non-zero value. Lower 4 bits of PCI_PREF_MEMORY_BASE and PCI_PREF_MEMORY_LIMIT registers contain information if 64-bit memory addressing is supported. So preserve this information when overwriting these registers. Lower 4 bits of PCI_IO_BASE and PCI_IO_LIMIT register contain information if 32-bit io addressing is supported. So preserve this information and do not try to configure 32-bit io addressing (via PCI_IO_BASE_UPPER16 and PCI_IO_LIMIT_UPPER16 registers) when it is unsupported. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Stefan Roese <sr@denx.de>
2021-09-10 11:33:35 +00:00
u8 io_32;
dm: pci: Avoid using pci_bus_to_hose() in the uclass This function is only available for compatibility with old code. Avoid using it in the uclass. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-19 03:19:16 +00:00
struct udevice *ctlr = pci_get_controller(dev);
struct pci_controller *ctlr_hose = dev_get_uclass_priv(ctlr);
pci: Work around PCIe link training failures Attempt to handle cases with a downstream port of a PCIe switch where link training never completes and the link continues switching between speeds indefinitely with the data link layer never reaching the active state. It has been observed with a downstream port of the ASMedia ASM2824 Gen 3 switch wired to the upstream port of the Pericom PI7C9X2G304 Gen 2 switch, using a Delock Riser Card PCI Express x1 > 2 x PCIe x1 device, P/N 41433, wired to a SiFive HiFive Unmatched board. In this setup the switches are supposed to negotiate the link speed of preferably 5.0GT/s, falling back to 2.5GT/s. However the link continues oscillating between the two speeds, at the rate of 34-35 times per second, with link training reported repeatedly active ~84% of the time, e.g.: 02:03.0 PCI bridge [0604]: ASMedia Technology Inc. ASM2824 PCIe Gen3 Packet Switch [1b21:2824] (rev 01) (prog-if 00 [Normal decode]) [...] Bus: primary=02, secondary=05, subordinate=05, sec-latency=0 [...] Capabilities: [80] Express (v2) Downstream Port (Slot+), MSI 00 [...] LnkSta: Speed 5GT/s (downgraded), Width x1 (ok) TrErr- Train+ SlotClk+ DLActive- BWMgmt+ ABWMgmt- [...] LnkCtl2: Target Link Speed: 8GT/s, EnterCompliance- SpeedDis+, Selectable De-emphasis: -3.5dB Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS- Compliance De-emphasis: -6dB [...] Forcibly limiting the target link speed to 2.5GT/s with the upstream ASM2824 device makes the two switches communicate correctly however: 02:03.0 PCI bridge [0604]: ASMedia Technology Inc. ASM2824 PCIe Gen3 Packet Switch [1b21:2824] (rev 01) (prog-if 00 [Normal decode]) [...] Bus: primary=02, secondary=05, subordinate=09, sec-latency=0 [...] Capabilities: [80] Express (v2) Downstream Port (Slot+), MSI 00 [...] LnkSta: Speed 2.5GT/s (downgraded), Width x1 (ok) TrErr- Train- SlotClk+ DLActive+ BWMgmt- ABWMgmt- [...] LnkCtl2: Target Link Speed: 2.5GT/s, EnterCompliance- SpeedDis+, Selectable De-emphasis: -3.5dB Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS- Compliance De-emphasis: -6dB [...] and then: 05:00.0 PCI bridge [0604]: Pericom Semiconductor PI7C9X2G304 EL/SL PCIe2 3-Port/4-Lane Packet Switch [12d8:2304] (rev 05) (prog-if 00 [Normal decode]) [...] Bus: primary=05, secondary=06, subordinate=09, sec-latency=0 [...] Capabilities: [c0] Express (v2) Upstream Port, MSI 00 [...] LnkSta: Speed 2.5GT/s (downgraded), Width x1 (downgraded) TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt- [...] LnkCtl2: Target Link Speed: 5GT/s, EnterCompliance- SpeedDis- Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS- Compliance De-emphasis: -6dB [...] Make use of this observation then and attempt to detect the inability to negotiate the link speed automatically, and then handle it by hand. Use the Data Link Layer Link Active status flag as the primary indicator of successful link speed negotiation, but given that the flag is optional by hardware to implement (the ASM2824 does have it though), resort to checking for the mandatory Link Bandwidth Management Status flag showing that the link speed or width has been changed in an attempt to correct unreliable link operation (the ASM2824 does set it too). If these checks indicate that link may not operate correctly, then poll the Data Link Layer Link Active status flag along with the Link Training flag for the duration of 200ms to see if the link has stabilised, that is either that the Data Link Layer Link Active status flag has been set or that Link Training has been inactive during at least the second half of the interval. If that has indicated failure, restrict the target speed to 2.5GT/s, request a link retrain and check again if the link has stabilised. If that does not work either, then restore the original speed setting and claim defeat, otherwise we are done. NB interestingly enough with the ASM2824 vs PI7C9X2G304 configuration referred above asking the ASM2824 to retrain with a higher target link speed once the 2.5GT/s speed has been negotiated makes the two devices successfully negotiate 5.0GT/s. Lifting the 2.5GT/s speed restriction would however prevent our workaround from working with an OS that issues a reset and that is unaware of the problem. This is because the devices would then try to negotiate a higher link speed from scratch and fail, while the sticky property of the Target Link Speed setting will keep the 2.5GT/s speed restriction across a reset. Keep the 2.5GT/s speed restriction then, conservatively, if functional once applied. Signed-off-by: Maciej W. Rozycki <macro@orcam.me.uk> Reviewed-by: Stefan Roese <sr@denx.de>
2021-11-20 23:03:30 +00:00
int pcie_off;
dm: pci: Use driver model PCI API in auto-config At present we are using legacy functions even in the auto-configuration code used by driver model. Add a new pci_auto.c version which uses the correct API. Create a new pci_internal.h header to hold functions that are used within the PCI subsystem, but are not exported to other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2015-11-29 20:17:49 +00:00
pci_mem = ctlr_hose->pci_mem;
pci_prefetch = ctlr_hose->pci_prefetch;
pci_io = ctlr_hose->pci_io;
dm_pci_read_config16(dev, PCI_COMMAND, &cmdstat);
dm_pci_read_config16(dev, PCI_PREF_MEMORY_BASE, &prefechable_64);
prefechable_64 &= PCI_PREF_RANGE_TYPE_MASK;
pci: Fix register for determining type of IO base address Function dm_pciauto_prescan_setup_bridge() configures base address registers, therefore it should read type of IO from base address registers (and not from limit address registers). Note that base and limit address registers should have same type, so this change is just usage correction and has no functional change on correctly working hardware. Fixes: 8e85f36a8fab ("pci: Fix configuring io/memory base and limit registers of PCI bridges") Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Stefan Roese <sr@denx.de>
2021-11-25 10:30:58 +00:00
dm_pci_read_config8(dev, PCI_IO_BASE, &io_32);
pci: Fix configuring io/memory base and limit registers of PCI bridges Lower 4 bits of PCI_MEMORY_BASE and PCI_MEMORY_LIMIT registers are reserved and should be zero. So do not set them to non-zero value. Lower 4 bits of PCI_PREF_MEMORY_BASE and PCI_PREF_MEMORY_LIMIT registers contain information if 64-bit memory addressing is supported. So preserve this information when overwriting these registers. Lower 4 bits of PCI_IO_BASE and PCI_IO_LIMIT register contain information if 32-bit io addressing is supported. So preserve this information and do not try to configure 32-bit io addressing (via PCI_IO_BASE_UPPER16 and PCI_IO_LIMIT_UPPER16 registers) when it is unsupported. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Stefan Roese <sr@denx.de>
2021-09-10 11:33:35 +00:00
io_32 &= PCI_IO_RANGE_TYPE_MASK;
dm: pci: Use driver model PCI API in auto-config At present we are using legacy functions even in the auto-configuration code used by driver model. Add a new pci_auto.c version which uses the correct API. Create a new pci_internal.h header to hold functions that are used within the PCI subsystem, but are not exported to other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2015-11-29 20:17:49 +00:00
/* Configure bus number registers */
dm_pci_write_config8(dev, PCI_PRIMARY_BUS,
dm: Avoid accessing seq directly At present various drivers etc. access the device's 'seq' member directly. This makes it harder to change the meaning of that member. Change access to go through a function instead. The drivers/i2c/lpc32xx_i2c.c file is left unchanged for now. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-12-17 04:20:07 +00:00
PCI_BUS(dm_pci_get_bdf(dev)) - dev_seq(ctlr));
dm_pci_write_config8(dev, PCI_SECONDARY_BUS, sub_bus - dev_seq(ctlr));
dm: pci: Use driver model PCI API in auto-config At present we are using legacy functions even in the auto-configuration code used by driver model. Add a new pci_auto.c version which uses the correct API. Create a new pci_internal.h header to hold functions that are used within the PCI subsystem, but are not exported to other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2015-11-29 20:17:49 +00:00
dm_pci_write_config8(dev, PCI_SUBORDINATE_BUS, 0xff);
if (pci_mem) {
/* Round memory allocator to 1MB boundary */
pciauto_region_align(pci_mem, 0x100000);
/*
* Set up memory and I/O filter limits, assume 32-bit
* I/O space
*/
dm_pci_write_config16(dev, PCI_MEMORY_BASE,
pci: Fix configuring io/memory base and limit registers of PCI bridges Lower 4 bits of PCI_MEMORY_BASE and PCI_MEMORY_LIMIT registers are reserved and should be zero. So do not set them to non-zero value. Lower 4 bits of PCI_PREF_MEMORY_BASE and PCI_PREF_MEMORY_LIMIT registers contain information if 64-bit memory addressing is supported. So preserve this information when overwriting these registers. Lower 4 bits of PCI_IO_BASE and PCI_IO_LIMIT register contain information if 32-bit io addressing is supported. So preserve this information and do not try to configure 32-bit io addressing (via PCI_IO_BASE_UPPER16 and PCI_IO_LIMIT_UPPER16 registers) when it is unsupported. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Stefan Roese <sr@denx.de>
2021-09-10 11:33:35 +00:00
((pci_mem->bus_lower & 0xfff00000) >> 16) &
PCI_MEMORY_RANGE_MASK);
dm: pci: Use driver model PCI API in auto-config At present we are using legacy functions even in the auto-configuration code used by driver model. Add a new pci_auto.c version which uses the correct API. Create a new pci_internal.h header to hold functions that are used within the PCI subsystem, but are not exported to other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2015-11-29 20:17:49 +00:00
cmdstat |= PCI_COMMAND_MEMORY;
}
if (pci_prefetch) {
/* Round memory allocator to 1MB boundary */
pciauto_region_align(pci_prefetch, 0x100000);
/*
* Set up memory and I/O filter limits, assume 32-bit
* I/O space
*/
dm_pci_write_config16(dev, PCI_PREF_MEMORY_BASE,
pci: Fix configuring io/memory base and limit registers of PCI bridges Lower 4 bits of PCI_MEMORY_BASE and PCI_MEMORY_LIMIT registers are reserved and should be zero. So do not set them to non-zero value. Lower 4 bits of PCI_PREF_MEMORY_BASE and PCI_PREF_MEMORY_LIMIT registers contain information if 64-bit memory addressing is supported. So preserve this information when overwriting these registers. Lower 4 bits of PCI_IO_BASE and PCI_IO_LIMIT register contain information if 32-bit io addressing is supported. So preserve this information and do not try to configure 32-bit io addressing (via PCI_IO_BASE_UPPER16 and PCI_IO_LIMIT_UPPER16 registers) when it is unsupported. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Stefan Roese <sr@denx.de>
2021-09-10 11:33:35 +00:00
(((pci_prefetch->bus_lower & 0xfff00000) >> 16) &
PCI_PREF_RANGE_MASK) | prefechable_64);
dm: pci: Use driver model PCI API in auto-config At present we are using legacy functions even in the auto-configuration code used by driver model. Add a new pci_auto.c version which uses the correct API. Create a new pci_internal.h header to hold functions that are used within the PCI subsystem, but are not exported to other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2015-11-29 20:17:49 +00:00
if (prefechable_64 == PCI_PREF_RANGE_TYPE_64)
#ifdef CONFIG_SYS_PCI_64BIT
dm_pci_write_config32(dev, PCI_PREF_BASE_UPPER32,
pci_prefetch->bus_lower >> 32);
#else
dm_pci_write_config32(dev, PCI_PREF_BASE_UPPER32, 0x0);
#endif
cmdstat |= PCI_COMMAND_MEMORY;
} else {
/* We don't support prefetchable memory for now, so disable */
pci: When disabling pref MEM set all base bits It is common to set all base address bits to one and all limit address bits to zero for disabling address forwarding. Forwarding is disabled when base address is higher than limit address, so this change should not have any effect. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Stefan Roese <sr@denx.de>
2021-11-25 10:34:37 +00:00
dm_pci_write_config16(dev, PCI_PREF_MEMORY_BASE, 0xfff0 |
pci: Fix configuring io/memory base and limit registers of PCI bridges Lower 4 bits of PCI_MEMORY_BASE and PCI_MEMORY_LIMIT registers are reserved and should be zero. So do not set them to non-zero value. Lower 4 bits of PCI_PREF_MEMORY_BASE and PCI_PREF_MEMORY_LIMIT registers contain information if 64-bit memory addressing is supported. So preserve this information when overwriting these registers. Lower 4 bits of PCI_IO_BASE and PCI_IO_LIMIT register contain information if 32-bit io addressing is supported. So preserve this information and do not try to configure 32-bit io addressing (via PCI_IO_BASE_UPPER16 and PCI_IO_LIMIT_UPPER16 registers) when it is unsupported. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Stefan Roese <sr@denx.de>
2021-09-10 11:33:35 +00:00
prefechable_64);
dm_pci_write_config16(dev, PCI_PREF_MEMORY_LIMIT, 0x0 |
prefechable_64);
dm: pci: Use driver model PCI API in auto-config At present we are using legacy functions even in the auto-configuration code used by driver model. Add a new pci_auto.c version which uses the correct API. Create a new pci_internal.h header to hold functions that are used within the PCI subsystem, but are not exported to other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2015-11-29 20:17:49 +00:00
if (prefechable_64 == PCI_PREF_RANGE_TYPE_64) {
dm_pci_write_config16(dev, PCI_PREF_BASE_UPPER32, 0x0);
dm_pci_write_config16(dev, PCI_PREF_LIMIT_UPPER32, 0x0);
}
}
if (pci_io) {
/* Round I/O allocator to 4KB boundary */
pciauto_region_align(pci_io, 0x1000);
dm_pci_write_config8(dev, PCI_IO_BASE,
pci: Fix configuring io/memory base and limit registers of PCI bridges Lower 4 bits of PCI_MEMORY_BASE and PCI_MEMORY_LIMIT registers are reserved and should be zero. So do not set them to non-zero value. Lower 4 bits of PCI_PREF_MEMORY_BASE and PCI_PREF_MEMORY_LIMIT registers contain information if 64-bit memory addressing is supported. So preserve this information when overwriting these registers. Lower 4 bits of PCI_IO_BASE and PCI_IO_LIMIT register contain information if 32-bit io addressing is supported. So preserve this information and do not try to configure 32-bit io addressing (via PCI_IO_BASE_UPPER16 and PCI_IO_LIMIT_UPPER16 registers) when it is unsupported. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Stefan Roese <sr@denx.de>
2021-09-10 11:33:35 +00:00
(((pci_io->bus_lower & 0x0000f000) >> 8) &
PCI_IO_RANGE_MASK) | io_32);
if (io_32 == PCI_IO_RANGE_TYPE_32)
dm_pci_write_config16(dev, PCI_IO_BASE_UPPER16,
dm: pci: Use driver model PCI API in auto-config At present we are using legacy functions even in the auto-configuration code used by driver model. Add a new pci_auto.c version which uses the correct API. Create a new pci_internal.h header to hold functions that are used within the PCI subsystem, but are not exported to other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2015-11-29 20:17:49 +00:00
(pci_io->bus_lower & 0xffff0000) >> 16);
cmdstat |= PCI_COMMAND_IO;
pci: Disable I/O forwarding during autoconfiguration if unsupported If U-Boot does not have any I/O resource for assignment then disable I/O forwarding in PCI bridge autoconfiguration code. Default initial state of PCI bridge IO registers is unspecified, therefore they can be in enabled if U-Boot does not touch them. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Stefan Roese <sr@denx.de>
2021-11-25 10:32:43 +00:00
} else {
/* Disable I/O if unsupported */
dm_pci_write_config8(dev, PCI_IO_BASE, 0xf0 | io_32);
dm_pci_write_config8(dev, PCI_IO_LIMIT, 0x0 | io_32);
if (io_32 == PCI_IO_RANGE_TYPE_32) {
dm_pci_write_config16(dev, PCI_IO_BASE_UPPER16, 0x0);
dm_pci_write_config16(dev, PCI_IO_LIMIT_UPPER16, 0x0);
}
dm: pci: Use driver model PCI API in auto-config At present we are using legacy functions even in the auto-configuration code used by driver model. Add a new pci_auto.c version which uses the correct API. Create a new pci_internal.h header to hold functions that are used within the PCI subsystem, but are not exported to other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2015-11-29 20:17:49 +00:00
}
pci: Work around PCIe link training failures Attempt to handle cases with a downstream port of a PCIe switch where link training never completes and the link continues switching between speeds indefinitely with the data link layer never reaching the active state. It has been observed with a downstream port of the ASMedia ASM2824 Gen 3 switch wired to the upstream port of the Pericom PI7C9X2G304 Gen 2 switch, using a Delock Riser Card PCI Express x1 > 2 x PCIe x1 device, P/N 41433, wired to a SiFive HiFive Unmatched board. In this setup the switches are supposed to negotiate the link speed of preferably 5.0GT/s, falling back to 2.5GT/s. However the link continues oscillating between the two speeds, at the rate of 34-35 times per second, with link training reported repeatedly active ~84% of the time, e.g.: 02:03.0 PCI bridge [0604]: ASMedia Technology Inc. ASM2824 PCIe Gen3 Packet Switch [1b21:2824] (rev 01) (prog-if 00 [Normal decode]) [...] Bus: primary=02, secondary=05, subordinate=05, sec-latency=0 [...] Capabilities: [80] Express (v2) Downstream Port (Slot+), MSI 00 [...] LnkSta: Speed 5GT/s (downgraded), Width x1 (ok) TrErr- Train+ SlotClk+ DLActive- BWMgmt+ ABWMgmt- [...] LnkCtl2: Target Link Speed: 8GT/s, EnterCompliance- SpeedDis+, Selectable De-emphasis: -3.5dB Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS- Compliance De-emphasis: -6dB [...] Forcibly limiting the target link speed to 2.5GT/s with the upstream ASM2824 device makes the two switches communicate correctly however: 02:03.0 PCI bridge [0604]: ASMedia Technology Inc. ASM2824 PCIe Gen3 Packet Switch [1b21:2824] (rev 01) (prog-if 00 [Normal decode]) [...] Bus: primary=02, secondary=05, subordinate=09, sec-latency=0 [...] Capabilities: [80] Express (v2) Downstream Port (Slot+), MSI 00 [...] LnkSta: Speed 2.5GT/s (downgraded), Width x1 (ok) TrErr- Train- SlotClk+ DLActive+ BWMgmt- ABWMgmt- [...] LnkCtl2: Target Link Speed: 2.5GT/s, EnterCompliance- SpeedDis+, Selectable De-emphasis: -3.5dB Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS- Compliance De-emphasis: -6dB [...] and then: 05:00.0 PCI bridge [0604]: Pericom Semiconductor PI7C9X2G304 EL/SL PCIe2 3-Port/4-Lane Packet Switch [12d8:2304] (rev 05) (prog-if 00 [Normal decode]) [...] Bus: primary=05, secondary=06, subordinate=09, sec-latency=0 [...] Capabilities: [c0] Express (v2) Upstream Port, MSI 00 [...] LnkSta: Speed 2.5GT/s (downgraded), Width x1 (downgraded) TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt- [...] LnkCtl2: Target Link Speed: 5GT/s, EnterCompliance- SpeedDis- Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS- Compliance De-emphasis: -6dB [...] Make use of this observation then and attempt to detect the inability to negotiate the link speed automatically, and then handle it by hand. Use the Data Link Layer Link Active status flag as the primary indicator of successful link speed negotiation, but given that the flag is optional by hardware to implement (the ASM2824 does have it though), resort to checking for the mandatory Link Bandwidth Management Status flag showing that the link speed or width has been changed in an attempt to correct unreliable link operation (the ASM2824 does set it too). If these checks indicate that link may not operate correctly, then poll the Data Link Layer Link Active status flag along with the Link Training flag for the duration of 200ms to see if the link has stabilised, that is either that the Data Link Layer Link Active status flag has been set or that Link Training has been inactive during at least the second half of the interval. If that has indicated failure, restrict the target speed to 2.5GT/s, request a link retrain and check again if the link has stabilised. If that does not work either, then restore the original speed setting and claim defeat, otherwise we are done. NB interestingly enough with the ASM2824 vs PI7C9X2G304 configuration referred above asking the ASM2824 to retrain with a higher target link speed once the 2.5GT/s speed has been negotiated makes the two devices successfully negotiate 5.0GT/s. Lifting the 2.5GT/s speed restriction would however prevent our workaround from working with an OS that issues a reset and that is unaware of the problem. This is because the devices would then try to negotiate a higher link speed from scratch and fail, while the sticky property of the Target Link Speed setting will keep the 2.5GT/s speed restriction across a reset. Keep the 2.5GT/s speed restriction then, conservatively, if functional once applied. Signed-off-by: Maciej W. Rozycki <macro@orcam.me.uk> Reviewed-by: Stefan Roese <sr@denx.de>
2021-11-20 23:03:30 +00:00
/* For PCIe devices see if we need to retrain the link by hand */
pcie_off = dm_pci_find_capability(dev, PCI_CAP_ID_EXP);
if (pcie_off)
dm_pciauto_exp_fixup_link(dev, pcie_off);
dm: pci: Use driver model PCI API in auto-config At present we are using legacy functions even in the auto-configuration code used by driver model. Add a new pci_auto.c version which uses the correct API. Create a new pci_internal.h header to hold functions that are used within the PCI subsystem, but are not exported to other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2015-11-29 20:17:49 +00:00
/* Enable memory and I/O accesses, enable bus master */
dm_pci_write_config16(dev, PCI_COMMAND, cmdstat | PCI_COMMAND_MASTER);
}
void dm_pciauto_postscan_setup_bridge(struct udevice *dev, int sub_bus)
{
struct pci_region *pci_mem;
struct pci_region *pci_prefetch;
struct pci_region *pci_io;
dm: pci: Avoid using pci_bus_to_hose() in the uclass This function is only available for compatibility with old code. Avoid using it in the uclass. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-19 03:19:16 +00:00
struct udevice *ctlr = pci_get_controller(dev);
struct pci_controller *ctlr_hose = dev_get_uclass_priv(ctlr);
dm: pci: Use driver model PCI API in auto-config At present we are using legacy functions even in the auto-configuration code used by driver model. Add a new pci_auto.c version which uses the correct API. Create a new pci_internal.h header to hold functions that are used within the PCI subsystem, but are not exported to other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2015-11-29 20:17:49 +00:00
pci_mem = ctlr_hose->pci_mem;
pci_prefetch = ctlr_hose->pci_prefetch;
pci_io = ctlr_hose->pci_io;
/* Configure bus number registers */
dm: Avoid accessing seq directly At present various drivers etc. access the device's 'seq' member directly. This makes it harder to change the meaning of that member. Change access to go through a function instead. The drivers/i2c/lpc32xx_i2c.c file is left unchanged for now. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-12-17 04:20:07 +00:00
dm_pci_write_config8(dev, PCI_SUBORDINATE_BUS, sub_bus - dev_seq(ctlr));
dm: pci: Use driver model PCI API in auto-config At present we are using legacy functions even in the auto-configuration code used by driver model. Add a new pci_auto.c version which uses the correct API. Create a new pci_internal.h header to hold functions that are used within the PCI subsystem, but are not exported to other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2015-11-29 20:17:49 +00:00
if (pci_mem) {
/* Round memory allocator to 1MB boundary */
pciauto_region_align(pci_mem, 0x100000);
dm_pci_write_config16(dev, PCI_MEMORY_LIMIT,
pci: Fix configuring io/memory base and limit registers of PCI bridges Lower 4 bits of PCI_MEMORY_BASE and PCI_MEMORY_LIMIT registers are reserved and should be zero. So do not set them to non-zero value. Lower 4 bits of PCI_PREF_MEMORY_BASE and PCI_PREF_MEMORY_LIMIT registers contain information if 64-bit memory addressing is supported. So preserve this information when overwriting these registers. Lower 4 bits of PCI_IO_BASE and PCI_IO_LIMIT register contain information if 32-bit io addressing is supported. So preserve this information and do not try to configure 32-bit io addressing (via PCI_IO_BASE_UPPER16 and PCI_IO_LIMIT_UPPER16 registers) when it is unsupported. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Stefan Roese <sr@denx.de>
2021-09-10 11:33:35 +00:00
((pci_mem->bus_lower - 1) >> 16) &
PCI_MEMORY_RANGE_MASK);
dm: pci: Use driver model PCI API in auto-config At present we are using legacy functions even in the auto-configuration code used by driver model. Add a new pci_auto.c version which uses the correct API. Create a new pci_internal.h header to hold functions that are used within the PCI subsystem, but are not exported to other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2015-11-29 20:17:49 +00:00
}
if (pci_prefetch) {
u16 prefechable_64;
dm_pci_read_config16(dev, PCI_PREF_MEMORY_LIMIT,
&prefechable_64);
prefechable_64 &= PCI_PREF_RANGE_TYPE_MASK;
/* Round memory allocator to 1MB boundary */
pciauto_region_align(pci_prefetch, 0x100000);
dm_pci_write_config16(dev, PCI_PREF_MEMORY_LIMIT,
pci: Fix configuring io/memory base and limit registers of PCI bridges Lower 4 bits of PCI_MEMORY_BASE and PCI_MEMORY_LIMIT registers are reserved and should be zero. So do not set them to non-zero value. Lower 4 bits of PCI_PREF_MEMORY_BASE and PCI_PREF_MEMORY_LIMIT registers contain information if 64-bit memory addressing is supported. So preserve this information when overwriting these registers. Lower 4 bits of PCI_IO_BASE and PCI_IO_LIMIT register contain information if 32-bit io addressing is supported. So preserve this information and do not try to configure 32-bit io addressing (via PCI_IO_BASE_UPPER16 and PCI_IO_LIMIT_UPPER16 registers) when it is unsupported. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Stefan Roese <sr@denx.de>
2021-09-10 11:33:35 +00:00
(((pci_prefetch->bus_lower - 1) >> 16) &
PCI_PREF_RANGE_MASK) | prefechable_64);
dm: pci: Use driver model PCI API in auto-config At present we are using legacy functions even in the auto-configuration code used by driver model. Add a new pci_auto.c version which uses the correct API. Create a new pci_internal.h header to hold functions that are used within the PCI subsystem, but are not exported to other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2015-11-29 20:17:49 +00:00
if (prefechable_64 == PCI_PREF_RANGE_TYPE_64)
#ifdef CONFIG_SYS_PCI_64BIT
dm_pci_write_config32(dev, PCI_PREF_LIMIT_UPPER32,
(pci_prefetch->bus_lower - 1) >> 32);
#else
dm_pci_write_config32(dev, PCI_PREF_LIMIT_UPPER32, 0x0);
#endif
}
if (pci_io) {
pci: Fix configuring io/memory base and limit registers of PCI bridges Lower 4 bits of PCI_MEMORY_BASE and PCI_MEMORY_LIMIT registers are reserved and should be zero. So do not set them to non-zero value. Lower 4 bits of PCI_PREF_MEMORY_BASE and PCI_PREF_MEMORY_LIMIT registers contain information if 64-bit memory addressing is supported. So preserve this information when overwriting these registers. Lower 4 bits of PCI_IO_BASE and PCI_IO_LIMIT register contain information if 32-bit io addressing is supported. So preserve this information and do not try to configure 32-bit io addressing (via PCI_IO_BASE_UPPER16 and PCI_IO_LIMIT_UPPER16 registers) when it is unsupported. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Stefan Roese <sr@denx.de>
2021-09-10 11:33:35 +00:00
u8 io_32;
dm_pci_read_config8(dev, PCI_IO_LIMIT,
&io_32);
io_32 &= PCI_IO_RANGE_TYPE_MASK;
dm: pci: Use driver model PCI API in auto-config At present we are using legacy functions even in the auto-configuration code used by driver model. Add a new pci_auto.c version which uses the correct API. Create a new pci_internal.h header to hold functions that are used within the PCI subsystem, but are not exported to other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2015-11-29 20:17:49 +00:00
/* Round I/O allocator to 4KB boundary */
pciauto_region_align(pci_io, 0x1000);
dm_pci_write_config8(dev, PCI_IO_LIMIT,
pci: Fix configuring io/memory base and limit registers of PCI bridges Lower 4 bits of PCI_MEMORY_BASE and PCI_MEMORY_LIMIT registers are reserved and should be zero. So do not set them to non-zero value. Lower 4 bits of PCI_PREF_MEMORY_BASE and PCI_PREF_MEMORY_LIMIT registers contain information if 64-bit memory addressing is supported. So preserve this information when overwriting these registers. Lower 4 bits of PCI_IO_BASE and PCI_IO_LIMIT register contain information if 32-bit io addressing is supported. So preserve this information and do not try to configure 32-bit io addressing (via PCI_IO_BASE_UPPER16 and PCI_IO_LIMIT_UPPER16 registers) when it is unsupported. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Stefan Roese <sr@denx.de>
2021-09-10 11:33:35 +00:00
((((pci_io->bus_lower - 1) & 0x0000f000) >> 8) &
PCI_IO_RANGE_MASK) | io_32);
if (io_32 == PCI_IO_RANGE_TYPE_32)
dm_pci_write_config16(dev, PCI_IO_LIMIT_UPPER16,
dm: pci: Use driver model PCI API in auto-config At present we are using legacy functions even in the auto-configuration code used by driver model. Add a new pci_auto.c version which uses the correct API. Create a new pci_internal.h header to hold functions that are used within the PCI subsystem, but are not exported to other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2015-11-29 20:17:49 +00:00
((pci_io->bus_lower - 1) & 0xffff0000) >> 16);
}
}
/*
* HJF: Changed this to return int. I think this is required
* to get the correct result when scanning bridges
*/
int dm_pciauto_config_device(struct udevice *dev)
{
struct pci_region *pci_mem;
struct pci_region *pci_prefetch;
struct pci_region *pci_io;
unsigned int sub_bus = PCI_BUS(dm_pci_get_bdf(dev));
unsigned short class;
dm: pci: Avoid using pci_bus_to_hose() in the uclass This function is only available for compatibility with old code. Avoid using it in the uclass. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-19 03:19:16 +00:00
struct udevice *ctlr = pci_get_controller(dev);
struct pci_controller *ctlr_hose = dev_get_uclass_priv(ctlr);
pci: Update to use new sequence numbers Now that we know the sequence number at bind time, there is no need for special-case code in dm_pci_hose_probe_bus(). Note: the PCI_CAP_ID_EA code may need a look, but there are no test failures so I have left it as is. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-12-17 04:20:18 +00:00
int ret;
dm: pci: Use driver model PCI API in auto-config At present we are using legacy functions even in the auto-configuration code used by driver model. Add a new pci_auto.c version which uses the correct API. Create a new pci_internal.h header to hold functions that are used within the PCI subsystem, but are not exported to other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2015-11-29 20:17:49 +00:00
pci_mem = ctlr_hose->pci_mem;
pci_prefetch = ctlr_hose->pci_prefetch;
pci_io = ctlr_hose->pci_io;
dm_pci_read_config16(dev, PCI_CLASS_DEVICE, &class);
switch (class) {
case PCI_CLASS_BRIDGE_PCI:
debug("PCI Autoconfig: Found P2P bridge, device %d\n",
PCI_DEV(dm_pci_get_bdf(dev)));
pci: Fix configuring BARs Number of BARs is defined by header type, not by class code. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Stefan Roese <sr@denx.de>
2021-10-07 12:50:59 +00:00
dm_pciauto_setup_device(dev, pci_mem, pci_prefetch, pci_io);
dm: pci: Use driver model PCI API in auto-config At present we are using legacy functions even in the auto-configuration code used by driver model. Add a new pci_auto.c version which uses the correct API. Create a new pci_internal.h header to hold functions that are used within the PCI subsystem, but are not exported to other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2015-11-29 20:17:49 +00:00
pci: Update to use new sequence numbers Now that we know the sequence number at bind time, there is no need for special-case code in dm_pci_hose_probe_bus(). Note: the PCI_CAP_ID_EA code may need a look, but there are no test failures so I have left it as is. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-12-17 04:20:18 +00:00
ret = dm_pci_hose_probe_bus(dev);
if (ret < 0)
return log_msg_ret("probe", ret);
sub_bus = ret;
dm: pci: Use driver model PCI API in auto-config At present we are using legacy functions even in the auto-configuration code used by driver model. Add a new pci_auto.c version which uses the correct API. Create a new pci_internal.h header to hold functions that are used within the PCI subsystem, but are not exported to other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2015-11-29 20:17:49 +00:00
break;
case PCI_CLASS_BRIDGE_CARDBUS:
/*
* just do a minimal setup of the bridge,
* let the OS take care of the rest
*/
pci: Fix configuring BARs Number of BARs is defined by header type, not by class code. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Stefan Roese <sr@denx.de>
2021-10-07 12:50:59 +00:00
dm_pciauto_setup_device(dev, pci_mem, pci_prefetch, pci_io);
dm: pci: Use driver model PCI API in auto-config At present we are using legacy functions even in the auto-configuration code used by driver model. Add a new pci_auto.c version which uses the correct API. Create a new pci_internal.h header to hold functions that are used within the PCI subsystem, but are not exported to other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2015-11-29 20:17:49 +00:00
debug("PCI Autoconfig: Found P2CardBus bridge, device %d\n",
PCI_DEV(dm_pci_get_bdf(dev)));
break;
#if defined(CONFIG_PCIAUTO_SKIP_HOST_BRIDGE)
case PCI_CLASS_BRIDGE_OTHER:
debug("PCI Autoconfig: Skipping bridge device %d\n",
PCI_DEV(dm_pci_get_bdf(dev)));
break;
#endif
ppc: Remove caddy2 / vme8349 boards These boards have not been converted to CONFIG_DM_PCI by the deadline and is also missing conversion to CONFIG_DM. Remove them. Cc: Reinhard Arlt <reinhard.arlt@esd-electronics.com> Signed-off-by: Tom Rini <trini@konsulko.com>
2021-05-15 01:34:17 +00:00
#if defined(CONFIG_ARCH_MPC834X)
dm: pci: Use driver model PCI API in auto-config At present we are using legacy functions even in the auto-configuration code used by driver model. Add a new pci_auto.c version which uses the correct API. Create a new pci_internal.h header to hold functions that are used within the PCI subsystem, but are not exported to other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2015-11-29 20:17:49 +00:00
case PCI_CLASS_BRIDGE_OTHER:
/*
* The host/PCI bridge 1 seems broken in 8349 - it presents
* itself as 'PCI_CLASS_BRIDGE_OTHER' and appears as an _agent_
* device claiming resources io/mem/irq.. we only allow for
* the PIMMR window to be allocated (BAR0 - 1MB size)
*/
debug("PCI Autoconfig: Broken bridge found, only minimal config\n");
dm_pciauto_setup_device(dev, 0, hose->pci_mem,
pci: Remove CONFIG_PCI_ENUM_ONLY as it's not used (any more) This patch completely removes CONFIG_PCI_ENUM_ONLY from the PCI code as it is not configured for any board (any more). With this removal, some PCI related files get cleaned up a bit. Additional, dm_pciauto_setup_device() is now static, as it's not referenced from any code outside of this C file. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-01-12 11:03:43 +00:00
hose->pci_prefetch, hose->pci_io);
dm: pci: Use driver model PCI API in auto-config At present we are using legacy functions even in the auto-configuration code used by driver model. Add a new pci_auto.c version which uses the correct API. Create a new pci_internal.h header to hold functions that are used within the PCI subsystem, but are not exported to other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2015-11-29 20:17:49 +00:00
break;
#endif
default:
pci: Fix configuring BARs Number of BARs is defined by header type, not by class code. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Stefan Roese <sr@denx.de>
2021-10-07 12:50:59 +00:00
dm_pciauto_setup_device(dev, pci_mem, pci_prefetch, pci_io);
dm: pci: Use driver model PCI API in auto-config At present we are using legacy functions even in the auto-configuration code used by driver model. Add a new pci_auto.c version which uses the correct API. Create a new pci_internal.h header to hold functions that are used within the PCI subsystem, but are not exported to other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2015-11-29 20:17:49 +00:00
break;
}
return sub_bus;
}
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