mirror of
https://github.com/AsahiLinux/u-boot
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62 lines
1.7 KiB
C
62 lines
1.7 KiB
C
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* U-Boot specific helpers for TI K3 AM65x NAVSS Ring accelerator
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* Manager (RA) subsystem driver
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*
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* Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com
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*/
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struct k3_nav_ring_cfg_regs {
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u32 resv_64[16];
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u32 ba_lo; /* Ring Base Address Lo Register */
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u32 ba_hi; /* Ring Base Address Hi Register */
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u32 size; /* Ring Size Register */
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u32 event; /* Ring Event Register */
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u32 orderid; /* Ring OrderID Register */
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};
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#define KNAV_RINGACC_CFG_REGS_STEP 0x100
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#define KNAV_RINGACC_CFG_RING_BA_HI_ADDR_HI_MASK GENMASK(15, 0)
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#define KNAV_RINGACC_CFG_RING_SIZE_QMODE_MASK GENMASK(31, 30)
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#define KNAV_RINGACC_CFG_RING_SIZE_QMODE_SHIFT (30)
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#define KNAV_RINGACC_CFG_RING_SIZE_ELSIZE_MASK GENMASK(26, 24)
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#define KNAV_RINGACC_CFG_RING_SIZE_ELSIZE_SHIFT (24)
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static void k3_ringacc_ring_reset_raw(struct k3_nav_ring *ring)
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{
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writel(0, &ring->cfg->size);
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}
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static void k3_ringacc_ring_reconfig_qmode_raw(struct k3_nav_ring *ring, enum k3_nav_ring_mode mode)
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{
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u32 val;
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val = readl(&ring->cfg->size);
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val &= KNAV_RINGACC_CFG_RING_SIZE_QMODE_MASK;
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val |= mode << KNAV_RINGACC_CFG_RING_SIZE_QMODE_SHIFT;
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writel(val, &ring->cfg->size);
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}
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static void k3_ringacc_ring_free_raw(struct k3_nav_ring *ring)
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{
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writel(0, &ring->cfg->ba_hi);
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writel(0, &ring->cfg->ba_lo);
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writel(0, &ring->cfg->size);
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}
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static void k3_nav_ringacc_ring_cfg_raw(struct k3_nav_ring *ring)
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{
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u32 val;
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writel(lower_32_bits(ring->ring_mem_dma), &ring->cfg->ba_lo);
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writel(upper_32_bits(ring->ring_mem_dma), &ring->cfg->ba_hi);
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val = ring->mode << KNAV_RINGACC_CFG_RING_SIZE_QMODE_SHIFT |
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ring->elm_size << KNAV_RINGACC_CFG_RING_SIZE_ELSIZE_SHIFT |
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ring->size;
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writel(val, &ring->cfg->size);
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}
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