mirror of
https://github.com/AsahiLinux/u-boot
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108 lines
2.5 KiB
C
108 lines
2.5 KiB
C
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/*
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* Copyright 2016 Rockchip Electronics Co., Ltd
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <libfdt.h>
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#include "../gadget/dwc2_udc_otg_priv.h"
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DECLARE_GLOBAL_DATA_PTR;
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#define BIT_WRITEABLE_SHIFT 16
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struct usb2phy_reg {
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unsigned int offset;
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unsigned int bitend;
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unsigned int bitstart;
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unsigned int disable;
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unsigned int enable;
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};
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/**
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* struct rockchip_usb2_phy_cfg: usb-phy port configuration
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* @port_reset: usb otg per-port reset register
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* @soft_con: software control usb otg register
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* @suspend: phy suspend register
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*/
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struct rockchip_usb2_phy_cfg {
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struct usb2phy_reg port_reset;
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struct usb2phy_reg soft_con;
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struct usb2phy_reg suspend;
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};
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struct rockchip_usb2_phy_dt_id {
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char compatible[128];
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const void *data;
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};
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static const struct rockchip_usb2_phy_cfg rk3288_pdata = {
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.port_reset = {0x00, 12, 12, 0, 1},
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.soft_con = {0x08, 2, 2, 0, 1},
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.suspend = {0x0c, 5, 0, 0x01, 0x2A},
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};
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static struct rockchip_usb2_phy_dt_id rockchip_usb2_phy_dt_ids[] = {
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{ .compatible = "rockchip,rk3288-usb-phy", .data = &rk3288_pdata },
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{}
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};
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static void property_enable(struct dwc2_plat_otg_data *pdata,
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const struct usb2phy_reg *reg, bool en)
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{
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unsigned int val, mask, tmp;
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tmp = en ? reg->enable : reg->disable;
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mask = GENMASK(reg->bitend, reg->bitstart);
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val = (tmp << reg->bitstart) | (mask << BIT_WRITEABLE_SHIFT);
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writel(val, pdata->regs_phy + reg->offset);
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}
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void otg_phy_init(struct dwc2_udc *dev)
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{
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struct dwc2_plat_otg_data *pdata = dev->pdata;
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struct rockchip_usb2_phy_cfg *phy_cfg = NULL;
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struct rockchip_usb2_phy_dt_id *of_id;
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int i;
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for (i = 0; i < ARRAY_SIZE(rockchip_usb2_phy_dt_ids); i++) {
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of_id = &rockchip_usb2_phy_dt_ids[i];
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if (fdt_node_check_compatible(gd->fdt_blob, pdata->phy_of_node,
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of_id->compatible) == 0) {
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phy_cfg = (struct rockchip_usb2_phy_cfg *)of_id->data;
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break;
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}
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}
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if (!phy_cfg) {
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debug("Can't find device platform data\n");
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hang();
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return;
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}
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pdata->priv = phy_cfg;
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/* disable software control */
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property_enable(pdata, &phy_cfg->soft_con, false);
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/* reset otg port */
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property_enable(pdata, &phy_cfg->port_reset, true);
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mdelay(1);
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property_enable(pdata, &phy_cfg->port_reset, false);
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udelay(1);
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}
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void otg_phy_off(struct dwc2_udc *dev)
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{
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struct dwc2_plat_otg_data *pdata = dev->pdata;
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struct rockchip_usb2_phy_cfg *phy_cfg = pdata->priv;
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/* enable software control */
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property_enable(pdata, &phy_cfg->soft_con, true);
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/* enter suspend */
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property_enable(pdata, &phy_cfg->suspend, true);
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}
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