mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-23 11:33:32 +00:00
430 lines
12 KiB
Text
430 lines
12 KiB
Text
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/*
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* Copyright (C) 2016 Freescale Semiconductor, Inc.
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* Copyright 2017 NXP
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include "fsl-imx8-ca53.dtsi"
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#include <dt-bindings/clock/imx8mq-clock.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/input/input.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/pinctrl/pins-imx8mq.h>
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#include <dt-bindings/thermal/thermal.h>
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/ {
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compatible = "fsl,imx8mq";
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interrupt-parent = <&gpc>;
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#address-cells = <2>;
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#size-cells = <2>;
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aliases {
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ethernet0 = &fec1;
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mmc0 = &usdhc1;
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mmc1 = &usdhc2;
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gpio0 = &gpio1;
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gpio1 = &gpio2;
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gpio2 = &gpio3;
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gpio3 = &gpio4;
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gpio4 = &gpio5;
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i2c0 = &i2c1;
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i2c1 = &i2c2;
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i2c2 = &i2c3;
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i2c3 = &i2c4;
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};
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memory@40000000 {
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device_type = "memory";
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reg = <0x00000000 0x40000000 0 0xc0000000>;
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};
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gic: interrupt-controller@38800000 {
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compatible = "arm,gic-v3";
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reg = <0x0 0x38800000 0 0x10000>, /* GIC Dist */
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<0x0 0x38880000 0 0xC0000>; /* GICR (RD_base + SGI_base) */
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#interrupt-cells = <3>;
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interrupt-controller;
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interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-parent = <&gic>;
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) |
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IRQ_TYPE_LEVEL_LOW)>, /* Physical Secure */
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<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) |
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IRQ_TYPE_LEVEL_LOW)>, /* Physical Non-Secure */
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<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) |
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IRQ_TYPE_LEVEL_LOW)>, /* Virtual */
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<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) |
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IRQ_TYPE_LEVEL_LOW)>; /* Hypervisor */
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clock-frequency = <8333333>;
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interrupt-parent = <&gic>;
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};
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power: power-controller {
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compatible = "fsl,imx8mq-pm-domain";
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num-domains = <11>;
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#power-domain-cells = <1>;
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};
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pwm2: pwm@30670000 {
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compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm";
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reg = <0x0 0x30670000 0x0 0x10000>;
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interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk IMX8MQ_CLK_PWM2_ROOT>,
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<&clk IMX8MQ_CLK_PWM2_ROOT>;
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clock-names = "ipg", "per";
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#pwm-cells = <2>;
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status = "disabled";
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};
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gpio1: gpio@30200000 {
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compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
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reg = <0x0 0x30200000 0x0 0x10000>;
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interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpio2: gpio@30210000 {
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compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
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reg = <0x0 0x30210000 0x0 0x10000>;
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interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpio3: gpio@30220000 {
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compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
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reg = <0x0 0x30220000 0x0 0x10000>;
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interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpio4: gpio@30230000 {
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compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
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reg = <0x0 0x30230000 0x0 0x10000>;
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interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpio5: gpio@30240000 {
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compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
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reg = <0x0 0x30240000 0x0 0x10000>;
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interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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tmu: tmu@30260000 {
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compatible = "fsl,imx8mq-tmu";
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reg = <0x0 0x30260000 0x0 0x10000>;
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interrupt = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
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little-endian;
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u-boot,dm-pre-reloc;
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fsl,tmu-range = <0xa0000 0x90026 0x8004a 0x1006a>;
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fsl,tmu-calibration = <0x00000000 0x00000020
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0x00000001 0x00000028
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0x00000002 0x00000030
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0x00000003 0x00000038
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0x00000004 0x00000040
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0x00000005 0x00000048
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0x00000006 0x00000050
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0x00000007 0x00000058
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0x00000008 0x00000060
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0x00000009 0x00000068
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0x0000000a 0x00000070
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0x0000000b 0x00000077
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0x00010000 0x00000057
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0x00010001 0x0000005b
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0x00010002 0x0000005f
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0x00010003 0x00000063
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0x00010004 0x00000067
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0x00010005 0x0000006b
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0x00010006 0x0000006f
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0x00010007 0x00000073
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0x00010008 0x00000077
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0x00010009 0x0000007b
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0x0001000a 0x0000007f
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0x00020000 0x00000002
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0x00020001 0x0000000e
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0x00020002 0x0000001a
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0x00020003 0x00000026
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0x00020004 0x00000032
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0x00020005 0x0000003e
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0x00020006 0x0000004a
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0x00020007 0x00000056
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0x00020008 0x00000062
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0x00030000 0x00000000
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0x00030001 0x00000008
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0x00030002 0x00000010
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0x00030003 0x00000018
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0x00030004 0x00000020
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0x00030005 0x00000028
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0x00030006 0x00000030
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0x00030007 0x00000038>;
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#thermal-sensor-cells = <0>;
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};
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thermal-zones {
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/* cpu thermal */
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cpu-thermal {
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polling-delay-passive = <250>;
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polling-delay = <2000>;
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thermal-sensors = <&tmu>;
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trips {
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cpu_alert0: trip0 {
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temperature = <85000>;
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hysteresis = <2000>;
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type = "passive";
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};
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cpu_crit0: trip1 {
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temperature = <125000>;
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hysteresis = <2000>;
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type = "critical";
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};
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};
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cooling-maps {
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map0 {
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trip = <&cpu_alert0>;
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cooling-device =
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<&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
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};
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};
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};
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};
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lcdif: lcdif@30320000 {
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compatible = "fsl,imx8mq-lcdif", "fsl,imx28-lcdif";
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reg = <0x0 0x30320000 0x0 0x10000>;
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clocks = <&clk IMX8MQ_CLK_LCDIF_PIXEL_DIV>,
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<&clk IMX8MQ_CLK_DUMMY>,
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<&clk IMX8MQ_CLK_DUMMY>;
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clock-names = "pix", "axi", "disp_axi";
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assigned-clocks = <&clk IMX8MQ_CLK_LCDIF_PIXEL_SRC>;
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assigned-clock-parents = <&clk IMX8MQ_VIDEO_PLL1_OUT>;
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assigned-clock-rate = <594000000>;
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interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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iomuxc: iomuxc@30330000 {
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compatible = "fsl,imx8mq-iomuxc";
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reg = <0x0 0x30330000 0x0 0x10000>;
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};
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gpr: iomuxc-gpr@30340000 {
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compatible = "fsl,imx8mq-iomuxc-gpr", "fsl,imx7d-iomuxc-gpr", "syscon";
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reg = <0x0 0x30340000 0x0 0x10000>;
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};
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ocotp: ocotp-ctrl@30350000 {
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compatible = "fsl,imx8mq-ocotp", "fsl,imx7d-ocotp", "syscon";
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reg = <0x0 0x30350000 0x0 0x10000>;
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};
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anatop: anatop@30360000 {
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compatible = "fsl,imx8mq-anatop", "fsl,imx6q-anatop",
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"syscon", "simple-bus";
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reg = <0x0 0x30360000 0x0 0x10000>;
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interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
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};
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clk: ccm@30380000 {
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compatible = "fsl,imx8mq-ccm";
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reg = <0x0 0x30380000 0x0 0x10000>;
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interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
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#clock-cells = <1>;
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};
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gpc: gpc@303a0000 {
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compatible = "fsl,imx8mq-gpc", "fsl,imx7d-gpc", "syscon";
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reg = <0x0 0x303a0000 0x0 0x10000>;
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interrupt-controller;
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interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
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#interrupt-cells = <3>;
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interrupt-parent = <&gic>;
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};
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usdhc1: usdhc@30b40000 {
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compatible = "fsl,imx8mq-usdhc", "fsl,imx7d-usdhc";
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reg = <0x0 0x30b40000 0x0 0x10000>;
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interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk IMX8MQ_CLK_DUMMY>,
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<&clk IMX8MQ_CLK_NAND_USDHC_BUS_DIV>,
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<&clk IMX8MQ_CLK_USDHC1_ROOT>;
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clock-names = "ipg", "ahb", "per";
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assigned-clocks = <&clk IMX8MQ_CLK_USDHC1_DIV>;
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assigned-clock-rates = <400000000>;
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fsl,tuning-start-tap = <20>;
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fsl,tuning-step= <2>;
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bus-width = <4>;
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status = "disabled";
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};
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usdhc2: usdhc@30b50000 {
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compatible = "fsl,imx8mq-usdhc", "fsl,imx7d-usdhc";
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reg = <0x0 0x30b50000 0x0 0x10000>;
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interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk IMX8MQ_CLK_DUMMY>,
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<&clk IMX8MQ_CLK_NAND_USDHC_BUS_DIV>,
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<&clk IMX8MQ_CLK_USDHC2_ROOT>;
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clock-names = "ipg", "ahb", "per";
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fsl,tuning-start-tap = <20>;
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fsl,tuning-step= <2>;
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bus-width = <4>;
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status = "disabled";
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};
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fec1: ethernet@30be0000 {
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compatible = "fsl,imx8mq-fec", "fsl,imx6sx-fec";
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reg = <0x0 0x30be0000 0x0 0x10000>;
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interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk IMX8MQ_CLK_ENET1_ROOT>,
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<&clk IMX8MQ_CLK_ENET1_ROOT>,
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<&clk IMX8MQ_CLK_ENET_TIMER_DIV>,
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<&clk IMX8MQ_CLK_ENET_REF_DIV>,
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<&clk IMX8MQ_CLK_ENET_PHY_REF_DIV>;
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clock-names = "ipg", "ahb", "ptp",
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"enet_clk_ref", "enet_out";
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assigned-clocks = <&clk IMX8MQ_CLK_ENET_AXI_SRC>,
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<&clk IMX8MQ_CLK_ENET_TIMER_SRC>,
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<&clk IMX8MQ_CLK_ENET_REF_SRC>,
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<&clk IMX8MQ_CLK_ENET_TIMER_DIV>;
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assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_266M>,
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<&clk IMX8MQ_SYS2_PLL_100M>,
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<&clk IMX8MQ_SYS2_PLL_125M>;
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assigned-clock-rates = <0>, <0>, <125000000>, <100000000>;
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stop-mode = <&gpr 0x10 3>;
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fsl,num-tx-queues=<3>;
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fsl,num-rx-queues=<3>;
|
||
|
|
fsl,wakeup_irq = <2>;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
imx_ion {
|
||
|
|
compatible = "fsl,mxc-ion";
|
||
|
|
fsl,heap-id = <0>;
|
||
|
|
};
|
||
|
|
|
||
|
|
i2c1: i2c@30a20000 {
|
||
|
|
#address-cells = <1>;
|
||
|
|
#size-cells = <0>;
|
||
|
|
compatible = "fsl,imx21-i2c";
|
||
|
|
reg = <0x0 0x30a20000 0x0 0x10000>;
|
||
|
|
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
clocks = <&clk IMX8MQ_CLK_I2C1_ROOT>;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
i2c2: i2c@30a30000 {
|
||
|
|
#address-cells = <1>;
|
||
|
|
#size-cells = <0>;
|
||
|
|
compatible = "fsl,imx21-i2c";
|
||
|
|
reg = <0x0 0x30a30000 0x0 0x10000>;
|
||
|
|
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
clocks = <&clk IMX8MQ_CLK_I2C2_ROOT>;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
i2c3: i2c@30a40000 {
|
||
|
|
#address-cells = <1>;
|
||
|
|
#size-cells = <0>;
|
||
|
|
compatible = "fsl,imx21-i2c";
|
||
|
|
reg = <0x0 0x30a40000 0x0 0x10000>;
|
||
|
|
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
clocks = <&clk IMX8MQ_CLK_I2C3_ROOT>;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
i2c4: i2c@30a50000 {
|
||
|
|
#address-cells = <1>;
|
||
|
|
#size-cells = <0>;
|
||
|
|
compatible = "fsl,imx21-i2c";
|
||
|
|
reg = <0x0 0x30a50000 0x0 0x10000>;
|
||
|
|
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
clocks = <&clk IMX8MQ_CLK_I2C4_ROOT>;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
wdog1: wdog@30280000 {
|
||
|
|
compatible = "fsl,imx21-wdt";
|
||
|
|
reg = <0 0x30280000 0 0x10000>;
|
||
|
|
interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
clocks = <&clk IMX8MQ_CLK_WDOG1_ROOT>;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
wdog2: wdog@30290000 {
|
||
|
|
compatible = "fsl,imx21-wdt";
|
||
|
|
reg = <0 0x30290000 0 0x10000>;
|
||
|
|
interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
clocks = <&clk IMX8MQ_CLK_WDOG2_ROOT>;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
wdog3: wdog@302a0000 {
|
||
|
|
compatible = "fsl,imx21-wdt";
|
||
|
|
reg = <0 0x302a0000 0 0x10000>;
|
||
|
|
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
clocks = <&clk IMX8MQ_CLK_WDOG3_ROOT>;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
dma_cap: dma_cap {
|
||
|
|
compatible = "dma-capability";
|
||
|
|
only-dma-mask32 = <1>;
|
||
|
|
};
|
||
|
|
|
||
|
|
qspi: qspi@30bb0000 {
|
||
|
|
#address-cells = <1>;
|
||
|
|
#size-cells = <0>;
|
||
|
|
compatible = "fsl,imx7d-qspi";
|
||
|
|
reg = <0 0x30bb0000 0 0x10000>, <0 0x08000000 0 0x10000000>;
|
||
|
|
reg-names = "QuadSPI", "QuadSPI-memory";
|
||
|
|
interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
clocks = <&clk IMX8MQ_CLK_QSPI_ROOT>,
|
||
|
|
<&clk IMX8MQ_CLK_QSPI_ROOT>;
|
||
|
|
clock-names = "qspi_en", "qspi";
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
&A53_0 {
|
||
|
|
#cooling-cells = <2>;
|
||
|
|
};
|