2016-05-08 06:30:16 +00:00
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/*
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* (C) Copyright 2016 Beniamino Galvani <b.galvani@gmail.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <libfdt.h>
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#include <linux/err.h>
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#include <asm/arch/gxbb.h>
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2016-05-08 06:30:17 +00:00
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#include <asm/arch/sm.h>
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2016-05-08 06:30:16 +00:00
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#include <asm/armv8/mmu.h>
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#include <asm/unaligned.h>
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DECLARE_GLOBAL_DATA_PTR;
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int dram_init(void)
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{
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const fdt64_t *val;
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int offset;
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int len;
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offset = fdt_path_offset(gd->fdt_blob, "/memory");
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if (offset < 0)
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return -EINVAL;
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val = fdt_getprop(gd->fdt_blob, offset, "reg", &len);
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if (len < sizeof(*val) * 2)
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return -EINVAL;
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/* Use unaligned access since cache is still disabled */
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gd->ram_size = get_unaligned_be64(&val[1]);
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return 0;
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}
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void dram_init_banksize(void)
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{
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/* Reserve first 16 MiB of RAM for firmware */
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gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE + (16 * 1024 * 1024);
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gd->bd->bi_dram[0].size = gd->ram_size - (16 * 1024 * 1024);
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}
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void reset_cpu(ulong addr)
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{
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psci_system_reset(true);
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}
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static struct mm_region gxbb_mem_map[] = {
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{
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.base = 0x0UL,
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.size = 0x80000000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
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PTE_BLOCK_INNER_SHARE
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}, {
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.base = 0x80000000UL,
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.size = 0x80000000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN
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}, {
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/* List terminator */
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0,
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}
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};
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struct mm_region *mem_map = gxbb_mem_map;
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