u-boot/arch/arm/mach-versal/include/mach/sys_proto.h

/* SPDX-License-Identifier: GPL-2.0+ */
/*
 * Copyright 2016 - 2018 Xilinx, Inc.
 */

enum {
	TCM_LOCK,
	TCM_SPLIT,
};

#define PAYLOAD_ARG_CNT	4U

void tcm_init(u8 mode);
void mem_map_fill(void);

int versal_pm_request(u32 api_id, u32 arg0, u32 arg1, u32 arg2,
		      u32 arg3, u32 *ret_payload);
arm64: versal: Add support for new Xilinx Versal ACAPs Xilinx is introducing Versal, an adaptive compute acceleration platform (ACAP), built on 7nm FinFET process technology. Versal ACAPs combine Scalar Processing Engines, Adaptable Hardware Engines, and Intelligent Engines with leading-edge memory and interfacing technologies to deliver powerful heterogeneous acceleration for any application. The Versal AI Core series has five devices, offering 128 to 400 AI Engines. The series includes dual-core Arm Cortex™-A72 application processors, dual-core Arm Cortex-R5 real-time processors, 256KB of on-chip memory with ECC, more than 1,900 DSP engines optimized for high-precision floating point with low latency. The patch is adding necessary infrastructure in place without enabling platform which is done in separate patch. Signed-off-by: Michal Simek <michal.simek@xilinx.com> 2018-08-22 12:55:27 +00:00			`/* SPDX-License-Identifier: GPL-2.0+ */`
			`/*`
			`* Copyright 2016 - 2018 Xilinx, Inc.`
			`*/`

arm64: versal: Add new Kconfig SYS_MEM_RSVD_FOR_MMU This patch adds new config option which is used for reserving a specific memory for MMU Table and in this case we are using TCM for that purpose. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> 2019-01-08 16:17:26 +00:00			`enum {`
			`TCM_LOCK,`
			`TCM_SPLIT,`
			`};`

clk: versal: Add clock driver support This patch adds clock driver support for Versal platform. The clock driver queries and performs clock operations using PLM firmware by communicating with it using SMC calls. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> 2019-06-23 06:54:57 +00:00			`#define PAYLOAD_ARG_CNT 4U`

arm64: versal: Add new Kconfig SYS_MEM_RSVD_FOR_MMU This patch adds new config option which is used for reserving a specific memory for MMU Table and in this case we are using TCM for that purpose. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> 2019-01-08 16:17:26 +00:00			`void tcm_init(u8 mode);`
arm64: versal: Enable memory mapping via DT Code reads DT and setup MMU table based on memory node. This will ensure that only DT needs to be changed. Signed-off-by: Michal Simek <michal.simek@xilinx.com> 2019-04-29 16:39:09 +00:00			`void mem_map_fill(void);`
clk: versal: Add clock driver support This patch adds clock driver support for Versal platform. The clock driver queries and performs clock operations using PLM firmware by communicating with it using SMC calls. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> 2019-06-23 06:54:57 +00:00
			`int versal_pm_request(u32 api_id, u32 arg0, u32 arg1, u32 arg2,`
			`u32 arg3, u32 *ret_payload);`