mirror of
https://github.com/AsahiLinux/u-boot
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125 lines
3 KiB
Text
125 lines
3 KiB
Text
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// SPDX-License-Identifier: (GPL-2.0)
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/*
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* support for the imx6 based aristainetos2 board
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*
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* Copyright (C) 2019 Heiko Schocher <hs@denx.de>
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* Copyright (C) 2015 Heiko Schocher <hs@denx.de>
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*
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*/
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/dts-v1/;
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#include "imx6dl.dtsi"
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#include "imx6qdl-aristainetos2.dtsi"
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/ {
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model = "aristainetos2 i.MX6 Dual Lite Board 4";
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compatible = "fsl,imx6dl";
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memory@10000000 {
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device_type = "memory";
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reg = <0x10000000 0x40000000>;
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};
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display0: disp0 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,imx-parallel-display";
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interface-pix-fmt = "rgb24";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_ipu_disp>;
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port@0 {
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reg = <0>;
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display0_in: endpoint {
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remote-endpoint = <&ipu1_di0_disp0>;
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};
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};
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port@1 {
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reg = <1>;
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display_out: endpoint {
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remote-endpoint = <&panel_in>;
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};
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};
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};
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};
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&ecspi1 {
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lcd_panel: display@0 {
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compatible = "lg,lg4573";
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spi-max-frequency = <10000000>;
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reg = <0>;
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power-on-delay = <10>;
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display-timings {
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480x800p57 {
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native-mode;
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clock-frequency = <27000027>;
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hactive = <480>;
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vactive = <800>;
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hfront-porch = <10>;
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hback-porch = <59>;
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hsync-len = <10>;
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vback-porch = <15>;
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vfront-porch = <15>;
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vsync-len = <15>;
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hsync-active = <1>;
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vsync-active = <1>;
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};
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};
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port {
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panel_in: endpoint {
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remote-endpoint = <&display_out>;
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};
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};
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};
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};
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&i2c3 {
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touch: touch@4b {
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compatible = "atmel,maxtouch";
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reg = <0x4b>;
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interrupt-parent = <&gpio2>;
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interrupts = <9 8>;
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};
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};
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&ipu1_di0_disp0 {
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remote-endpoint = <&display0_in>;
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};
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&iomuxc {
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pinctrl_ipu_disp: ipudisp1grp {
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fsl,pins = <
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MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x31
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MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0xE1
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MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10
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MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10
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MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0xE1
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MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0xE1
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MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0xE1
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MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0xE1
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MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0xE1
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MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0xE1
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MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0xE1
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MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0xE1
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MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0xE1
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MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0xE1
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MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0xE1
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MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0xE1
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MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0xE1
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MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0xE1
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MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0xe1
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MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0xE1
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MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0xE1
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MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0xE1
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MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0xE1
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MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0xE1
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MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0xE1
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MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0xE1
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MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0xE1
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MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0xE1
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>;
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};
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};
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