2022-09-27 08:45:15 +00:00
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/* SPDX-License-Identifier: GPL-2.0+ */
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#ifndef _NPCM_RST_H_
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#define _NPCM_RST_H_
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/* Watchdog Timer Controller Register */
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#define WTCR0_REG 0xF000801C
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#define WTCR_WTR BIT(0)
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#define WTCR_WTRE BIT(1)
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#define WTCR_WTE BIT(7)
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/* Reset status bits */
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#define PORST BIT(31)
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#define CORST BIT(30)
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#define WD0RST BIT(29)
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#define SW1RST BIT(28)
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#define SW2RST BIT(27)
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#define SW3RST BIT(26)
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2022-12-20 08:49:31 +00:00
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#define TIPRST BIT(25)
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2022-09-27 08:45:15 +00:00
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#define WD1RST BIT(24)
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#define WD2RST BIT(23)
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#define RST_STS_MASK GENMASK(31, 23)
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int npcm_get_reset_status(void);
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#endif
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