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u-boot/arch/x86/cpu/intel_common/p2sb.c

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x86: apl: Add P2SB driver Adds a driver for the Apollo Lake Primary-to-sideband bus. This supports various child devices. It supposed both device tree and of-platdata. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-09 00:40:16 +00:00
// SPDX-License-Identifier: GPL-2.0
/*
* Primary-to-Sideband Bridge
*
* Copyright 2019 Google LLC
*/
#define LOG_CATEGORY UCLASS_P2SB
#include <common.h>
#include <dm.h>
#include <dt-structs.h>
common: Drop log.h from common header Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-10 17:40:05 +00:00
#include <log.h>
x86: apl: Add P2SB driver Adds a driver for the Apollo Lake Primary-to-sideband bus. This supports various child devices. It supposed both device tree and of-platdata. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-09 00:40:16 +00:00
#include <p2sb.h>
#include <spl.h>
x86: Move priv/plat structs for intel_common to headers With the new of-platdata, these need to be available to dt_platdata.c so must be in header files. Move them. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-12-19 17:39:58 +00:00
#include <asm/p2sb.h>
x86: apl: Add P2SB driver Adds a driver for the Apollo Lake Primary-to-sideband bus. This supports various child devices. It supposed both device tree and of-platdata. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-09 00:40:16 +00:00
#include <asm/pci.h>
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-10 17:40:13 +00:00
#include <linux/bitops.h>
x86: apl: Add P2SB driver Adds a driver for the Apollo Lake Primary-to-sideband bus. This supports various child devices. It supposed both device tree and of-platdata. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-09 00:40:16 +00:00
x86: apl: Support set_hide() in p2sb driver Add support for this new method in the driver and in the fsp-s setup. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
2020-07-08 03:32:31 +00:00
#define PCH_P2SB_E0 0xe0
#define HIDE_BIT BIT(0)
x86: apl: Add P2SB driver Adds a driver for the Apollo Lake Primary-to-sideband bus. This supports various child devices. It supposed both device tree and of-platdata. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-09 00:40:16 +00:00
/* PCI config space registers */
#define HPTC_OFFSET 0x60
#define HPTC_ADDR_ENABLE_BIT BIT(7)
/* High Performance Event Timer Configuration */
#define P2SB_HPTC 0x60
#define P2SB_HPTC_ADDRESS_ENABLE BIT(7)
/*
* ADDRESS_SELECT ENCODING_RANGE
* 0 0xfed0 0000 - 0xfed0 03ff
* 1 0xfed0 1000 - 0xfed0 13ff
* 2 0xfed0 2000 - 0xfed0 23ff
* 3 0xfed0 3000 - 0xfed0 33ff
*/
#define P2SB_HPTC_ADDRESS_SELECT_0 (0 << 0)
#define P2SB_HPTC_ADDRESS_SELECT_1 (1 << 0)
#define P2SB_HPTC_ADDRESS_SELECT_2 (2 << 0)
#define P2SB_HPTC_ADDRESS_SELECT_3 (3 << 0)
/*
x86: p2sb: Drop 'apl' prefix Drop the Apollo Lake prefix 'apl' from the functions, types and variables in the P2SB driver. The P2SB is not Apollo Lake specific, and as such it was moved in commit 2999846c1127 ("x86: Move P2SB from Apollo Lake to a more generic location") from the Apollo Lake folder to the intel_common folder. Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-02-18 14:32:10 +00:00
* p2sb_early_init() - Enable decoding for HPET range
x86: apl: Add P2SB driver Adds a driver for the Apollo Lake Primary-to-sideband bus. This supports various child devices. It supposed both device tree and of-platdata. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-09 00:40:16 +00:00
*
* This is needed by FSP-M which uses the High Precision Event Timer.
*
* @dev: P2SB device
doc: replace @return by Return: Sphinx expects Return: and not @return to indicate a return value. find . -name '*.c' -exec \ sed -i 's/^\(\s\)\*\(\s*\)@return\(\s\)/\1*\2Return:\3/' {} \; find . -name '*.h' -exec \ sed -i 's/^\(\s\)\*\(\s*\)@return\(\s\)/\1*\2Return:\3/' {} \; Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2022-01-19 17:05:50 +00:00
* Return: 0 if OK, -ve on error
x86: apl: Add P2SB driver Adds a driver for the Apollo Lake Primary-to-sideband bus. This supports various child devices. It supposed both device tree and of-platdata. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-09 00:40:16 +00:00
*/
x86: p2sb: Drop 'apl' prefix Drop the Apollo Lake prefix 'apl' from the functions, types and variables in the P2SB driver. The P2SB is not Apollo Lake specific, and as such it was moved in commit 2999846c1127 ("x86: Move P2SB from Apollo Lake to a more generic location") from the Apollo Lake folder to the intel_common folder. Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-02-18 14:32:10 +00:00
static int p2sb_early_init(struct udevice *dev)
x86: apl: Add P2SB driver Adds a driver for the Apollo Lake Primary-to-sideband bus. This supports various child devices. It supposed both device tree and of-platdata. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-09 00:40:16 +00:00
{
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-12-03 23:55:23 +00:00
struct p2sb_plat *plat = dev_get_plat(dev);
x86: apl: Add P2SB driver Adds a driver for the Apollo Lake Primary-to-sideband bus. This supports various child devices. It supposed both device tree and of-platdata. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-09 00:40:16 +00:00
pci_dev_t pdev = plat->bdf;
/*
* Enable decoding for HPET memory address range.
* HPTC_OFFSET(0x60) bit 7, when set the P2SB will decode
* the High Performance Timer memory address range
* selected by bits 1:0
*/
pci_x86_write_config(pdev, HPTC_OFFSET, HPTC_ADDR_ENABLE_BIT,
PCI_SIZE_8);
/* Enable PCR Base address in PCH */
pci_x86_write_config(pdev, PCI_BASE_ADDRESS_0, plat->mmio_base,
PCI_SIZE_32);
pci_x86_write_config(pdev, PCI_BASE_ADDRESS_1, 0, PCI_SIZE_32);
/* Enable P2SB MSE */
pci_x86_write_config(pdev, PCI_COMMAND, PCI_COMMAND_MASTER |
PCI_COMMAND_MEMORY, PCI_SIZE_8);
return 0;
}
x86: p2sb: Drop 'apl' prefix Drop the Apollo Lake prefix 'apl' from the functions, types and variables in the P2SB driver. The P2SB is not Apollo Lake specific, and as such it was moved in commit 2999846c1127 ("x86: Move P2SB from Apollo Lake to a more generic location") from the Apollo Lake folder to the intel_common folder. Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-02-18 14:32:10 +00:00
static int p2sb_spl_init(struct udevice *dev)
x86: apl: Add P2SB driver Adds a driver for the Apollo Lake Primary-to-sideband bus. This supports various child devices. It supposed both device tree and of-platdata. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-09 00:40:16 +00:00
{
/* Enable decoding for HPET. Needed for FSP global pointer storage */
dm_pci_write_config(dev, P2SB_HPTC, P2SB_HPTC_ADDRESS_SELECT_0 |
P2SB_HPTC_ADDRESS_ENABLE, PCI_SIZE_8);
return 0;
}
dm: treewide: Rename ofdata_to_platdata() to of_to_plat() This name is far too long. Rename it to remove the 'data' bits. This makes it consistent with the platdata->plat rename. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-12-03 23:55:21 +00:00
int p2sb_of_to_plat(struct udevice *dev)
x86: apl: Add P2SB driver Adds a driver for the Apollo Lake Primary-to-sideband bus. This supports various child devices. It supposed both device tree and of-platdata. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-09 00:40:16 +00:00
{
struct p2sb_uc_priv *upriv = dev_get_uclass_priv(dev);
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-12-03 23:55:23 +00:00
struct p2sb_plat *plat = dev_get_plat(dev);
x86: apl: Add P2SB driver Adds a driver for the Apollo Lake Primary-to-sideband bus. This supports various child devices. It supposed both device tree and of-platdata. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-09 00:40:16 +00:00
treewide: Use OF_REAL instead of !OF_PLATDATA Now that we have a 'positive' Kconfig option, use this instead of the negative one, which is harder to understand. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-08-07 13:24:04 +00:00
#if CONFIG_IS_ENABLED(OF_REAL)
x86: apl: Add P2SB driver Adds a driver for the Apollo Lake Primary-to-sideband bus. This supports various child devices. It supposed both device tree and of-platdata. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-09 00:40:16 +00:00
int ret;
x86: apl: Move p2sb ofdata reading to the correct method With P2SB the initial BAR (base-address register) is set up by TPL and this is used unchanged right through U-Boot. At present the reading of this address is split between the ofdata() and probe() methods. There are a few problems that are unique to the p2sb. One is that its children need to call pcr_read32(), etc. which needs to have the p2sb address correct. Also some of its children are pinctrl devices and pinctrl is used when any device is probed. So p2sb really needs to get its base address set up in ofdata_to_platdata(), before it is probed. Another point is that reading the p2sb BAR will not work if the p2sb is hidden. The FSP-S seems to hide it, presumably to avoid confusing PCI enumeration. Reading ofdata in ofdata_to_platdata() is the correct place anyway, so this is easy to fix. Move the code into one place and use the early-regs property in all cases for simplicity and to avoid needing to probe any PCI devices just to read the BAR. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
2020-04-08 22:57:28 +00:00
u32 base[2];
x86: apl: Add P2SB driver Adds a driver for the Apollo Lake Primary-to-sideband bus. This supports various child devices. It supposed both device tree and of-platdata. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-09 00:40:16 +00:00
x86: apl: Move p2sb ofdata reading to the correct method With P2SB the initial BAR (base-address register) is set up by TPL and this is used unchanged right through U-Boot. At present the reading of this address is split between the ofdata() and probe() methods. There are a few problems that are unique to the p2sb. One is that its children need to call pcr_read32(), etc. which needs to have the p2sb address correct. Also some of its children are pinctrl devices and pinctrl is used when any device is probed. So p2sb really needs to get its base address set up in ofdata_to_platdata(), before it is probed. Another point is that reading the p2sb BAR will not work if the p2sb is hidden. The FSP-S seems to hide it, presumably to avoid confusing PCI enumeration. Reading ofdata in ofdata_to_platdata() is the correct place anyway, so this is easy to fix. Move the code into one place and use the early-regs property in all cases for simplicity and to avoid needing to probe any PCI devices just to read the BAR. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
2020-04-08 22:57:28 +00:00
ret = dev_read_u32_array(dev, "early-regs", base, ARRAY_SIZE(base));
if (ret)
return log_msg_ret("Missing/short early-regs", ret);
plat->mmio_base = base[0];
/* TPL sets up the initial BAR */
x86: apl: Add P2SB driver Adds a driver for the Apollo Lake Primary-to-sideband bus. This supports various child devices. It supposed both device tree and of-platdata. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-09 00:40:16 +00:00
if (spl_phase() == PHASE_TPL) {
plat->bdf = pci_get_devfn(dev);
if (plat->bdf < 0)
return log_msg_ret("Cannot get p2sb PCI address",
plat->bdf);
}
x86: apl: Move p2sb ofdata reading to the correct method With P2SB the initial BAR (base-address register) is set up by TPL and this is used unchanged right through U-Boot. At present the reading of this address is split between the ofdata() and probe() methods. There are a few problems that are unique to the p2sb. One is that its children need to call pcr_read32(), etc. which needs to have the p2sb address correct. Also some of its children are pinctrl devices and pinctrl is used when any device is probed. So p2sb really needs to get its base address set up in ofdata_to_platdata(), before it is probed. Another point is that reading the p2sb BAR will not work if the p2sb is hidden. The FSP-S seems to hide it, presumably to avoid confusing PCI enumeration. Reading ofdata in ofdata_to_platdata() is the correct place anyway, so this is easy to fix. Move the code into one place and use the early-regs property in all cases for simplicity and to avoid needing to probe any PCI devices just to read the BAR. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
2020-04-08 22:57:28 +00:00
upriv->mmio_base = plat->mmio_base;
x86: apl: Add P2SB driver Adds a driver for the Apollo Lake Primary-to-sideband bus. This supports various child devices. It supposed both device tree and of-platdata. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-09 00:40:16 +00:00
#else
plat->mmio_base = plat->dtplat.early_regs[0];
plat->bdf = pci_ofplat_get_devfn(plat->dtplat.reg[0]);
upriv->mmio_base = plat->mmio_base;
x86: apl: Move p2sb ofdata reading to the correct method With P2SB the initial BAR (base-address register) is set up by TPL and this is used unchanged right through U-Boot. At present the reading of this address is split between the ofdata() and probe() methods. There are a few problems that are unique to the p2sb. One is that its children need to call pcr_read32(), etc. which needs to have the p2sb address correct. Also some of its children are pinctrl devices and pinctrl is used when any device is probed. So p2sb really needs to get its base address set up in ofdata_to_platdata(), before it is probed. Another point is that reading the p2sb BAR will not work if the p2sb is hidden. The FSP-S seems to hide it, presumably to avoid confusing PCI enumeration. Reading ofdata in ofdata_to_platdata() is the correct place anyway, so this is easy to fix. Move the code into one place and use the early-regs property in all cases for simplicity and to avoid needing to probe any PCI devices just to read the BAR. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
2020-04-08 22:57:28 +00:00
#endif
x86: apl: Add P2SB driver Adds a driver for the Apollo Lake Primary-to-sideband bus. This supports various child devices. It supposed both device tree and of-platdata. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-09 00:40:16 +00:00
return 0;
}
x86: p2sb: Drop 'apl' prefix Drop the Apollo Lake prefix 'apl' from the functions, types and variables in the P2SB driver. The P2SB is not Apollo Lake specific, and as such it was moved in commit 2999846c1127 ("x86: Move P2SB from Apollo Lake to a more generic location") from the Apollo Lake folder to the intel_common folder. Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-02-18 14:32:10 +00:00
static int p2sb_probe(struct udevice *dev)
x86: apl: Add P2SB driver Adds a driver for the Apollo Lake Primary-to-sideband bus. This supports various child devices. It supposed both device tree and of-platdata. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-09 00:40:16 +00:00
{
x86: apl: Move p2sb ofdata reading to the correct method With P2SB the initial BAR (base-address register) is set up by TPL and this is used unchanged right through U-Boot. At present the reading of this address is split between the ofdata() and probe() methods. There are a few problems that are unique to the p2sb. One is that its children need to call pcr_read32(), etc. which needs to have the p2sb address correct. Also some of its children are pinctrl devices and pinctrl is used when any device is probed. So p2sb really needs to get its base address set up in ofdata_to_platdata(), before it is probed. Another point is that reading the p2sb BAR will not work if the p2sb is hidden. The FSP-S seems to hide it, presumably to avoid confusing PCI enumeration. Reading ofdata in ofdata_to_platdata() is the correct place anyway, so this is easy to fix. Move the code into one place and use the early-regs property in all cases for simplicity and to avoid needing to probe any PCI devices just to read the BAR. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
2020-04-08 22:57:28 +00:00
if (spl_phase() == PHASE_TPL)
x86: p2sb: Drop 'apl' prefix Drop the Apollo Lake prefix 'apl' from the functions, types and variables in the P2SB driver. The P2SB is not Apollo Lake specific, and as such it was moved in commit 2999846c1127 ("x86: Move P2SB from Apollo Lake to a more generic location") from the Apollo Lake folder to the intel_common folder. Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-02-18 14:32:10 +00:00
return p2sb_early_init(dev);
x86: apl: Move p2sb ofdata reading to the correct method With P2SB the initial BAR (base-address register) is set up by TPL and this is used unchanged right through U-Boot. At present the reading of this address is split between the ofdata() and probe() methods. There are a few problems that are unique to the p2sb. One is that its children need to call pcr_read32(), etc. which needs to have the p2sb address correct. Also some of its children are pinctrl devices and pinctrl is used when any device is probed. So p2sb really needs to get its base address set up in ofdata_to_platdata(), before it is probed. Another point is that reading the p2sb BAR will not work if the p2sb is hidden. The FSP-S seems to hide it, presumably to avoid confusing PCI enumeration. Reading ofdata in ofdata_to_platdata() is the correct place anyway, so this is easy to fix. Move the code into one place and use the early-regs property in all cases for simplicity and to avoid needing to probe any PCI devices just to read the BAR. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
2020-04-08 22:57:28 +00:00
else if (spl_phase() == PHASE_SPL)
return p2sb_spl_init(dev);
x86: apl: Add P2SB driver Adds a driver for the Apollo Lake Primary-to-sideband bus. This supports various child devices. It supposed both device tree and of-platdata. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-09 00:40:16 +00:00
return 0;
}
x86: apl: Support set_hide() in p2sb driver Add support for this new method in the driver and in the fsp-s setup. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
2020-07-08 03:32:31 +00:00
static void p2sb_set_hide_bit(struct udevice *dev, bool hide)
{
dm_pci_clrset_config8(dev, PCH_P2SB_E0 + 1, HIDE_BIT,
hide ? HIDE_BIT : 0);
}
static int intel_p2sb_set_hide(struct udevice *dev, bool hide)
{
u16 vendor;
if (!CONFIG_IS_ENABLED(PCI))
return -EPERM;
p2sb_set_hide_bit(dev, hide);
dm_pci_read_config16(dev, PCI_VENDOR_ID, &vendor);
if (hide && vendor != 0xffff)
return log_msg_ret("hide", -EEXIST);
else if (!hide && vendor != PCI_VENDOR_ID_INTEL)
return log_msg_ret("unhide", -ENOMEDIUM);
return 0;
}
x86: apl: Hide the p2sb on exit from U-Boot This confuses Linux's PCI probing so needs to be hidden when booting Linux. Add a remove() method to handle this. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
2020-07-08 03:32:32 +00:00
static int p2sb_remove(struct udevice *dev)
{
int ret;
ret = intel_p2sb_set_hide(dev, true);
if (ret)
return log_msg_ret("hide", ret);
return 0;
}
x86: apl: Add P2SB driver Adds a driver for the Apollo Lake Primary-to-sideband bus. This supports various child devices. It supposed both device tree and of-platdata. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-09 00:40:16 +00:00
static int p2sb_child_post_bind(struct udevice *dev)
{
treewide: Try to avoid the preprocessor with OF_REAL Convert some of these occurences to C code, where it is easy to do. This should help encourage this approach to be used in new code. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-08-07 13:24:06 +00:00
if (CONFIG_IS_ENABLED(OF_REAL)) {
struct p2sb_child_plat *pplat = dev_get_parent_plat(dev);
int ret;
u32 pid;
ret = dev_read_u32(dev, "intel,p2sb-port-id", &pid);
if (ret)
return ret;
pplat->pid = pid;
}
x86: apl: Add P2SB driver Adds a driver for the Apollo Lake Primary-to-sideband bus. This supports various child devices. It supposed both device tree and of-platdata. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-09 00:40:16 +00:00
return 0;
}
x86: apl: Use const for driver operations Update these declarations to const to ensure that the data ends up in the rodata section. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-12-23 15:11:26 +00:00
static const struct p2sb_ops p2sb_ops = {
x86: apl: Support set_hide() in p2sb driver Add support for this new method in the driver and in the fsp-s setup. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
2020-07-08 03:32:31 +00:00
.set_hide = intel_p2sb_set_hide,
};
treewide: Use OF_REAL instead of !OF_PLATDATA Now that we have a 'positive' Kconfig option, use this instead of the negative one, which is harder to understand. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-08-07 13:24:04 +00:00
#if CONFIG_IS_ENABLED(OF_REAL)
x86: p2sb: Drop 'apl' prefix Drop the Apollo Lake prefix 'apl' from the functions, types and variables in the P2SB driver. The P2SB is not Apollo Lake specific, and as such it was moved in commit 2999846c1127 ("x86: Move P2SB from Apollo Lake to a more generic location") from the Apollo Lake folder to the intel_common folder. Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-02-18 14:32:10 +00:00
static const struct udevice_id p2sb_ids[] = {
{ .compatible = "intel,p2sb" },
x86: apl: Add P2SB driver Adds a driver for the Apollo Lake Primary-to-sideband bus. This supports various child devices. It supposed both device tree and of-platdata. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-09 00:40:16 +00:00
{ }
};
x86: apl: Reduce size for TPL Update various drivers to use of_match_ptr() and to avoid including debug strings in TPL. Omit the WiFi driver entirely, since it is not used in TPL. This reduces the TPL binary size by about 608 bytes. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-12-23 15:11:30 +00:00
#endif
x86: apl: Add P2SB driver Adds a driver for the Apollo Lake Primary-to-sideband bus. This supports various child devices. It supposed both device tree and of-platdata. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-09 00:40:16 +00:00
x86: Fix up driver names to avoid dtoc warnings At present there are a lot of dtoc warnings reported when building chromebook_coral, of the form: WARNING: the driver intel_apl_lpc was not found in the driver list Correct these by using driver names that matches their compatible string. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-10-05 11:27:01 +00:00
U_BOOT_DRIVER(intel_p2sb) = {
x86: p2sb: Drop 'apl' prefix Drop the Apollo Lake prefix 'apl' from the functions, types and variables in the P2SB driver. The P2SB is not Apollo Lake specific, and as such it was moved in commit 2999846c1127 ("x86: Move P2SB from Apollo Lake to a more generic location") from the Apollo Lake folder to the intel_common folder. Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-02-18 14:32:10 +00:00
.name = "intel_p2sb",
x86: apl: Add P2SB driver Adds a driver for the Apollo Lake Primary-to-sideband bus. This supports various child devices. It supposed both device tree and of-platdata. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-09 00:40:16 +00:00
.id = UCLASS_P2SB,
x86: apl: Reduce size for TPL Update various drivers to use of_match_ptr() and to avoid including debug strings in TPL. Omit the WiFi driver entirely, since it is not used in TPL. This reduces the TPL binary size by about 608 bytes. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-12-23 15:11:30 +00:00
.of_match = of_match_ptr(p2sb_ids),
x86: p2sb: Drop 'apl' prefix Drop the Apollo Lake prefix 'apl' from the functions, types and variables in the P2SB driver. The P2SB is not Apollo Lake specific, and as such it was moved in commit 2999846c1127 ("x86: Move P2SB from Apollo Lake to a more generic location") from the Apollo Lake folder to the intel_common folder. Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-02-18 14:32:10 +00:00
.probe = p2sb_probe,
x86: apl: Hide the p2sb on exit from U-Boot This confuses Linux's PCI probing so needs to be hidden when booting Linux. Add a remove() method to handle this. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
2020-07-08 03:32:32 +00:00
.remove = p2sb_remove,
x86: apl: Support set_hide() in p2sb driver Add support for this new method in the driver and in the fsp-s setup. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
2020-07-08 03:32:31 +00:00
.ops = &p2sb_ops,
dm: treewide: Rename ofdata_to_platdata() to of_to_plat() This name is far too long. Rename it to remove the 'data' bits. This makes it consistent with the platdata->plat rename. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-12-03 23:55:21 +00:00
.of_to_plat = p2sb_of_to_plat,
dm: treewide: Rename ..._platdata variables to just ..._plat Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-12-03 23:55:23 +00:00
.plat_auto = sizeof(struct p2sb_plat),
.per_child_plat_auto = sizeof(struct p2sb_child_plat),
x86: apl: Add P2SB driver Adds a driver for the Apollo Lake Primary-to-sideband bus. This supports various child devices. It supposed both device tree and of-platdata. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-09 00:40:16 +00:00
.child_post_bind = p2sb_child_post_bind,
x86: apl: Hide the p2sb on exit from U-Boot This confuses Linux's PCI probing so needs to be hidden when booting Linux. Add a remove() method to handle this. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
2020-07-08 03:32:32 +00:00
.flags = DM_FLAG_OS_PREPARE,
x86: apl: Add P2SB driver Adds a driver for the Apollo Lake Primary-to-sideband bus. This supports various child devices. It supposed both device tree and of-platdata. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-09 00:40:16 +00:00
};
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