2018-05-06 21:58:06 +00:00
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// SPDX-License-Identifier: GPL-2.0+
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2016-04-25 08:50:42 +00:00
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/*
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* Copyright (C) 2015 - 2016 Xilinx, Inc.
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2017-09-12 13:46:59 +00:00
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* Copyright (C) 2017 National Instruments Corp
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2016-04-25 08:50:42 +00:00
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* Written by Michal Simek
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*/
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#include <common.h>
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#include <dm.h>
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#include <errno.h>
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#include <i2c.h>
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2020-05-10 17:40:05 +00:00
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#include <log.h>
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2020-02-03 14:36:16 +00:00
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#include <malloc.h>
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2017-09-12 13:46:59 +00:00
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#include <asm-generic/gpio.h>
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2016-04-25 08:50:42 +00:00
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DECLARE_GLOBAL_DATA_PTR;
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2017-06-09 17:28:43 +00:00
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enum pca_type {
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PCA9543,
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PCA9544,
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PCA9546,
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PCA9547,
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PCA9548,
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PCA9646
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};
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struct chip_desc {
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u8 enable; /* Enable mask in ctl register (used for muxes only) */
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enum muxtype {
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pca954x_ismux = 0,
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pca954x_isswi,
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} muxtype;
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u32 width;
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};
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struct pca954x_priv {
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u32 addr; /* I2C mux address */
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u32 width; /* I2C mux width - number of busses */
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struct gpio_desc gpio_mux_reset;
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};
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static const struct chip_desc chips[] = {
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[PCA9543] = {
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.muxtype = pca954x_isswi,
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.width = 2,
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},
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[PCA9544] = {
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.enable = 0x4,
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.muxtype = pca954x_ismux,
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.width = 4,
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},
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[PCA9546] = {
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.muxtype = pca954x_isswi,
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.width = 4,
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},
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[PCA9547] = {
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.enable = 0x8,
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.muxtype = pca954x_ismux,
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.width = 8,
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},
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[PCA9548] = {
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.muxtype = pca954x_isswi,
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.width = 8,
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},
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[PCA9646] = {
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.muxtype = pca954x_isswi,
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.width = 4,
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},
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};
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static int pca954x_deselect(struct udevice *mux, struct udevice *bus,
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uint channel)
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{
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struct pca954x_priv *priv = dev_get_priv(mux);
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uchar byte = 0;
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return dm_i2c_write(mux, priv->addr, &byte, 1);
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}
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static int pca954x_select(struct udevice *mux, struct udevice *bus,
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uint channel)
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{
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struct pca954x_priv *priv = dev_get_priv(mux);
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const struct chip_desc *chip = &chips[dev_get_driver_data(mux)];
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uchar byte;
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if (chip->muxtype == pca954x_ismux)
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byte = channel | chip->enable;
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else
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byte = 1 << channel;
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return dm_i2c_write(mux, priv->addr, &byte, 1);
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}
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static const struct i2c_mux_ops pca954x_ops = {
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.select = pca954x_select,
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.deselect = pca954x_deselect,
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};
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static const struct udevice_id pca954x_ids[] = {
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{ .compatible = "nxp,pca9543", .data = PCA9543 },
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{ .compatible = "nxp,pca9544", .data = PCA9544 },
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{ .compatible = "nxp,pca9546", .data = PCA9546 },
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{ .compatible = "nxp,pca9547", .data = PCA9547 },
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{ .compatible = "nxp,pca9548", .data = PCA9548 },
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{ .compatible = "nxp,pca9646", .data = PCA9646 },
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{ }
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};
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static int pca954x_ofdata_to_platdata(struct udevice *dev)
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{
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struct pca954x_priv *priv = dev_get_priv(dev);
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const struct chip_desc *chip = &chips[dev_get_driver_data(dev)];
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2019-01-09 10:58:24 +00:00
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priv->addr = dev_read_u32_default(dev, "reg", 0);
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if (!priv->addr) {
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debug("MUX not found\n");
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return -ENODEV;
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}
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priv->width = chip->width;
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if (!priv->width) {
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debug("No I2C MUX width specified\n");
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return -EINVAL;
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}
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debug("Device %s at 0x%x with width %d\n",
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dev->name, priv->addr, priv->width);
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return 0;
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}
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static int pca954x_probe(struct udevice *dev)
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{
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if (CONFIG_IS_ENABLED(DM_GPIO)) {
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struct pca954x_priv *priv = dev_get_priv(dev);
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int err;
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err = gpio_request_by_name(dev, "reset-gpios", 0,
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&priv->gpio_mux_reset, GPIOD_IS_OUT);
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/* it's optional so only bail if we get a real error */
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if (err && (err != -ENOENT))
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return err;
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/* dm will take care of polarity */
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if (dm_gpio_is_valid(&priv->gpio_mux_reset))
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dm_gpio_set_value(&priv->gpio_mux_reset, 0);
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}
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return 0;
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}
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static int pca954x_remove(struct udevice *dev)
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{
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if (CONFIG_IS_ENABLED(DM_GPIO)) {
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struct pca954x_priv *priv = dev_get_priv(dev);
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if (dm_gpio_is_valid(&priv->gpio_mux_reset))
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dm_gpio_free(dev, &priv->gpio_mux_reset);
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}
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return 0;
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}
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U_BOOT_DRIVER(pca954x) = {
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.name = "pca954x",
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.id = UCLASS_I2C_MUX,
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.of_match = pca954x_ids,
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.probe = pca954x_probe,
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.remove = pca954x_remove,
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.ops = &pca954x_ops,
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.ofdata_to_platdata = pca954x_ofdata_to_platdata,
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.priv_auto_alloc_size = sizeof(struct pca954x_priv),
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};
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