2018-05-06 21:58:06 +00:00
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// SPDX-License-Identifier: GPL-2.0+
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2014-11-07 11:37:49 +00:00
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/*
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* Copyright (C) 2012
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* Altera Corporation <www.altera.com>
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*/
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#include <common.h>
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2019-11-20 21:27:31 +00:00
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#include <clk.h>
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2020-05-10 17:40:05 +00:00
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#include <log.h>
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2019-12-05 10:16:06 +00:00
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#include <asm-generic/io.h>
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2014-11-07 11:37:49 +00:00
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#include <dm.h>
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#include <fdtdec.h>
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#include <malloc.h>
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2019-03-01 19:12:35 +00:00
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#include <reset.h>
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2014-11-07 11:37:49 +00:00
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#include <spi.h>
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2020-01-27 05:06:39 +00:00
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#include <spi-mem.h>
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2020-02-03 14:36:16 +00:00
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#include <dm/device_compat.h>
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2020-02-03 14:36:15 +00:00
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#include <linux/err.h>
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2016-09-21 02:28:55 +00:00
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#include <linux/errno.h>
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2020-01-27 05:06:40 +00:00
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#include <linux/sizes.h>
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2022-05-12 10:05:34 +00:00
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#include <zynqmp_firmware.h>
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2014-11-07 11:37:49 +00:00
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#include "cadence_qspi.h"
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2022-05-12 10:05:34 +00:00
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#include <dt-bindings/power/xlnx-versal-power.h>
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2014-11-07 11:37:49 +00:00
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2021-06-25 19:17:08 +00:00
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#define NSEC_PER_SEC 1000000000L
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2014-11-07 11:37:49 +00:00
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#define CQSPI_STIG_READ 0
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#define CQSPI_STIG_WRITE 1
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2020-01-27 05:06:40 +00:00
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#define CQSPI_READ 2
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#define CQSPI_WRITE 3
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2014-11-07 11:37:49 +00:00
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2022-08-24 11:38:47 +00:00
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__weak int cadence_qspi_apb_dma_read(struct cadence_spi_priv *priv,
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2022-05-12 10:05:32 +00:00
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const struct spi_mem_op *op)
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{
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return 0;
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}
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2022-05-12 10:05:33 +00:00
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__weak int cadence_qspi_versal_flash_reset(struct udevice *dev)
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{
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return 0;
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}
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2014-11-07 11:37:49 +00:00
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static int cadence_spi_write_speed(struct udevice *bus, uint hz)
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{
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struct cadence_spi_priv *priv = dev_get_priv(bus);
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cadence_qspi_apb_config_baudrate_div(priv->regbase,
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2022-08-24 11:38:47 +00:00
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priv->ref_clk_hz, hz);
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2014-11-07 11:37:49 +00:00
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/* Reconfigure delay timing if speed is changed. */
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2022-08-24 11:38:47 +00:00
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cadence_qspi_apb_delay(priv->regbase, priv->ref_clk_hz, hz,
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priv->tshsl_ns, priv->tsd2d_ns,
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priv->tchsh_ns, priv->tslch_ns);
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2014-11-07 11:37:49 +00:00
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return 0;
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}
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2022-08-24 11:38:47 +00:00
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static int cadence_spi_read_id(struct cadence_spi_priv *priv, u8 len,
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2021-06-25 19:17:09 +00:00
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u8 *idcode)
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2020-01-27 05:06:39 +00:00
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{
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2022-08-24 11:38:46 +00:00
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int err;
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2022-08-24 11:38:47 +00:00
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2020-01-27 05:06:39 +00:00
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struct spi_mem_op op = SPI_MEM_OP(SPI_MEM_OP_CMD(0x9F, 1),
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SPI_MEM_OP_NO_ADDR,
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SPI_MEM_OP_NO_DUMMY,
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SPI_MEM_OP_DATA_IN(len, idcode, 1));
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2022-08-24 11:38:47 +00:00
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err = cadence_qspi_apb_command_read_setup(priv, &op);
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2022-08-24 11:38:46 +00:00
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if (!err)
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2022-08-24 11:38:47 +00:00
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err = cadence_qspi_apb_command_read(priv, &op);
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2022-08-24 11:38:46 +00:00
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return err;
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2020-01-27 05:06:39 +00:00
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}
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2014-11-07 11:37:49 +00:00
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/* Calibration sequence to determine the read data capture delay register */
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2015-10-17 13:31:55 +00:00
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static int spi_calibration(struct udevice *bus, uint hz)
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2014-11-07 11:37:49 +00:00
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{
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struct cadence_spi_priv *priv = dev_get_priv(bus);
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void *base = priv->regbase;
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unsigned int idcode = 0, temp = 0;
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int err = 0, i, range_lo = -1, range_hi = -1;
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/* start with slowest clock (1 MHz) */
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cadence_spi_write_speed(bus, 1000000);
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/* configure the read data capture delay register to 0 */
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cadence_qspi_apb_readdata_capture(base, 1, 0);
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/* Enable QSPI */
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cadence_qspi_apb_controller_enable(base);
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/* read the ID which will be our golden value */
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2022-08-24 11:38:47 +00:00
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err = cadence_spi_read_id(priv, 3, (u8 *)&idcode);
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2014-11-07 11:37:49 +00:00
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if (err) {
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puts("SF: Calibration failed (read)\n");
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return err;
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}
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/* use back the intended clock and find low range */
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2015-10-17 13:31:55 +00:00
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cadence_spi_write_speed(bus, hz);
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2014-11-07 11:37:49 +00:00
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for (i = 0; i < CQSPI_READ_CAPTURE_MAX_DELAY; i++) {
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/* Disable QSPI */
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cadence_qspi_apb_controller_disable(base);
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/* reconfigure the read data capture delay register */
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cadence_qspi_apb_readdata_capture(base, 1, i);
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/* Enable back QSPI */
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cadence_qspi_apb_controller_enable(base);
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/* issue a RDID to get the ID value */
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2022-08-24 11:38:47 +00:00
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err = cadence_spi_read_id(priv, 3, (u8 *)&temp);
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2014-11-07 11:37:49 +00:00
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if (err) {
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puts("SF: Calibration failed (read)\n");
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return err;
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}
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/* search for range lo */
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if (range_lo == -1 && temp == idcode) {
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range_lo = i;
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continue;
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}
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/* search for range hi */
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if (range_lo != -1 && temp != idcode) {
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range_hi = i - 1;
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break;
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}
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range_hi = i;
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}
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if (range_lo == -1) {
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puts("SF: Calibration failed (low range)\n");
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return err;
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}
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/* Disable QSPI for subsequent initialization */
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cadence_qspi_apb_controller_disable(base);
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/* configure the final value for read data capture delay register */
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cadence_qspi_apb_readdata_capture(base, 1, (range_hi + range_lo) / 2);
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debug("SF: Read data capture delay calibrated to %i (%i - %i)\n",
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(range_hi + range_lo) / 2, range_lo, range_hi);
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/* just to ensure we do once only when speed or chip select change */
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2015-10-17 13:31:55 +00:00
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priv->qspi_calibrated_hz = hz;
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2014-11-07 11:37:49 +00:00
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priv->qspi_calibrated_cs = spi_chip_select(bus);
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return 0;
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}
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static int cadence_spi_set_speed(struct udevice *bus, uint hz)
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{
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struct cadence_spi_priv *priv = dev_get_priv(bus);
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int err;
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2022-08-24 11:38:47 +00:00
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if (!hz || hz > priv->max_hz)
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hz = priv->max_hz;
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2014-11-07 11:37:49 +00:00
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/* Disable QSPI */
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cadence_qspi_apb_controller_disable(priv->regbase);
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2015-10-17 13:31:55 +00:00
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/*
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2021-06-25 19:17:07 +00:00
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* If the device tree already provides a read delay value, use that
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* instead of calibrating.
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2015-10-17 13:31:55 +00:00
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*/
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2022-08-24 11:38:47 +00:00
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if (priv->read_delay >= 0) {
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2021-06-25 19:17:07 +00:00
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cadence_spi_write_speed(bus, hz);
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cadence_qspi_apb_readdata_capture(priv->regbase, 1,
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2022-08-24 11:38:47 +00:00
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priv->read_delay);
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2021-06-25 19:17:07 +00:00
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} else if (priv->previous_hz != hz ||
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priv->qspi_calibrated_hz != hz ||
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priv->qspi_calibrated_cs != spi_chip_select(bus)) {
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/*
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* Calibration required for different current SCLK speed,
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* requested SCLK speed or chip select
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*/
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2015-10-17 13:31:55 +00:00
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err = spi_calibration(bus, hz);
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2014-11-07 11:37:49 +00:00
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if (err)
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return err;
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2015-10-17 13:31:55 +00:00
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/* prevent calibration run when same as previous request */
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priv->previous_hz = hz;
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2014-11-07 11:37:49 +00:00
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}
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/* Enable QSPI */
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cadence_qspi_apb_controller_enable(priv->regbase);
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debug("%s: speed=%d\n", __func__, hz);
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return 0;
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}
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static int cadence_spi_probe(struct udevice *bus)
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{
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2020-12-23 02:30:28 +00:00
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struct cadence_spi_plat *plat = dev_get_plat(bus);
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2014-11-07 11:37:49 +00:00
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struct cadence_spi_priv *priv = dev_get_priv(bus);
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2020-02-24 07:10:51 +00:00
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struct clk clk;
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2019-03-01 19:12:35 +00:00
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int ret;
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2014-11-07 11:37:49 +00:00
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2022-08-24 11:38:47 +00:00
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priv->regbase = plat->regbase;
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priv->ahbbase = plat->ahbbase;
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priv->is_dma = plat->is_dma;
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priv->is_decoded_cs = plat->is_decoded_cs;
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priv->fifo_depth = plat->fifo_depth;
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priv->fifo_width = plat->fifo_width;
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priv->trigger_address = plat->trigger_address;
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priv->read_delay = plat->read_delay;
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priv->ahbsize = plat->ahbsize;
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priv->max_hz = plat->max_hz;
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priv->page_size = plat->page_size;
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priv->block_size = plat->block_size;
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priv->tshsl_ns = plat->tshsl_ns;
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priv->tsd2d_ns = plat->tsd2d_ns;
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priv->tchsh_ns = plat->tchsh_ns;
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priv->tslch_ns = plat->tslch_ns;
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2014-11-07 11:37:49 +00:00
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2023-02-05 22:44:33 +00:00
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if (IS_ENABLED(CONFIG_ZYNQMP_FIRMWARE))
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2022-05-12 10:05:34 +00:00
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xilinx_pm_request(PM_REQUEST_NODE, PM_DEV_OSPI,
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ZYNQMP_PM_CAPABILITY_ACCESS, ZYNQMP_PM_MAX_QOS,
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ZYNQMP_PM_REQUEST_ACK_NO, NULL);
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2022-08-24 11:38:47 +00:00
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if (priv->ref_clk_hz == 0) {
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2020-02-24 07:10:51 +00:00
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ret = clk_get_by_index(bus, 0, &clk);
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if (ret) {
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2022-03-30 22:07:23 +00:00
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#ifdef CONFIG_HAS_CQSPI_REF_CLK
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2022-08-24 11:38:47 +00:00
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priv->ref_clk_hz = CONFIG_CQSPI_REF_CLK;
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2022-03-30 22:07:23 +00:00
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#elif defined(CONFIG_ARCH_SOCFPGA)
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2022-08-24 11:38:47 +00:00
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priv->ref_clk_hz = cm_get_qspi_controller_clk_hz();
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2020-02-24 07:10:51 +00:00
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#else
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return ret;
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#endif
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} else {
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2022-08-24 11:38:47 +00:00
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priv->ref_clk_hz = clk_get_rate(&clk);
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2020-02-24 07:10:51 +00:00
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clk_free(&clk);
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2022-08-24 11:38:47 +00:00
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if (IS_ERR_VALUE(priv->ref_clk_hz))
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return priv->ref_clk_hz;
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2020-02-24 07:10:51 +00:00
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}
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}
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2022-02-22 16:23:25 +00:00
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priv->resets = devm_reset_bulk_get_optional(bus);
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if (priv->resets)
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reset_deassert_bulk(priv->resets);
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2019-03-01 19:12:35 +00:00
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2014-11-07 11:37:49 +00:00
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if (!priv->qspi_is_init) {
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2022-08-24 11:38:47 +00:00
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cadence_qspi_apb_controller_init(priv);
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2014-11-07 11:37:49 +00:00
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priv->qspi_is_init = 1;
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}
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2022-08-24 11:38:47 +00:00
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priv->wr_delay = 50 * DIV_ROUND_UP(NSEC_PER_SEC, priv->ref_clk_hz);
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2021-06-25 19:17:08 +00:00
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2023-06-14 12:04:52 +00:00
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/* Versal and Versal-NET use spi calibration to set read delay */
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if (CONFIG_IS_ENABLED(ARCH_VERSAL) ||
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CONFIG_IS_ENABLED(ARCH_VERSAL_NET))
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2022-08-24 11:38:47 +00:00
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if (priv->read_delay >= 0)
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priv->read_delay = -1;
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2022-05-12 10:05:33 +00:00
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2023-06-14 12:04:52 +00:00
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/* Reset ospi flash device */
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return cadence_qspi_versal_flash_reset(bus);
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2014-11-07 11:37:49 +00:00
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}
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2019-03-01 19:12:35 +00:00
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static int cadence_spi_remove(struct udevice *dev)
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{
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struct cadence_spi_priv *priv = dev_get_priv(dev);
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2022-02-22 16:23:25 +00:00
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int ret = 0;
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2019-03-01 19:12:35 +00:00
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2022-02-22 16:23:25 +00:00
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if (priv->resets)
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ret = reset_release_bulk(priv->resets);
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return ret;
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2019-03-01 19:12:35 +00:00
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}
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2014-11-07 11:37:49 +00:00
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static int cadence_spi_set_mode(struct udevice *bus, uint mode)
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{
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struct cadence_spi_priv *priv = dev_get_priv(bus);
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/* Disable QSPI */
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cadence_qspi_apb_controller_disable(priv->regbase);
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/* Set SPI mode */
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2016-11-29 12:58:31 +00:00
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cadence_qspi_apb_set_clk_mode(priv->regbase, mode);
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2014-11-07 11:37:49 +00:00
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2020-01-27 05:06:40 +00:00
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/* Enable Direct Access Controller */
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2022-08-24 11:38:47 +00:00
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if (priv->use_dac_mode)
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2020-01-27 05:06:40 +00:00
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cadence_qspi_apb_dac_mode_enable(priv->regbase);
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2014-11-07 11:37:49 +00:00
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|
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/* Enable QSPI */
|
|
|
|
cadence_qspi_apb_controller_enable(priv->regbase);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2020-01-27 05:06:39 +00:00
|
|
|
static int cadence_spi_mem_exec_op(struct spi_slave *spi,
|
|
|
|
const struct spi_mem_op *op)
|
2014-11-07 11:37:49 +00:00
|
|
|
{
|
2020-01-27 05:06:39 +00:00
|
|
|
struct udevice *bus = spi->dev->parent;
|
2014-11-07 11:37:49 +00:00
|
|
|
struct cadence_spi_priv *priv = dev_get_priv(bus);
|
|
|
|
void *base = priv->regbase;
|
|
|
|
int err = 0;
|
2020-01-27 05:06:39 +00:00
|
|
|
u32 mode;
|
2014-11-07 11:37:49 +00:00
|
|
|
|
|
|
|
/* Set Chip select */
|
2020-01-27 05:06:39 +00:00
|
|
|
cadence_qspi_apb_chipselect(base, spi_chip_select(spi->dev),
|
2022-08-24 11:38:47 +00:00
|
|
|
priv->is_decoded_cs);
|
2014-11-07 11:37:49 +00:00
|
|
|
|
2020-01-27 05:06:39 +00:00
|
|
|
if (op->data.dir == SPI_MEM_DATA_IN && op->data.buf.in) {
|
2023-01-03 06:31:12 +00:00
|
|
|
/*
|
|
|
|
* Performing reads in DAC mode forces to read minimum 4 bytes
|
|
|
|
* which is unsupported on some flash devices during register
|
|
|
|
* reads, prefer STIG mode for such small reads.
|
|
|
|
*/
|
2023-04-12 10:58:55 +00:00
|
|
|
if (op->data.nbytes <= CQSPI_STIG_DATA_LEN_MAX)
|
2020-01-27 05:06:39 +00:00
|
|
|
mode = CQSPI_STIG_READ;
|
|
|
|
else
|
2020-01-27 05:06:40 +00:00
|
|
|
mode = CQSPI_READ;
|
2020-01-27 05:06:39 +00:00
|
|
|
} else {
|
2023-04-12 10:58:55 +00:00
|
|
|
if (op->data.nbytes <= CQSPI_STIG_DATA_LEN_MAX)
|
2020-01-27 05:06:39 +00:00
|
|
|
mode = CQSPI_STIG_WRITE;
|
|
|
|
else
|
2020-01-27 05:06:40 +00:00
|
|
|
mode = CQSPI_WRITE;
|
2020-01-27 05:06:39 +00:00
|
|
|
}
|
2014-11-07 11:37:49 +00:00
|
|
|
|
2020-01-27 05:06:39 +00:00
|
|
|
switch (mode) {
|
|
|
|
case CQSPI_STIG_READ:
|
2022-08-24 11:38:47 +00:00
|
|
|
err = cadence_qspi_apb_command_read_setup(priv, op);
|
2021-06-25 19:17:09 +00:00
|
|
|
if (!err)
|
2022-08-24 11:38:47 +00:00
|
|
|
err = cadence_qspi_apb_command_read(priv, op);
|
2014-11-07 11:37:49 +00:00
|
|
|
break;
|
2020-01-27 05:06:39 +00:00
|
|
|
case CQSPI_STIG_WRITE:
|
2022-08-24 11:38:47 +00:00
|
|
|
err = cadence_qspi_apb_command_write_setup(priv, op);
|
2021-06-25 19:17:09 +00:00
|
|
|
if (!err)
|
2022-08-24 11:38:47 +00:00
|
|
|
err = cadence_qspi_apb_command_write(priv, op);
|
2014-11-07 11:37:49 +00:00
|
|
|
break;
|
2020-01-27 05:06:40 +00:00
|
|
|
case CQSPI_READ:
|
2022-08-24 11:38:47 +00:00
|
|
|
err = cadence_qspi_apb_read_setup(priv, op);
|
2022-05-12 10:05:32 +00:00
|
|
|
if (!err) {
|
2022-08-24 11:38:47 +00:00
|
|
|
if (priv->is_dma)
|
|
|
|
err = cadence_qspi_apb_dma_read(priv, op);
|
2022-05-12 10:05:32 +00:00
|
|
|
else
|
2022-08-24 11:38:47 +00:00
|
|
|
err = cadence_qspi_apb_read_execute(priv, op);
|
2022-05-12 10:05:32 +00:00
|
|
|
}
|
2020-01-27 05:06:39 +00:00
|
|
|
break;
|
2020-01-27 05:06:40 +00:00
|
|
|
case CQSPI_WRITE:
|
2022-08-24 11:38:47 +00:00
|
|
|
err = cadence_qspi_apb_write_setup(priv, op);
|
2020-01-27 05:06:40 +00:00
|
|
|
if (!err)
|
2022-08-24 11:38:47 +00:00
|
|
|
err = cadence_qspi_apb_write_execute(priv, op);
|
2020-01-27 05:06:39 +00:00
|
|
|
break;
|
|
|
|
default:
|
|
|
|
err = -1;
|
|
|
|
break;
|
2014-11-07 11:37:49 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
return err;
|
|
|
|
}
|
|
|
|
|
2021-06-25 19:17:09 +00:00
|
|
|
static bool cadence_spi_mem_supports_op(struct spi_slave *slave,
|
|
|
|
const struct spi_mem_op *op)
|
|
|
|
{
|
|
|
|
bool all_true, all_false;
|
|
|
|
|
2023-04-12 10:58:54 +00:00
|
|
|
/*
|
|
|
|
* op->dummy.dtr is required for converting nbytes into ncycles.
|
|
|
|
* Also, don't check the dtr field of the op phase having zero nbytes.
|
|
|
|
*/
|
|
|
|
all_true = op->cmd.dtr &&
|
|
|
|
(!op->addr.nbytes || op->addr.dtr) &&
|
|
|
|
(!op->dummy.nbytes || op->dummy.dtr) &&
|
|
|
|
(!op->data.nbytes || op->data.dtr);
|
|
|
|
|
2021-06-25 19:17:09 +00:00
|
|
|
all_false = !op->cmd.dtr && !op->addr.dtr && !op->dummy.dtr &&
|
|
|
|
!op->data.dtr;
|
|
|
|
|
|
|
|
/* Mixed DTR modes not supported. */
|
|
|
|
if (!(all_true || all_false))
|
|
|
|
return false;
|
|
|
|
|
|
|
|
if (all_true)
|
|
|
|
return spi_mem_dtr_supports_op(slave, op);
|
|
|
|
else
|
|
|
|
return spi_mem_default_supports_op(slave, op);
|
|
|
|
}
|
|
|
|
|
2020-12-03 23:55:21 +00:00
|
|
|
static int cadence_spi_of_to_plat(struct udevice *bus)
|
2014-11-07 11:37:49 +00:00
|
|
|
{
|
2020-12-23 02:30:28 +00:00
|
|
|
struct cadence_spi_plat *plat = dev_get_plat(bus);
|
2022-08-24 11:38:47 +00:00
|
|
|
struct cadence_spi_priv *priv = dev_get_priv(bus);
|
2019-05-09 20:11:56 +00:00
|
|
|
ofnode subnode;
|
2014-11-07 11:37:49 +00:00
|
|
|
|
2023-03-13 00:32:31 +00:00
|
|
|
plat->regbase = devfdt_get_addr_index_ptr(bus, 0);
|
2023-03-13 00:32:18 +00:00
|
|
|
plat->ahbbase = devfdt_get_addr_size_index_ptr(bus, 1, &plat->ahbsize);
|
2019-05-09 20:11:56 +00:00
|
|
|
plat->is_decoded_cs = dev_read_bool(bus, "cdns,is-decoded-cs");
|
|
|
|
plat->fifo_depth = dev_read_u32_default(bus, "cdns,fifo-depth", 128);
|
|
|
|
plat->fifo_width = dev_read_u32_default(bus, "cdns,fifo-width", 4);
|
|
|
|
plat->trigger_address = dev_read_u32_default(bus,
|
|
|
|
"cdns,trigger-address",
|
|
|
|
0);
|
2020-01-27 05:06:40 +00:00
|
|
|
/* Use DAC mode only when MMIO window is at least 8M wide */
|
|
|
|
if (plat->ahbsize >= SZ_8M)
|
2022-08-24 11:38:47 +00:00
|
|
|
priv->use_dac_mode = true;
|
2014-11-07 11:37:49 +00:00
|
|
|
|
2022-05-12 10:05:32 +00:00
|
|
|
plat->is_dma = dev_read_bool(bus, "cdns,is-dma");
|
|
|
|
|
2022-12-09 01:39:50 +00:00
|
|
|
/* All other parameters are embedded in the child node */
|
2019-05-09 20:11:56 +00:00
|
|
|
subnode = dev_read_first_subnode(bus);
|
|
|
|
if (!ofnode_valid(subnode)) {
|
2014-11-07 11:37:49 +00:00
|
|
|
printf("Error: subnode with SPI flash config missing!\n");
|
|
|
|
return -ENODEV;
|
|
|
|
}
|
|
|
|
|
2015-10-17 13:32:14 +00:00
|
|
|
/* Use 500 KHz as a suitable default */
|
2019-05-09 20:11:56 +00:00
|
|
|
plat->max_hz = ofnode_read_u32_default(subnode, "spi-max-frequency",
|
|
|
|
500000);
|
2015-10-17 13:32:14 +00:00
|
|
|
|
2014-11-07 11:37:49 +00:00
|
|
|
/* Read other parameters from DT */
|
2019-05-09 20:11:56 +00:00
|
|
|
plat->page_size = ofnode_read_u32_default(subnode, "page-size", 256);
|
|
|
|
plat->block_size = ofnode_read_u32_default(subnode, "block-size", 16);
|
|
|
|
plat->tshsl_ns = ofnode_read_u32_default(subnode, "cdns,tshsl-ns",
|
|
|
|
200);
|
|
|
|
plat->tsd2d_ns = ofnode_read_u32_default(subnode, "cdns,tsd2d-ns",
|
|
|
|
255);
|
|
|
|
plat->tchsh_ns = ofnode_read_u32_default(subnode, "cdns,tchsh-ns", 20);
|
|
|
|
plat->tslch_ns = ofnode_read_u32_default(subnode, "cdns,tslch-ns", 20);
|
2021-06-25 19:17:07 +00:00
|
|
|
/*
|
|
|
|
* Read delay should be an unsigned value but we use a signed integer
|
|
|
|
* so that negative values can indicate that the device tree did not
|
|
|
|
* specify any signed values and we need to perform the calibration
|
|
|
|
* sequence to find it out.
|
|
|
|
*/
|
|
|
|
plat->read_delay = ofnode_read_s32_default(subnode, "cdns,read-delay",
|
|
|
|
-1);
|
2014-11-07 11:37:49 +00:00
|
|
|
|
|
|
|
debug("%s: regbase=%p ahbbase=%p max-frequency=%d page-size=%d\n",
|
|
|
|
__func__, plat->regbase, plat->ahbbase, plat->max_hz,
|
|
|
|
plat->page_size);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2020-01-27 05:06:39 +00:00
|
|
|
static const struct spi_controller_mem_ops cadence_spi_mem_ops = {
|
|
|
|
.exec_op = cadence_spi_mem_exec_op,
|
2021-06-25 19:17:09 +00:00
|
|
|
.supports_op = cadence_spi_mem_supports_op,
|
2020-01-27 05:06:39 +00:00
|
|
|
};
|
|
|
|
|
2014-11-07 11:37:49 +00:00
|
|
|
static const struct dm_spi_ops cadence_spi_ops = {
|
|
|
|
.set_speed = cadence_spi_set_speed,
|
|
|
|
.set_mode = cadence_spi_set_mode,
|
2020-01-27 05:06:39 +00:00
|
|
|
.mem_ops = &cadence_spi_mem_ops,
|
2014-11-07 11:37:49 +00:00
|
|
|
/*
|
|
|
|
* cs_info is not needed, since we require all chip selects to be
|
|
|
|
* in the device tree explicitly
|
|
|
|
*/
|
|
|
|
};
|
|
|
|
|
|
|
|
static const struct udevice_id cadence_spi_ids[] = {
|
2018-11-02 10:54:51 +00:00
|
|
|
{ .compatible = "cdns,qspi-nor" },
|
2019-12-05 10:16:07 +00:00
|
|
|
{ .compatible = "ti,am654-ospi" },
|
2014-11-07 11:37:49 +00:00
|
|
|
{ }
|
|
|
|
};
|
|
|
|
|
|
|
|
U_BOOT_DRIVER(cadence_spi) = {
|
|
|
|
.name = "cadence_spi",
|
|
|
|
.id = UCLASS_SPI,
|
|
|
|
.of_match = cadence_spi_ids,
|
|
|
|
.ops = &cadence_spi_ops,
|
2020-12-03 23:55:21 +00:00
|
|
|
.of_to_plat = cadence_spi_of_to_plat,
|
2020-12-03 23:55:23 +00:00
|
|
|
.plat_auto = sizeof(struct cadence_spi_plat),
|
2020-12-03 23:55:17 +00:00
|
|
|
.priv_auto = sizeof(struct cadence_spi_priv),
|
2014-11-07 11:37:49 +00:00
|
|
|
.probe = cadence_spi_probe,
|
2019-03-01 19:12:35 +00:00
|
|
|
.remove = cadence_spi_remove,
|
|
|
|
.flags = DM_FLAG_OS_PREPARE,
|
2014-11-07 11:37:49 +00:00
|
|
|
};
|