2018-05-06 21:58:06 +00:00
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// SPDX-License-Identifier: GPL-2.0+
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2018-01-20 01:13:38 +00:00
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/*
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* Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
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*
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* Derived from linux/drivers/spi/spi-bcm63xx-hsspi.c:
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* Copyright (C) 2000-2010 Broadcom Corporation
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* Copyright (C) 2012-2013 Jonas Gorski <jogo@openwrt.org>
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*/
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#include <common.h>
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#include <clk.h>
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#include <dm.h>
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2020-05-10 17:40:05 +00:00
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#include <log.h>
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2020-02-03 14:36:16 +00:00
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#include <malloc.h>
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2018-01-20 01:13:38 +00:00
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#include <spi.h>
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#include <reset.h>
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#include <wait_bit.h>
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#include <asm/io.h>
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2020-05-10 17:40:13 +00:00
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#include <linux/bitops.h>
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2018-01-20 01:13:38 +00:00
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#define HSSPI_PP 0
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2023-06-07 23:37:04 +00:00
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/*
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* The maximum frequency for SPI synchronous mode is 30MHz for some chips and
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* 25MHz for some others. This depends on the chip layout and SPI signals
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* distance to the pad. We use the lower of these values to cover all relevant
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* chips.
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*/
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#define SPI_MAX_SYNC_CLOCK 25000000
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2018-01-20 01:13:38 +00:00
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/* SPI Control register */
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#define SPI_CTL_REG 0x000
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#define SPI_CTL_CS_POL_SHIFT 0
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#define SPI_CTL_CS_POL_MASK (0xff << SPI_CTL_CS_POL_SHIFT)
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#define SPI_CTL_CLK_GATE_SHIFT 16
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#define SPI_CTL_CLK_GATE_MASK (1 << SPI_CTL_CLK_GATE_SHIFT)
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#define SPI_CTL_CLK_POL_SHIFT 17
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#define SPI_CTL_CLK_POL_MASK (1 << SPI_CTL_CLK_POL_SHIFT)
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/* SPI Interrupts registers */
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#define SPI_IR_STAT_REG 0x008
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#define SPI_IR_ST_MASK_REG 0x00c
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#define SPI_IR_MASK_REG 0x010
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#define SPI_IR_CLEAR_ALL 0xff001f1f
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/* SPI Ping-Pong Command registers */
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#define SPI_CMD_REG (0x080 + (0x40 * (HSSPI_PP)) + 0x00)
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#define SPI_CMD_OP_SHIFT 0
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#define SPI_CMD_OP_START (0x1 << SPI_CMD_OP_SHIFT)
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#define SPI_CMD_PFL_SHIFT 8
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#define SPI_CMD_PFL_MASK (0x7 << SPI_CMD_PFL_SHIFT)
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#define SPI_CMD_SLAVE_SHIFT 12
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#define SPI_CMD_SLAVE_MASK (0x7 << SPI_CMD_SLAVE_SHIFT)
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/* SPI Ping-Pong Status registers */
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#define SPI_STAT_REG (0x080 + (0x40 * (HSSPI_PP)) + 0x04)
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#define SPI_STAT_SRCBUSY_SHIFT 1
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#define SPI_STAT_SRCBUSY_MASK (1 << SPI_STAT_SRCBUSY_SHIFT)
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/* SPI Profile Clock registers */
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#define SPI_PFL_CLK_REG(x) (0x100 + (0x20 * (x)) + 0x00)
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#define SPI_PFL_CLK_FREQ_SHIFT 0
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#define SPI_PFL_CLK_FREQ_MASK (0x3fff << SPI_PFL_CLK_FREQ_SHIFT)
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#define SPI_PFL_CLK_RSTLOOP_SHIFT 15
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#define SPI_PFL_CLK_RSTLOOP_MASK (1 << SPI_PFL_CLK_RSTLOOP_SHIFT)
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/* SPI Profile Signal registers */
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#define SPI_PFL_SIG_REG(x) (0x100 + (0x20 * (x)) + 0x04)
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#define SPI_PFL_SIG_LATCHRIS_SHIFT 12
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#define SPI_PFL_SIG_LATCHRIS_MASK (1 << SPI_PFL_SIG_LATCHRIS_SHIFT)
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#define SPI_PFL_SIG_LAUNCHRIS_SHIFT 13
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#define SPI_PFL_SIG_LAUNCHRIS_MASK (1 << SPI_PFL_SIG_LAUNCHRIS_SHIFT)
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#define SPI_PFL_SIG_ASYNCIN_SHIFT 16
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#define SPI_PFL_SIG_ASYNCIN_MASK (1 << SPI_PFL_SIG_ASYNCIN_SHIFT)
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/* SPI Profile Mode registers */
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#define SPI_PFL_MODE_REG(x) (0x100 + (0x20 * (x)) + 0x08)
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#define SPI_PFL_MODE_FILL_SHIFT 0
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#define SPI_PFL_MODE_FILL_MASK (0xff << SPI_PFL_MODE_FILL_SHIFT)
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2023-06-07 23:37:04 +00:00
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#define SPI_PFL_MODE_MDRDST_SHIFT 8
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#define SPI_PFL_MODE_MDWRST_SHIFT 12
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2018-01-20 01:13:38 +00:00
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#define SPI_PFL_MODE_MDRDSZ_SHIFT 16
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#define SPI_PFL_MODE_MDRDSZ_MASK (1 << SPI_PFL_MODE_MDRDSZ_SHIFT)
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#define SPI_PFL_MODE_MDWRSZ_SHIFT 18
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#define SPI_PFL_MODE_MDWRSZ_MASK (1 << SPI_PFL_MODE_MDWRSZ_SHIFT)
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#define SPI_PFL_MODE_3WIRE_SHIFT 20
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#define SPI_PFL_MODE_3WIRE_MASK (1 << SPI_PFL_MODE_3WIRE_SHIFT)
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2023-06-07 23:37:04 +00:00
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#define SPI_PFL_MODE_PREPCNT_SHIFT 24
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#define SPI_PFL_MODE_PREPCNT_MASK (4 << SPI_PFL_MODE_PREPCNT_SHIFT)
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2018-01-20 01:13:38 +00:00
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/* SPI Ping-Pong FIFO registers */
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#define HSSPI_FIFO_SIZE 0x200
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#define HSSPI_FIFO_BASE (0x200 + \
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(HSSPI_FIFO_SIZE * HSSPI_PP))
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/* SPI Ping-Pong FIFO OP register */
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#define HSSPI_FIFO_OP_SIZE 0x2
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#define HSSPI_FIFO_OP_REG (HSSPI_FIFO_BASE + 0x00)
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#define HSSPI_FIFO_OP_BYTES_SHIFT 0
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#define HSSPI_FIFO_OP_BYTES_MASK (0x3ff << HSSPI_FIFO_OP_BYTES_SHIFT)
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#define HSSPI_FIFO_OP_MBIT_SHIFT 11
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#define HSSPI_FIFO_OP_MBIT_MASK (1 << HSSPI_FIFO_OP_MBIT_SHIFT)
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#define HSSPI_FIFO_OP_CODE_SHIFT 13
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#define HSSPI_FIFO_OP_READ_WRITE (1 << HSSPI_FIFO_OP_CODE_SHIFT)
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#define HSSPI_FIFO_OP_CODE_W (2 << HSSPI_FIFO_OP_CODE_SHIFT)
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#define HSSPI_FIFO_OP_CODE_R (3 << HSSPI_FIFO_OP_CODE_SHIFT)
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2023-06-07 23:37:04 +00:00
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#define HSSPI_MAX_DATA_SIZE (HSSPI_FIFO_SIZE - HSSPI_FIFO_OP_SIZE)
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#define HSSPI_MAX_PREPEND_SIZE 15
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#define HSSPI_XFER_MODE_PREPEND 0
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#define HSSPI_XFER_MODE_DUMMYCS 1
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2018-01-20 01:13:38 +00:00
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struct bcm63xx_hsspi_priv {
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void __iomem *regs;
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ulong clk_rate;
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uint8_t num_cs;
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uint8_t cs_pols;
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uint speed;
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2023-06-07 23:37:04 +00:00
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uint xfer_mode;
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uint32_t prepend_cnt;
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uint8_t prepend_buf[HSSPI_MAX_PREPEND_SIZE];
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2018-01-20 01:13:38 +00:00
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};
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static int bcm63xx_hsspi_cs_info(struct udevice *bus, uint cs,
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struct spi_cs_info *info)
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{
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struct bcm63xx_hsspi_priv *priv = dev_get_priv(bus);
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if (cs >= priv->num_cs) {
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printf("no cs %u\n", cs);
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2019-09-09 13:00:01 +00:00
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return -EINVAL;
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2018-01-20 01:13:38 +00:00
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}
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return 0;
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}
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static int bcm63xx_hsspi_set_mode(struct udevice *bus, uint mode)
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{
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struct bcm63xx_hsspi_priv *priv = dev_get_priv(bus);
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/* clock polarity */
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if (mode & SPI_CPOL)
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2019-08-14 13:18:34 +00:00
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setbits_32(priv->regs + SPI_CTL_REG, SPI_CTL_CLK_POL_MASK);
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2018-01-20 01:13:38 +00:00
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else
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2019-08-14 13:18:34 +00:00
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clrbits_32(priv->regs + SPI_CTL_REG, SPI_CTL_CLK_POL_MASK);
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2018-01-20 01:13:38 +00:00
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return 0;
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}
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static int bcm63xx_hsspi_set_speed(struct udevice *bus, uint speed)
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{
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struct bcm63xx_hsspi_priv *priv = dev_get_priv(bus);
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priv->speed = speed;
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return 0;
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}
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static void bcm63xx_hsspi_activate_cs(struct bcm63xx_hsspi_priv *priv,
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2020-12-03 23:55:23 +00:00
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struct dm_spi_slave_plat *plat)
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2018-01-20 01:13:38 +00:00
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{
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uint32_t clr, set;
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2023-06-07 23:37:04 +00:00
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uint speed = priv->speed;
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if (priv->xfer_mode == HSSPI_XFER_MODE_DUMMYCS &&
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speed > SPI_MAX_SYNC_CLOCK) {
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speed = SPI_MAX_SYNC_CLOCK;
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debug("Force to dummy cs mode. Reduce the speed to %dHz\n", speed);
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}
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2018-01-20 01:13:38 +00:00
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/* profile clock */
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2023-06-07 23:37:04 +00:00
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set = DIV_ROUND_UP(priv->clk_rate, speed);
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2018-01-20 01:13:38 +00:00
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set = DIV_ROUND_UP(2048, set);
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set &= SPI_PFL_CLK_FREQ_MASK;
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set |= SPI_PFL_CLK_RSTLOOP_MASK;
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2019-08-14 13:18:34 +00:00
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writel(set, priv->regs + SPI_PFL_CLK_REG(plat->cs));
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2018-01-20 01:13:38 +00:00
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/* profile signal */
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set = 0;
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clr = SPI_PFL_SIG_LAUNCHRIS_MASK |
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SPI_PFL_SIG_LATCHRIS_MASK |
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SPI_PFL_SIG_ASYNCIN_MASK;
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/* latch/launch config */
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if (plat->mode & SPI_CPHA)
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set |= SPI_PFL_SIG_LAUNCHRIS_MASK;
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else
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set |= SPI_PFL_SIG_LATCHRIS_MASK;
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/* async clk */
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2023-06-07 23:37:04 +00:00
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if (speed > SPI_MAX_SYNC_CLOCK)
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2018-01-20 01:13:38 +00:00
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set |= SPI_PFL_SIG_ASYNCIN_MASK;
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2019-08-14 13:18:34 +00:00
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clrsetbits_32(priv->regs + SPI_PFL_SIG_REG(plat->cs), clr, set);
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2018-01-20 01:13:38 +00:00
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/* global control */
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set = 0;
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clr = 0;
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2023-06-07 23:37:04 +00:00
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if (priv->xfer_mode == HSSPI_XFER_MODE_PREPEND) {
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if (priv->cs_pols & BIT(plat->cs))
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set |= BIT(plat->cs);
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else
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clr |= BIT(plat->cs);
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} else {
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/* invert cs polarity */
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if (priv->cs_pols & BIT(plat->cs))
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clr |= BIT(plat->cs);
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else
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set |= BIT(plat->cs);
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/* invert dummy cs polarity */
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if (priv->cs_pols & BIT(!plat->cs))
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clr |= BIT(!plat->cs);
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else
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set |= BIT(!plat->cs);
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}
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2018-01-20 01:13:38 +00:00
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2019-08-14 13:18:34 +00:00
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clrsetbits_32(priv->regs + SPI_CTL_REG, clr, set);
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2018-01-20 01:13:38 +00:00
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}
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static void bcm63xx_hsspi_deactivate_cs(struct bcm63xx_hsspi_priv *priv)
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{
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/* restore cs polarities */
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2019-08-14 13:18:34 +00:00
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clrsetbits_32(priv->regs + SPI_CTL_REG, SPI_CTL_CS_POL_MASK,
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2018-01-20 01:13:38 +00:00
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priv->cs_pols);
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}
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/*
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* BCM63xx HSSPI driver doesn't allow keeping CS active between transfers
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* because they are controlled by HW.
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* However, it provides a mechanism to prepend write transfers prior to read
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* transfers (with a maximum prepend of 15 bytes), which is usually enough for
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* SPI-connected flashes since reading requires prepending a write transfer of
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* 5 bytes. On the other hand it also provides a way to invert each CS
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* polarity, not only between transfers like the older BCM63xx SPI driver, but
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* also the rest of the time.
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*
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* Instead of using the prepend mechanism, this implementation inverts the
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* polarity of both the desired CS and another dummy CS when the bus is
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* claimed. This way, the dummy CS is restored to its inactive value when
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* transfers are issued and the desired CS is preserved in its active value
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* all the time. This hack is also used in the upstream linux driver and
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2022-12-09 01:39:50 +00:00
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* allows keeping CS active between transfers even if the HW doesn't give
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2018-01-20 01:13:38 +00:00
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* this possibility.
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2023-06-07 23:37:04 +00:00
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*
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* This workaround only works when the dummy CS (usually CS1 when the actual
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* CS is 0) pinmuxed to SPI chip select function if SPI clock is faster than
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* SPI_MAX_SYNC_CLOCK. In old broadcom chip, CS1 pin is default to chip select
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* function. But this is not the case for new chips. To make this function
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* always work, it should be called with maximum clock of SPI_MAX_SYNC_CLOCK.
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2018-01-20 01:13:38 +00:00
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*/
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2023-06-07 23:37:04 +00:00
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static int bcm63xx_hsspi_xfer_dummy_cs(struct udevice *dev, unsigned int data_bytes,
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const void *dout, void *din, unsigned long flags)
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2018-01-20 01:13:38 +00:00
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{
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struct bcm63xx_hsspi_priv *priv = dev_get_priv(dev->parent);
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2020-12-03 23:55:23 +00:00
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struct dm_spi_slave_plat *plat = dev_get_parent_plat(dev);
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2018-01-20 01:13:38 +00:00
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size_t step_size = HSSPI_FIFO_SIZE;
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uint16_t opcode = 0;
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2023-06-07 23:37:02 +00:00
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uint32_t val = SPI_PFL_MODE_FILL_MASK;
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2018-01-20 01:13:38 +00:00
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const uint8_t *tx = dout;
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uint8_t *rx = din;
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if (flags & SPI_XFER_BEGIN)
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bcm63xx_hsspi_activate_cs(priv, plat);
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/* fifo operation */
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if (tx && rx)
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opcode = HSSPI_FIFO_OP_READ_WRITE;
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else if (rx)
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opcode = HSSPI_FIFO_OP_CODE_R;
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else if (tx)
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opcode = HSSPI_FIFO_OP_CODE_W;
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if (opcode != HSSPI_FIFO_OP_CODE_R)
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step_size -= HSSPI_FIFO_OP_SIZE;
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/* dual mode */
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2023-06-07 23:37:02 +00:00
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if ((opcode == HSSPI_FIFO_OP_CODE_R && (plat->mode & SPI_RX_DUAL)) ||
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(opcode == HSSPI_FIFO_OP_CODE_W && (plat->mode & SPI_TX_DUAL))) {
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2018-01-20 01:13:38 +00:00
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opcode |= HSSPI_FIFO_OP_MBIT_MASK;
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2023-06-07 23:37:02 +00:00
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/* profile mode */
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if (plat->mode & SPI_RX_DUAL)
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val |= SPI_PFL_MODE_MDRDSZ_MASK;
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if (plat->mode & SPI_TX_DUAL)
|
|
|
|
val |= SPI_PFL_MODE_MDWRSZ_MASK;
|
|
|
|
}
|
|
|
|
|
2018-01-20 01:13:38 +00:00
|
|
|
if (plat->mode & SPI_3WIRE)
|
|
|
|
val |= SPI_PFL_MODE_3WIRE_MASK;
|
2019-08-14 13:18:34 +00:00
|
|
|
writel(val, priv->regs + SPI_PFL_MODE_REG(plat->cs));
|
2018-01-20 01:13:38 +00:00
|
|
|
|
|
|
|
/* transfer loop */
|
|
|
|
while (data_bytes > 0) {
|
|
|
|
size_t curr_step = min(step_size, data_bytes);
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
/* copy tx data */
|
|
|
|
if (tx) {
|
|
|
|
memcpy_toio(priv->regs + HSSPI_FIFO_BASE +
|
|
|
|
HSSPI_FIFO_OP_SIZE, tx, curr_step);
|
|
|
|
tx += curr_step;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* set fifo operation */
|
2019-08-14 13:18:34 +00:00
|
|
|
writew(cpu_to_be16(opcode | (curr_step & HSSPI_FIFO_OP_BYTES_MASK)),
|
2018-01-20 01:13:38 +00:00
|
|
|
priv->regs + HSSPI_FIFO_OP_REG);
|
|
|
|
|
|
|
|
/* issue the transfer */
|
|
|
|
val = SPI_CMD_OP_START;
|
|
|
|
val |= (plat->cs << SPI_CMD_PFL_SHIFT) &
|
|
|
|
SPI_CMD_PFL_MASK;
|
|
|
|
val |= (!plat->cs << SPI_CMD_SLAVE_SHIFT) &
|
|
|
|
SPI_CMD_SLAVE_MASK;
|
2019-08-14 13:18:34 +00:00
|
|
|
writel(val, priv->regs + SPI_CMD_REG);
|
2018-01-20 01:13:38 +00:00
|
|
|
|
|
|
|
/* wait for completion */
|
2019-08-14 13:18:34 +00:00
|
|
|
ret = wait_for_bit_32(priv->regs + SPI_STAT_REG,
|
2018-01-20 01:13:38 +00:00
|
|
|
SPI_STAT_SRCBUSY_MASK, false,
|
|
|
|
1000, false);
|
|
|
|
if (ret) {
|
|
|
|
printf("interrupt timeout\n");
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* copy rx data */
|
|
|
|
if (rx) {
|
|
|
|
memcpy_fromio(rx, priv->regs + HSSPI_FIFO_BASE,
|
|
|
|
curr_step);
|
|
|
|
rx += curr_step;
|
|
|
|
}
|
|
|
|
|
|
|
|
data_bytes -= curr_step;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (flags & SPI_XFER_END)
|
|
|
|
bcm63xx_hsspi_deactivate_cs(priv);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2023-06-07 23:37:04 +00:00
|
|
|
static int bcm63xx_prepare_prepend_transfer(struct bcm63xx_hsspi_priv *priv,
|
|
|
|
unsigned int data_bytes, const void *dout, void *din,
|
|
|
|
unsigned long flags)
|
|
|
|
{
|
|
|
|
/*
|
|
|
|
* only support multiple half duplex write transfer + optional
|
|
|
|
* full duplex read/write at the end.
|
|
|
|
*/
|
|
|
|
if (flags & SPI_XFER_BEGIN) {
|
|
|
|
/* clear prepends */
|
|
|
|
priv->prepend_cnt = 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (din) {
|
|
|
|
/* buffering reads not possible for prepend mode */
|
|
|
|
if (!(flags & SPI_XFER_END)) {
|
|
|
|
debug("unable to buffer reads\n");
|
|
|
|
return HSSPI_XFER_MODE_DUMMYCS;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* check rx size */
|
|
|
|
if (data_bytes > HSSPI_MAX_DATA_SIZE) {
|
|
|
|
debug("max rx bytes exceeded\n");
|
|
|
|
return HSSPI_XFER_MODE_DUMMYCS;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
if (dout) {
|
|
|
|
/* check tx size */
|
|
|
|
if (flags & SPI_XFER_END) {
|
|
|
|
if (priv->prepend_cnt + data_bytes > HSSPI_MAX_DATA_SIZE) {
|
|
|
|
debug("max tx bytes exceeded\n");
|
|
|
|
return HSSPI_XFER_MODE_DUMMYCS;
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
if (priv->prepend_cnt + data_bytes > HSSPI_MAX_PREPEND_SIZE) {
|
|
|
|
debug("max prepend bytes exceeded\n");
|
|
|
|
return HSSPI_XFER_MODE_DUMMYCS;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* buffer transfer data in the prepend buf in case we have to fall
|
|
|
|
* back to dummy cs mode.
|
|
|
|
*/
|
|
|
|
memcpy(&priv->prepend_buf[priv->prepend_cnt], dout, data_bytes);
|
|
|
|
priv->prepend_cnt += data_bytes;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return HSSPI_XFER_MODE_PREPEND;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int bcm63xx_hsspi_xfer_prepend(struct udevice *dev, unsigned int data_bytes,
|
|
|
|
const void *dout, void *din, unsigned long flags)
|
|
|
|
{
|
|
|
|
struct bcm63xx_hsspi_priv *priv = dev_get_priv(dev->parent);
|
|
|
|
struct dm_spi_slave_plat *plat = dev_get_parent_plat(dev);
|
|
|
|
uint16_t opcode = 0;
|
|
|
|
uint32_t val, offset;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
if (flags & SPI_XFER_END) {
|
|
|
|
offset = HSSPI_FIFO_BASE + HSSPI_FIFO_OP_SIZE;
|
|
|
|
if (priv->prepend_cnt) {
|
|
|
|
/* copy prepend data */
|
|
|
|
memcpy_toio(priv->regs + offset,
|
|
|
|
priv->prepend_buf, priv->prepend_cnt);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (dout && data_bytes) {
|
|
|
|
/* copy tx data */
|
|
|
|
offset += priv->prepend_cnt;
|
|
|
|
memcpy_toio(priv->regs + offset, dout, data_bytes);
|
|
|
|
}
|
|
|
|
|
|
|
|
bcm63xx_hsspi_activate_cs(priv, plat);
|
|
|
|
if (dout && !din) {
|
|
|
|
/* all half-duplex write. merge to single write */
|
|
|
|
data_bytes += priv->prepend_cnt;
|
|
|
|
opcode = HSSPI_FIFO_OP_CODE_W;
|
|
|
|
priv->prepend_cnt = 0;
|
|
|
|
} else if (!dout && din) {
|
|
|
|
/* half-duplex read with prepend write */
|
|
|
|
opcode = HSSPI_FIFO_OP_CODE_R;
|
|
|
|
} else {
|
|
|
|
/* full duplex read/write */
|
|
|
|
opcode = HSSPI_FIFO_OP_READ_WRITE;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* profile mode */
|
|
|
|
val = SPI_PFL_MODE_FILL_MASK;
|
|
|
|
if (plat->mode & SPI_3WIRE)
|
|
|
|
val |= SPI_PFL_MODE_3WIRE_MASK;
|
|
|
|
|
|
|
|
/* dual mode */
|
|
|
|
if ((opcode == HSSPI_FIFO_OP_CODE_R && (plat->mode & SPI_RX_DUAL)) ||
|
|
|
|
(opcode == HSSPI_FIFO_OP_CODE_W && (plat->mode & SPI_TX_DUAL))) {
|
|
|
|
opcode |= HSSPI_FIFO_OP_MBIT_MASK;
|
|
|
|
|
|
|
|
if (plat->mode & SPI_RX_DUAL) {
|
|
|
|
val |= SPI_PFL_MODE_MDRDSZ_MASK;
|
|
|
|
val |= priv->prepend_cnt << SPI_PFL_MODE_MDRDST_SHIFT;
|
|
|
|
}
|
|
|
|
if (plat->mode & SPI_TX_DUAL) {
|
|
|
|
val |= SPI_PFL_MODE_MDWRSZ_MASK;
|
|
|
|
val |= priv->prepend_cnt << SPI_PFL_MODE_MDWRST_SHIFT;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
val |= (priv->prepend_cnt << SPI_PFL_MODE_PREPCNT_SHIFT);
|
|
|
|
writel(val, priv->regs + SPI_PFL_MODE_REG(plat->cs));
|
|
|
|
|
|
|
|
/* set fifo operation */
|
|
|
|
val = opcode | (data_bytes & HSSPI_FIFO_OP_BYTES_MASK);
|
|
|
|
writew(cpu_to_be16(val),
|
|
|
|
priv->regs + HSSPI_FIFO_OP_REG);
|
|
|
|
|
|
|
|
/* issue the transfer */
|
|
|
|
val = SPI_CMD_OP_START;
|
|
|
|
val |= (plat->cs << SPI_CMD_PFL_SHIFT) &
|
|
|
|
SPI_CMD_PFL_MASK;
|
|
|
|
val |= (plat->cs << SPI_CMD_SLAVE_SHIFT) &
|
|
|
|
SPI_CMD_SLAVE_MASK;
|
|
|
|
writel(val, priv->regs + SPI_CMD_REG);
|
|
|
|
|
|
|
|
/* wait for completion */
|
|
|
|
ret = wait_for_bit_32(priv->regs + SPI_STAT_REG,
|
|
|
|
SPI_STAT_SRCBUSY_MASK, false,
|
|
|
|
1000, false);
|
|
|
|
if (ret) {
|
|
|
|
bcm63xx_hsspi_deactivate_cs(priv);
|
|
|
|
printf("spi polling timeout\n");
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* copy rx data */
|
|
|
|
if (din)
|
|
|
|
memcpy_fromio(din, priv->regs + HSSPI_FIFO_BASE,
|
|
|
|
data_bytes);
|
|
|
|
bcm63xx_hsspi_deactivate_cs(priv);
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int bcm63xx_hsspi_xfer(struct udevice *dev, unsigned int bitlen,
|
|
|
|
const void *dout, void *din, unsigned long flags)
|
|
|
|
{
|
|
|
|
struct bcm63xx_hsspi_priv *priv = dev_get_priv(dev->parent);
|
|
|
|
int ret;
|
|
|
|
u32 data_bytes = bitlen >> 3;
|
|
|
|
|
|
|
|
if (priv->xfer_mode == HSSPI_XFER_MODE_PREPEND) {
|
|
|
|
priv->xfer_mode =
|
|
|
|
bcm63xx_prepare_prepend_transfer(priv, data_bytes, dout, din, flags);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* if not prependable, fall back to dummy cs mode with safe clock */
|
|
|
|
if (priv->xfer_mode == HSSPI_XFER_MODE_DUMMYCS) {
|
|
|
|
/* For pending prepend data from previous transfers, send it first */
|
|
|
|
if (priv->prepend_cnt) {
|
|
|
|
bcm63xx_hsspi_xfer_dummy_cs(dev, priv->prepend_cnt,
|
|
|
|
priv->prepend_buf, NULL,
|
|
|
|
(flags & ~SPI_XFER_END) | SPI_XFER_BEGIN);
|
|
|
|
priv->prepend_cnt = 0;
|
|
|
|
}
|
|
|
|
ret = bcm63xx_hsspi_xfer_dummy_cs(dev, data_bytes, dout, din, flags);
|
|
|
|
} else {
|
|
|
|
ret = bcm63xx_hsspi_xfer_prepend(dev, data_bytes, dout, din, flags);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (flags & SPI_XFER_END)
|
|
|
|
priv->xfer_mode = HSSPI_XFER_MODE_PREPEND;
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2018-01-20 01:13:38 +00:00
|
|
|
static const struct dm_spi_ops bcm63xx_hsspi_ops = {
|
|
|
|
.cs_info = bcm63xx_hsspi_cs_info,
|
|
|
|
.set_mode = bcm63xx_hsspi_set_mode,
|
|
|
|
.set_speed = bcm63xx_hsspi_set_speed,
|
|
|
|
.xfer = bcm63xx_hsspi_xfer,
|
|
|
|
};
|
|
|
|
|
|
|
|
static const struct udevice_id bcm63xx_hsspi_ids[] = {
|
|
|
|
{ .compatible = "brcm,bcm6328-hsspi", },
|
2023-06-07 23:37:03 +00:00
|
|
|
{ .compatible = "brcm,bcmbca-hsspi-v1.0", },
|
2018-01-20 01:13:38 +00:00
|
|
|
{ /* sentinel */ }
|
|
|
|
};
|
|
|
|
|
|
|
|
static int bcm63xx_hsspi_child_pre_probe(struct udevice *dev)
|
|
|
|
{
|
|
|
|
struct bcm63xx_hsspi_priv *priv = dev_get_priv(dev->parent);
|
2020-12-03 23:55:23 +00:00
|
|
|
struct dm_spi_slave_plat *plat = dev_get_parent_plat(dev);
|
2023-06-07 23:37:04 +00:00
|
|
|
struct spi_slave *slave = dev_get_parent_priv(dev);
|
2018-01-20 01:13:38 +00:00
|
|
|
|
|
|
|
/* check cs */
|
|
|
|
if (plat->cs >= priv->num_cs) {
|
|
|
|
printf("no cs %u\n", plat->cs);
|
|
|
|
return -ENODEV;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* cs polarity */
|
|
|
|
if (plat->mode & SPI_CS_HIGH)
|
|
|
|
priv->cs_pols |= BIT(plat->cs);
|
|
|
|
else
|
|
|
|
priv->cs_pols &= ~BIT(plat->cs);
|
|
|
|
|
2023-06-07 23:37:04 +00:00
|
|
|
/*
|
|
|
|
* set the max read/write size to make sure each xfer are within the
|
|
|
|
* prepend limit
|
|
|
|
*/
|
|
|
|
slave->max_read_size = HSSPI_MAX_DATA_SIZE;
|
|
|
|
slave->max_write_size = HSSPI_MAX_DATA_SIZE;
|
|
|
|
|
2018-01-20 01:13:38 +00:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int bcm63xx_hsspi_probe(struct udevice *dev)
|
|
|
|
{
|
|
|
|
struct bcm63xx_hsspi_priv *priv = dev_get_priv(dev);
|
|
|
|
struct reset_ctl rst_ctl;
|
|
|
|
struct clk clk;
|
|
|
|
int ret;
|
|
|
|
|
2018-03-22 18:39:37 +00:00
|
|
|
priv->regs = dev_remap_addr(dev);
|
|
|
|
if (!priv->regs)
|
2018-01-20 01:13:38 +00:00
|
|
|
return -EINVAL;
|
|
|
|
|
2018-03-22 18:39:37 +00:00
|
|
|
priv->num_cs = dev_read_u32_default(dev, "num-cs", 8);
|
2018-01-20 01:13:38 +00:00
|
|
|
|
|
|
|
/* enable clock */
|
|
|
|
ret = clk_get_by_name(dev, "hsspi", &clk);
|
|
|
|
if (ret < 0)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
ret = clk_enable(&clk);
|
2019-08-14 13:18:35 +00:00
|
|
|
if (ret < 0 && ret != -ENOSYS)
|
2018-01-20 01:13:38 +00:00
|
|
|
return ret;
|
|
|
|
|
2022-01-15 22:25:02 +00:00
|
|
|
clk_free(&clk);
|
2018-01-20 01:13:38 +00:00
|
|
|
|
|
|
|
/* get clock rate */
|
|
|
|
ret = clk_get_by_name(dev, "pll", &clk);
|
2019-08-14 13:18:35 +00:00
|
|
|
if (ret < 0 && ret != -ENOSYS)
|
2018-01-20 01:13:38 +00:00
|
|
|
return ret;
|
|
|
|
|
|
|
|
priv->clk_rate = clk_get_rate(&clk);
|
|
|
|
|
2022-01-15 22:25:02 +00:00
|
|
|
clk_free(&clk);
|
2018-01-20 01:13:38 +00:00
|
|
|
|
|
|
|
/* perform reset */
|
|
|
|
ret = reset_get_by_index(dev, 0, &rst_ctl);
|
2019-08-14 13:18:35 +00:00
|
|
|
if (ret >= 0) {
|
|
|
|
ret = reset_deassert(&rst_ctl);
|
|
|
|
if (ret < 0)
|
|
|
|
return ret;
|
|
|
|
}
|
2018-01-20 01:13:38 +00:00
|
|
|
|
|
|
|
ret = reset_free(&rst_ctl);
|
|
|
|
if (ret < 0)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
/* initialize hardware */
|
2019-08-14 13:18:34 +00:00
|
|
|
writel(0, priv->regs + SPI_IR_MASK_REG);
|
2018-01-20 01:13:38 +00:00
|
|
|
|
|
|
|
/* clear pending interrupts */
|
2019-08-14 13:18:34 +00:00
|
|
|
writel(SPI_IR_CLEAR_ALL, priv->regs + SPI_IR_STAT_REG);
|
2018-01-20 01:13:38 +00:00
|
|
|
|
|
|
|
/* enable clk gate */
|
2019-08-14 13:18:34 +00:00
|
|
|
setbits_32(priv->regs + SPI_CTL_REG, SPI_CTL_CLK_GATE_MASK);
|
2018-01-20 01:13:38 +00:00
|
|
|
|
|
|
|
/* read default cs polarities */
|
2019-08-14 13:18:34 +00:00
|
|
|
priv->cs_pols = readl(priv->regs + SPI_CTL_REG) &
|
2018-01-20 01:13:38 +00:00
|
|
|
SPI_CTL_CS_POL_MASK;
|
|
|
|
|
2023-06-07 23:37:04 +00:00
|
|
|
/* default in prepend mode */
|
|
|
|
priv->xfer_mode = HSSPI_XFER_MODE_PREPEND;
|
|
|
|
|
2018-01-20 01:13:38 +00:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
U_BOOT_DRIVER(bcm63xx_hsspi) = {
|
|
|
|
.name = "bcm63xx_hsspi",
|
|
|
|
.id = UCLASS_SPI,
|
|
|
|
.of_match = bcm63xx_hsspi_ids,
|
|
|
|
.ops = &bcm63xx_hsspi_ops,
|
2020-12-03 23:55:17 +00:00
|
|
|
.priv_auto = sizeof(struct bcm63xx_hsspi_priv),
|
2018-01-20 01:13:38 +00:00
|
|
|
.child_pre_probe = bcm63xx_hsspi_child_pre_probe,
|
|
|
|
.probe = bcm63xx_hsspi_probe,
|
|
|
|
};
|