2021-07-02 10:40:34 +00:00
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Xilinx Multirate Ethernet MAC(MRMAC) driver
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*
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* Author(s): Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
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2023-07-10 12:35:49 +00:00
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* Michal Simek <michal.simek@amd.com>
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2021-07-02 10:40:34 +00:00
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*
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* Copyright (C) 2021 Xilinx, Inc. All rights reserved.
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*/
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#include <config.h>
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#include <common.h>
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#include <cpu_func.h>
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#include <dm.h>
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#include <log.h>
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#include <net.h>
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#include <malloc.h>
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#include <wait_bit.h>
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#include <asm/io.h>
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#include <linux/delay.h>
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#include <linux/ethtool.h>
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#include "xilinx_axi_mrmac.h"
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static void axi_mrmac_dma_write(struct mcdma_bd *bd, u32 *desc)
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{
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if (IS_ENABLED(CONFIG_PHYS_64BIT))
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writeq((unsigned long)bd, desc);
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else
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writel((uintptr_t)bd, desc);
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}
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/**
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* axi_mrmac_ethernet_init - MRMAC init function
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* @priv: MRMAC private structure
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*
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* Return: 0 on success, negative value on errors
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*
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* This function is called to reset and initialize MRMAC core. This is
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* typically called during initialization. It does a reset of MRMAC Rx/Tx
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* channels and Rx/Tx SERDES. It configures MRMAC speed based on mrmac_rate
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* which is read from DT. This function waits for block lock bit to get set,
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* if it is not set within 100ms time returns a timeout error.
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*/
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static int axi_mrmac_ethernet_init(struct axi_mrmac_priv *priv)
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{
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struct mrmac_regs *regs = priv->iobase;
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u32 reg;
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u32 ret;
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/* Perform all the RESET's required */
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setbits_le32(®s->reset, MRMAC_RX_SERDES_RST_MASK | MRMAC_RX_RST_MASK
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| MRMAC_TX_SERDES_RST_MASK | MRMAC_TX_RST_MASK);
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mdelay(MRMAC_RESET_DELAY);
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/* Configure Mode register */
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reg = readl(®s->mode);
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log_debug("Configuring MRMAC speed to %d\n", priv->mrmac_rate);
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if (priv->mrmac_rate == SPEED_25000) {
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reg &= ~MRMAC_CTL_RATE_CFG_MASK;
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reg |= MRMAC_CTL_DATA_RATE_25G;
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reg |= (MRMAC_CTL_AXIS_CFG_25G_IND << MRMAC_CTL_AXIS_CFG_SHIFT);
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reg |= (MRMAC_CTL_SERDES_WIDTH_25G <<
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MRMAC_CTL_SERDES_WIDTH_SHIFT);
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} else {
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reg &= ~MRMAC_CTL_RATE_CFG_MASK;
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reg |= MRMAC_CTL_DATA_RATE_10G;
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reg |= (MRMAC_CTL_AXIS_CFG_10G_IND << MRMAC_CTL_AXIS_CFG_SHIFT);
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reg |= (MRMAC_CTL_SERDES_WIDTH_10G <<
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MRMAC_CTL_SERDES_WIDTH_SHIFT);
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}
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/* For tick reg */
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reg |= MRMAC_CTL_PM_TICK_MASK;
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writel(reg, ®s->mode);
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clrbits_le32(®s->reset, MRMAC_RX_SERDES_RST_MASK | MRMAC_RX_RST_MASK
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| MRMAC_TX_SERDES_RST_MASK | MRMAC_TX_RST_MASK);
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mdelay(MRMAC_RESET_DELAY);
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/* Setup MRMAC hardware options */
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setbits_le32(®s->rx_config, MRMAC_RX_DEL_FCS_MASK);
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setbits_le32(®s->tx_config, MRMAC_TX_INS_FCS_MASK);
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setbits_le32(®s->tx_config, MRMAC_TX_EN_MASK);
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setbits_le32(®s->rx_config, MRMAC_RX_EN_MASK);
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/* Check for block lock bit to be set. This ensures that
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* MRMAC ethernet IP is functioning normally.
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*/
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writel(MRMAC_STS_ALL_MASK, (phys_addr_t)priv->iobase +
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MRMAC_TX_STS_OFFSET);
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writel(MRMAC_STS_ALL_MASK, (phys_addr_t)priv->iobase +
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MRMAC_RX_STS_OFFSET);
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writel(MRMAC_STS_ALL_MASK, (phys_addr_t)priv->iobase +
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MRMAC_STATRX_BLKLCK_OFFSET);
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ret = wait_for_bit_le32((u32 *)((phys_addr_t)priv->iobase +
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MRMAC_STATRX_BLKLCK_OFFSET),
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MRMAC_RX_BLKLCK_MASK, true,
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MRMAC_BLKLCK_TIMEOUT, true);
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if (ret) {
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log_warning("Error: MRMAC block lock not complete!\n");
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return -EIO;
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}
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writel(MRMAC_TICK_TRIGGER, ®s->tick_reg);
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return 0;
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}
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/**
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* axi_mcdma_init - Reset MCDMA engine
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* @priv: MRMAC private structure
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*
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* Return: 0 on success, negative value on timeouts
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*
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* This function is called to reset and initialize MCDMA engine
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*/
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static int axi_mcdma_init(struct axi_mrmac_priv *priv)
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{
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u32 ret;
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/* Reset the engine so the hardware starts from a known state */
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writel(XMCDMA_CR_RESET, &priv->mm2s_cmn->control);
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writel(XMCDMA_CR_RESET, &priv->s2mm_cmn->control);
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/* Check Tx/Rx MCDMA.RST. Reset is done when the reset bit is low */
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ret = wait_for_bit_le32(&priv->mm2s_cmn->control, XMCDMA_CR_RESET,
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false, MRMAC_DMARST_TIMEOUT, true);
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if (ret) {
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log_warning("Tx MCDMA reset Timeout\n");
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return -ETIMEDOUT;
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}
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ret = wait_for_bit_le32(&priv->s2mm_cmn->control, XMCDMA_CR_RESET,
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false, MRMAC_DMARST_TIMEOUT, true);
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if (ret) {
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log_warning("Rx MCDMA reset Timeout\n");
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return -ETIMEDOUT;
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}
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/* Enable channel 1 for Tx and Rx */
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writel(XMCDMA_CHANNEL_1, &priv->mm2s_cmn->chen);
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writel(XMCDMA_CHANNEL_1, &priv->s2mm_cmn->chen);
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return 0;
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}
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/**
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* axi_mrmac_start - MRMAC start
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* @dev: udevice structure
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*
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* Return: 0 on success, negative value on errors
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*
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* This is a initialization function of MRMAC. Call MCDMA initialization
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* function and setup Rx buffer descriptors for starting reception of packets.
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* Enable Tx and Rx channels and trigger Rx channel fetch.
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*/
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static int axi_mrmac_start(struct udevice *dev)
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{
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struct axi_mrmac_priv *priv = dev_get_priv(dev);
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struct mrmac_regs *regs = priv->iobase;
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/*
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* Initialize MCDMA engine. MCDMA engine must be initialized before
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* MRMAC. During MCDMA engine initialization, MCDMA hardware is reset,
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* since MCDMA reset line is connected to MRMAC, this would ensure a
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* reset of MRMAC.
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*/
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axi_mcdma_init(priv);
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/* Initialize MRMAC hardware */
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if (axi_mrmac_ethernet_init(priv))
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return -EIO;
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/* Disable all Rx interrupts before RxBD space setup */
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clrbits_le32(&priv->mcdma_rx->control, XMCDMA_IRQ_ALL_MASK);
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/* Update current descriptor */
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axi_mrmac_dma_write(priv->rx_bd[0], &priv->mcdma_rx->current);
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/* Setup Rx BD. MRMAC needs atleast two descriptors */
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memset(priv->rx_bd[0], 0, RX_BD_TOTAL_SIZE);
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priv->rx_bd[0]->next_desc = lower_32_bits((u64)priv->rx_bd[1]);
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priv->rx_bd[0]->buf_addr = lower_32_bits((u64)net_rx_packets[0]);
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priv->rx_bd[1]->next_desc = lower_32_bits((u64)priv->rx_bd[0]);
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priv->rx_bd[1]->buf_addr = lower_32_bits((u64)net_rx_packets[1]);
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if (IS_ENABLED(CONFIG_PHYS_64BIT)) {
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priv->rx_bd[0]->next_desc_msb = upper_32_bits((u64)priv->rx_bd[1]);
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priv->rx_bd[0]->buf_addr_msb = upper_32_bits((u64)net_rx_packets[0]);
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priv->rx_bd[1]->next_desc_msb = upper_32_bits((u64)priv->rx_bd[0]);
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priv->rx_bd[1]->buf_addr_msb = upper_32_bits((u64)net_rx_packets[1]);
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}
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priv->rx_bd[0]->cntrl = PKTSIZE_ALIGN;
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priv->rx_bd[1]->cntrl = PKTSIZE_ALIGN;
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/* Flush the last BD so DMA core could see the updates */
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flush_cache((phys_addr_t)priv->rx_bd[0], RX_BD_TOTAL_SIZE);
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/* It is necessary to flush rx buffers because if you don't do it
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* then cache can contain uninitialized data
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*/
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flush_cache((phys_addr_t)priv->rx_bd[0]->buf_addr, RX_BUFF_TOTAL_SIZE);
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/* Start the hardware */
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setbits_le32(&priv->s2mm_cmn->control, XMCDMA_CR_RUNSTOP_MASK);
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setbits_le32(&priv->mm2s_cmn->control, XMCDMA_CR_RUNSTOP_MASK);
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setbits_le32(&priv->mcdma_rx->control, XMCDMA_IRQ_ALL_MASK);
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/* Channel fetch */
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setbits_le32(&priv->mcdma_rx->control, XMCDMA_CR_RUNSTOP_MASK);
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/* Update tail descriptor. Now it's ready to receive data */
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axi_mrmac_dma_write(priv->rx_bd[1], &priv->mcdma_rx->tail);
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/* Enable Tx */
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setbits_le32(®s->tx_config, MRMAC_TX_EN_MASK);
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/* Enable Rx */
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setbits_le32(®s->rx_config, MRMAC_RX_EN_MASK);
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return 0;
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}
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/**
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* axi_mrmac_send - MRMAC Tx function
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* @dev: udevice structure
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* @ptr: pointer to Tx buffer
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* @len: transfer length
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*
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* Return: 0 on success, negative value on errors
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*
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* This is a Tx send function of MRMAC. Setup Tx buffer descriptors and trigger
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* transfer. Wait till the data is transferred.
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*/
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static int axi_mrmac_send(struct udevice *dev, void *ptr, int len)
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{
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struct axi_mrmac_priv *priv = dev_get_priv(dev);
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u32 ret;
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#ifdef DEBUG
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print_buffer(ptr, ptr, 1, len, 16);
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#endif
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if (len > PKTSIZE_ALIGN)
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len = PKTSIZE_ALIGN;
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/* If size is less than min packet size, pad to min size */
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if (len < MIN_PKT_SIZE) {
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memset(priv->txminframe, 0, MIN_PKT_SIZE);
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memcpy(priv->txminframe, ptr, len);
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len = MIN_PKT_SIZE;
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ptr = priv->txminframe;
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}
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writel(XMCDMA_IRQ_ALL_MASK, &priv->mcdma_tx->status);
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clrbits_le32(&priv->mcdma_tx->control, XMCDMA_CR_RUNSTOP_MASK);
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/* Flush packet to main memory to be trasfered by DMA */
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flush_cache((phys_addr_t)ptr, len);
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/* Setup Tx BD. MRMAC needs atleast two descriptors */
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memset(priv->tx_bd[0], 0, TX_BD_TOTAL_SIZE);
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priv->tx_bd[0]->next_desc = lower_32_bits((u64)priv->tx_bd[1]);
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priv->tx_bd[0]->buf_addr = lower_32_bits((u64)ptr);
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/* At the end of the ring, link the last BD back to the top */
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priv->tx_bd[1]->next_desc = lower_32_bits((u64)priv->tx_bd[0]);
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priv->tx_bd[1]->buf_addr = lower_32_bits((u64)ptr + len / 2);
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if (IS_ENABLED(CONFIG_PHYS_64BIT)) {
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priv->tx_bd[0]->next_desc_msb = upper_32_bits((u64)priv->tx_bd[1]);
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priv->tx_bd[0]->buf_addr_msb = upper_32_bits((u64)ptr);
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priv->tx_bd[1]->next_desc_msb = upper_32_bits((u64)priv->tx_bd[0]);
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priv->tx_bd[1]->buf_addr_msb = upper_32_bits((u64)ptr + len / 2);
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}
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/* Split Tx data in to half and send in two descriptors */
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priv->tx_bd[0]->cntrl = (len / 2) | XMCDMA_BD_CTRL_TXSOF_MASK;
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priv->tx_bd[1]->cntrl = (len - len / 2) | XMCDMA_BD_CTRL_TXEOF_MASK;
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/* Flush the last BD so DMA core could see the updates */
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flush_cache((phys_addr_t)priv->tx_bd[0], TX_BD_TOTAL_SIZE);
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if (readl(&priv->mcdma_tx->status) & XMCDMA_CH_IDLE) {
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axi_mrmac_dma_write(priv->tx_bd[0], &priv->mcdma_tx->current);
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/* Channel fetch */
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setbits_le32(&priv->mcdma_tx->control, XMCDMA_CR_RUNSTOP_MASK);
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} else {
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log_warning("Error: current desc is not updated\n");
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return -EIO;
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}
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setbits_le32(&priv->mcdma_tx->control, XMCDMA_IRQ_ALL_MASK);
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/* Start transfer */
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axi_mrmac_dma_write(priv->tx_bd[1], &priv->mcdma_tx->tail);
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/* Wait for transmission to complete */
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ret = wait_for_bit_le32(&priv->mcdma_tx->status, XMCDMA_IRQ_IOC_MASK,
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true, 1, true);
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if (ret) {
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log_warning("%s: Timeout\n", __func__);
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return -ETIMEDOUT;
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}
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/* Clear status */
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priv->tx_bd[0]->sband_stats = 0;
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priv->tx_bd[1]->sband_stats = 0;
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log_debug("Sending complete\n");
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return 0;
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}
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static bool isrxready(struct axi_mrmac_priv *priv)
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{
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u32 status;
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/* Read pending interrupts */
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status = readl(&priv->mcdma_rx->status);
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/* Acknowledge pending interrupts */
|
|
|
|
writel(status & XMCDMA_IRQ_ALL_MASK, &priv->mcdma_rx->status);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* If Reception done interrupt is asserted, call Rx call back function
|
|
|
|
* to handle the processed BDs and then raise the according flag.
|
|
|
|
*/
|
|
|
|
if (status & (XMCDMA_IRQ_IOC_MASK | XMCDMA_IRQ_DELAY_MASK))
|
|
|
|
return 1;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* axi_mrmac_recv - MRMAC Rx function
|
|
|
|
* @dev: udevice structure
|
|
|
|
* @flags: flags from network stack
|
|
|
|
* @packetp pointer to received data
|
|
|
|
*
|
|
|
|
* Return: received data length on success, negative value on errors
|
|
|
|
*
|
|
|
|
* This is a Rx function of MRMAC. Check if any data is received on MCDMA.
|
|
|
|
* Copy buffer pointer to packetp and return received data length.
|
|
|
|
*/
|
|
|
|
static int axi_mrmac_recv(struct udevice *dev, int flags, uchar **packetp)
|
|
|
|
{
|
|
|
|
struct axi_mrmac_priv *priv = dev_get_priv(dev);
|
|
|
|
u32 rx_bd_end;
|
|
|
|
u32 length;
|
|
|
|
|
|
|
|
/* Wait for an incoming packet */
|
|
|
|
if (!isrxready(priv))
|
|
|
|
return -EAGAIN;
|
|
|
|
|
|
|
|
/* Clear all interrupts */
|
|
|
|
writel(XMCDMA_IRQ_ALL_MASK, &priv->mcdma_rx->status);
|
|
|
|
|
|
|
|
/* Disable IRQ for a moment till packet is handled */
|
|
|
|
clrbits_le32(&priv->mcdma_rx->control, XMCDMA_IRQ_ALL_MASK);
|
|
|
|
|
|
|
|
/* Disable channel fetch */
|
|
|
|
clrbits_le32(&priv->mcdma_rx->control, XMCDMA_CR_RUNSTOP_MASK);
|
|
|
|
|
|
|
|
rx_bd_end = (ulong)priv->rx_bd[0] + roundup(RX_BD_TOTAL_SIZE,
|
|
|
|
ARCH_DMA_MINALIGN);
|
|
|
|
/* Invalidate Rx descriptors to see proper Rx length */
|
|
|
|
invalidate_dcache_range((phys_addr_t)priv->rx_bd[0], rx_bd_end);
|
|
|
|
|
|
|
|
length = priv->rx_bd[0]->status & XMCDMA_BD_STS_ACTUAL_LEN_MASK;
|
|
|
|
*packetp = (uchar *)(ulong)priv->rx_bd[0]->buf_addr;
|
|
|
|
|
|
|
|
if (!length) {
|
|
|
|
length = priv->rx_bd[1]->status & XMCDMA_BD_STS_ACTUAL_LEN_MASK;
|
|
|
|
*packetp = (uchar *)(ulong)priv->rx_bd[1]->buf_addr;
|
|
|
|
}
|
|
|
|
|
|
|
|
#ifdef DEBUG
|
|
|
|
print_buffer(*packetp, *packetp, 1, length, 16);
|
|
|
|
#endif
|
|
|
|
/* Clear status */
|
|
|
|
priv->rx_bd[0]->status = 0;
|
|
|
|
priv->rx_bd[1]->status = 0;
|
|
|
|
|
|
|
|
return length;
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* axi_mrmac_free_pkt - MRMAC free packet function
|
|
|
|
* @dev: udevice structure
|
|
|
|
* @packet: receive buffer pointer
|
|
|
|
* @length received data length
|
|
|
|
*
|
|
|
|
* Return: 0 on success, negative value on errors
|
|
|
|
*
|
|
|
|
* This is Rx free packet function of MRMAC. Prepare MRMAC for reception of
|
|
|
|
* data again. Invalidate previous data from Rx buffers and set Rx buffer
|
|
|
|
* descriptors. Trigger reception by updating tail descriptor.
|
|
|
|
*/
|
|
|
|
static int axi_mrmac_free_pkt(struct udevice *dev, uchar *packet, int length)
|
|
|
|
{
|
|
|
|
struct axi_mrmac_priv *priv = dev_get_priv(dev);
|
|
|
|
|
|
|
|
#ifdef DEBUG
|
|
|
|
/* It is useful to clear buffer to be sure that it is consistent */
|
|
|
|
memset(priv->rx_bd[0]->buf_addr, 0, RX_BUFF_TOTAL_SIZE);
|
|
|
|
#endif
|
|
|
|
/* Disable all Rx interrupts before RxBD space setup */
|
|
|
|
clrbits_le32(&priv->mcdma_rx->control, XMCDMA_IRQ_ALL_MASK);
|
|
|
|
|
|
|
|
/* Disable channel fetch */
|
|
|
|
clrbits_le32(&priv->mcdma_rx->control, XMCDMA_CR_RUNSTOP_MASK);
|
|
|
|
|
|
|
|
/* Update current descriptor */
|
|
|
|
axi_mrmac_dma_write(priv->rx_bd[0], &priv->mcdma_rx->current);
|
|
|
|
|
|
|
|
/* Write bd to HW */
|
|
|
|
flush_cache((phys_addr_t)priv->rx_bd[0], RX_BD_TOTAL_SIZE);
|
|
|
|
|
|
|
|
/* It is necessary to flush rx buffers because if you don't do it
|
|
|
|
* then cache will contain previous packet
|
|
|
|
*/
|
|
|
|
flush_cache((phys_addr_t)priv->rx_bd[0]->buf_addr, RX_BUFF_TOTAL_SIZE);
|
|
|
|
|
|
|
|
/* Enable all IRQ */
|
|
|
|
setbits_le32(&priv->mcdma_rx->control, XMCDMA_IRQ_ALL_MASK);
|
|
|
|
|
|
|
|
/* Channel fetch */
|
|
|
|
setbits_le32(&priv->mcdma_rx->control, XMCDMA_CR_RUNSTOP_MASK);
|
|
|
|
|
|
|
|
/* Update tail descriptor. Now it's ready to receive data */
|
|
|
|
axi_mrmac_dma_write(priv->rx_bd[1], &priv->mcdma_rx->tail);
|
|
|
|
|
|
|
|
log_debug("Rx completed, framelength = %x\n", length);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* axi_mrmac_stop - Stop MCDMA transfers
|
|
|
|
* @dev: udevice structure
|
|
|
|
*
|
|
|
|
* Return: 0 on success, negative value on errors
|
|
|
|
*
|
|
|
|
* Stop MCDMA engine for both Tx and Rx transfers.
|
|
|
|
*/
|
|
|
|
static void axi_mrmac_stop(struct udevice *dev)
|
|
|
|
{
|
|
|
|
struct axi_mrmac_priv *priv = dev_get_priv(dev);
|
|
|
|
|
|
|
|
/* Stop the hardware */
|
|
|
|
clrbits_le32(&priv->mcdma_tx->control, XMCDMA_CR_RUNSTOP_MASK);
|
|
|
|
clrbits_le32(&priv->mcdma_rx->control, XMCDMA_CR_RUNSTOP_MASK);
|
|
|
|
|
|
|
|
log_debug("Halted\n");
|
|
|
|
}
|
|
|
|
|
|
|
|
static int axi_mrmac_probe(struct udevice *dev)
|
|
|
|
{
|
|
|
|
struct axi_mrmac_plat *plat = dev_get_plat(dev);
|
|
|
|
struct eth_pdata *pdata = &plat->eth_pdata;
|
|
|
|
struct axi_mrmac_priv *priv = dev_get_priv(dev);
|
|
|
|
|
|
|
|
priv->iobase = (struct mrmac_regs *)pdata->iobase;
|
|
|
|
|
|
|
|
priv->mm2s_cmn = plat->mm2s_cmn;
|
|
|
|
priv->mcdma_tx = (struct mcdma_chan_reg *)((phys_addr_t)priv->mm2s_cmn
|
|
|
|
+ XMCDMA_CHAN_OFFSET);
|
|
|
|
priv->s2mm_cmn = (struct mcdma_common_regs *)((phys_addr_t)priv->mm2s_cmn
|
|
|
|
+ XMCDMA_RX_OFFSET);
|
|
|
|
priv->mcdma_rx = (struct mcdma_chan_reg *)((phys_addr_t)priv->s2mm_cmn
|
|
|
|
+ XMCDMA_CHAN_OFFSET);
|
|
|
|
priv->mrmac_rate = plat->mrmac_rate;
|
|
|
|
|
|
|
|
/* Align buffers to ARCH_DMA_MINALIGN */
|
|
|
|
priv->tx_bd[0] = memalign(ARCH_DMA_MINALIGN, TX_BD_TOTAL_SIZE);
|
|
|
|
priv->tx_bd[1] = (struct mcdma_bd *)((ulong)priv->tx_bd[0] +
|
|
|
|
sizeof(struct mcdma_bd));
|
|
|
|
|
|
|
|
priv->rx_bd[0] = memalign(ARCH_DMA_MINALIGN, RX_BD_TOTAL_SIZE);
|
|
|
|
priv->rx_bd[1] = (struct mcdma_bd *)((ulong)priv->rx_bd[0] +
|
|
|
|
sizeof(struct mcdma_bd));
|
|
|
|
|
|
|
|
priv->txminframe = memalign(ARCH_DMA_MINALIGN, MIN_PKT_SIZE);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int axi_mrmac_remove(struct udevice *dev)
|
|
|
|
{
|
|
|
|
struct axi_mrmac_priv *priv = dev_get_priv(dev);
|
|
|
|
|
|
|
|
/* Free buffer descriptors */
|
|
|
|
free(priv->tx_bd[0]);
|
|
|
|
free(priv->rx_bd[0]);
|
|
|
|
free(priv->txminframe);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int axi_mrmac_of_to_plat(struct udevice *dev)
|
|
|
|
{
|
|
|
|
struct axi_mrmac_plat *plat = dev_get_plat(dev);
|
|
|
|
struct eth_pdata *pdata = &plat->eth_pdata;
|
|
|
|
struct ofnode_phandle_args phandle_args;
|
|
|
|
int ret = 0;
|
|
|
|
|
|
|
|
pdata->iobase = dev_read_addr(dev);
|
|
|
|
|
|
|
|
ret = dev_read_phandle_with_args(dev, "axistream-connected", NULL, 0, 0,
|
|
|
|
&phandle_args);
|
|
|
|
if (ret) {
|
|
|
|
log_debug("axistream not found\n");
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
plat->mm2s_cmn = (struct mcdma_common_regs *)ofnode_read_u64_default
|
|
|
|
(phandle_args.node, "reg", -1);
|
|
|
|
if (!plat->mm2s_cmn) {
|
|
|
|
log_warning("MRMAC dma register space not found\n");
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Set default MRMAC rate to 10000 */
|
|
|
|
plat->mrmac_rate = dev_read_u32_default(dev, "xlnx,mrmac-rate", 10000);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static const struct eth_ops axi_mrmac_ops = {
|
|
|
|
.start = axi_mrmac_start,
|
|
|
|
.send = axi_mrmac_send,
|
|
|
|
.recv = axi_mrmac_recv,
|
|
|
|
.free_pkt = axi_mrmac_free_pkt,
|
|
|
|
.stop = axi_mrmac_stop,
|
|
|
|
};
|
|
|
|
|
|
|
|
static const struct udevice_id axi_mrmac_ids[] = {
|
|
|
|
{ .compatible = "xlnx,mrmac-ethernet-1.0" },
|
|
|
|
{ }
|
|
|
|
};
|
|
|
|
|
|
|
|
U_BOOT_DRIVER(axi_mrmac) = {
|
|
|
|
.name = "axi_mrmac",
|
|
|
|
.id = UCLASS_ETH,
|
|
|
|
.of_match = axi_mrmac_ids,
|
|
|
|
.of_to_plat = axi_mrmac_of_to_plat,
|
|
|
|
.probe = axi_mrmac_probe,
|
|
|
|
.remove = axi_mrmac_remove,
|
|
|
|
.ops = &axi_mrmac_ops,
|
|
|
|
.priv_auto = sizeof(struct axi_mrmac_priv),
|
|
|
|
.plat_auto = sizeof(struct axi_mrmac_plat),
|
|
|
|
};
|