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https://github.com/AsahiLinux/u-boot
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250 lines
6.3 KiB
C
250 lines
6.3 KiB
C
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2023 StarFive Technology Co., Ltd.
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* Author: Yanhong Wang<yanhong.wang@starfivetech.com>
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*/
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#include <common.h>
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#include <asm/cache.h>
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#include <asm/gpio.h>
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#include <clk.h>
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#include <dm.h>
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#include <eth_phy.h>
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#include <net.h>
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#include <regmap.h>
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#include <reset.h>
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#include <syscon.h>
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#include "dwc_eth_qos.h"
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#define STARFIVE_DWMAC_PHY_INFT_RGMII 0x1
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#define STARFIVE_DWMAC_PHY_INFT_RMII 0x4
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#define STARFIVE_DWMAC_PHY_INFT_FIELD 0x7U
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struct starfive_platform_data {
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struct regmap *regmap;
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struct reset_ctl_bulk resets;
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struct clk_bulk clks;
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phy_interface_t interface;
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u32 offset;
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u32 shift;
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bool tx_use_rgmii_clk;
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};
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static int eqos_interface_init_jh7110(struct udevice *dev)
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{
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struct eth_pdata *pdata = dev_get_plat(dev);
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struct starfive_platform_data *data = pdata->priv_pdata;
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struct ofnode_phandle_args args;
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unsigned int mode;
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int ret;
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switch (data->interface) {
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case PHY_INTERFACE_MODE_RMII:
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mode = STARFIVE_DWMAC_PHY_INFT_RMII;
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break;
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case PHY_INTERFACE_MODE_RGMII:
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case PHY_INTERFACE_MODE_RGMII_ID:
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mode = STARFIVE_DWMAC_PHY_INFT_RGMII;
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break;
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default:
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return -EINVAL;
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}
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ret = dev_read_phandle_with_args(dev, "starfive,syscon", NULL,
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2, 0, &args);
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if (ret)
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return ret;
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if (args.args_count != 2)
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return -EINVAL;
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data->offset = args.args[0];
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data->shift = args.args[1];
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data->regmap = syscon_regmap_lookup_by_phandle(dev, "starfive,syscon");
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if (IS_ERR(data->regmap)) {
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ret = PTR_ERR(data->regmap);
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pr_err("Failed to get regmap: %d\n", ret);
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return ret;
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}
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return regmap_update_bits(data->regmap, data->offset,
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STARFIVE_DWMAC_PHY_INFT_FIELD << data->shift,
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mode << data->shift);
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}
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static int eqos_set_tx_clk_speed_jh7110(struct udevice *dev)
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{
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struct eqos_priv *eqos = dev_get_priv(dev);
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struct eth_pdata *pdata = dev_get_plat(dev);
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struct starfive_platform_data *data = pdata->priv_pdata;
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struct clk *pclk, *c;
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ulong rate;
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int ret;
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/* Generally, the rgmii_tx clock is provided by the internal clock,
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* which needs to match the corresponding clock frequency according
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* to different speeds. If the rgmii_tx clock is provided by the
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* external rgmii_rxin, there is no need to configure the clock
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* internally, because rgmii_rxin will be adaptively adjusted.
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*/
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if (data->tx_use_rgmii_clk)
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return 0;
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switch (eqos->phy->speed) {
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case SPEED_1000:
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rate = 125 * 1000 * 1000;
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break;
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case SPEED_100:
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rate = 25 * 1000 * 1000;
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break;
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case SPEED_10:
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rate = 2.5 * 1000 * 1000;
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break;
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default:
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pr_err("invalid speed %d", eqos->phy->speed);
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return -EINVAL;
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}
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/* eqos->clk_tx clock has no set rate operation, so just set the parent
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* clock rate directly
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*/
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ret = clk_get_by_id(eqos->clk_tx.id, &c);
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if (ret)
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return ret;
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pclk = clk_get_parent(c);
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if (pclk) {
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ret = clk_set_rate(pclk, rate);
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if (ret < 0) {
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pr_err("jh7110 (clk_tx, %lu) failed: %d", rate, ret);
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return ret;
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}
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}
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return 0;
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}
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static ulong eqos_get_tick_clk_rate_jh7110(struct udevice *dev)
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{
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struct eqos_priv *eqos = dev_get_priv(dev);
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return clk_get_rate(&eqos->clk_tx);
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}
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static int eqos_start_clks_jh7110(struct udevice *dev)
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{
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struct eth_pdata *pdata = dev_get_plat(dev);
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struct starfive_platform_data *data = pdata->priv_pdata;
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return clk_enable_bulk(&data->clks);
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}
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static int eqos_stop_clks_jh7110(struct udevice *dev)
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{
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struct eth_pdata *pdata = dev_get_plat(dev);
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struct starfive_platform_data *data = pdata->priv_pdata;
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return clk_disable_bulk(&data->clks);
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}
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static int eqos_start_resets_jh7110(struct udevice *dev)
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{
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struct eth_pdata *pdata = dev_get_plat(dev);
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struct starfive_platform_data *data = pdata->priv_pdata;
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return reset_deassert_bulk(&data->resets);
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}
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static int eqos_stop_resets_jh7110(struct udevice *dev)
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{
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struct eth_pdata *pdata = dev_get_plat(dev);
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struct starfive_platform_data *data = pdata->priv_pdata;
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return reset_assert_bulk(&data->resets);
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}
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static int eqos_remove_resources_jh7110(struct udevice *dev)
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{
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struct eth_pdata *pdata = dev_get_plat(dev);
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struct starfive_platform_data *data = pdata->priv_pdata;
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reset_assert_bulk(&data->resets);
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clk_disable_bulk(&data->clks);
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return 0;
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}
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static int eqos_probe_resources_jh7110(struct udevice *dev)
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{
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struct eqos_priv *eqos = dev_get_priv(dev);
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struct eth_pdata *pdata = dev_get_plat(dev);
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struct starfive_platform_data *data;
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int ret;
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data = calloc(1, sizeof(struct starfive_platform_data));
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if (!data)
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return -ENOMEM;
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pdata->priv_pdata = data;
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data->interface = eqos->config->interface(dev);
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if (data->interface == PHY_INTERFACE_MODE_NA) {
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pr_err("Invalid PHY interface\n");
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return -EINVAL;
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}
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ret = reset_get_bulk(dev, &data->resets);
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if (ret < 0)
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return ret;
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ret = clk_get_bulk(dev, &data->clks);
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if (ret < 0)
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return ret;
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ret = clk_get_by_name(dev, "gtx", &eqos->clk_tx);
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if (ret)
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return ret;
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data->tx_use_rgmii_clk = dev_read_bool(dev, "starfive,tx-use-rgmii-clk");
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return eqos_interface_init_jh7110(dev);
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}
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static struct eqos_ops eqos_jh7110_ops = {
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.eqos_inval_desc = eqos_inval_desc_generic,
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.eqos_flush_desc = eqos_flush_desc_generic,
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.eqos_inval_buffer = eqos_inval_buffer_generic,
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.eqos_flush_buffer = eqos_flush_buffer_generic,
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.eqos_probe_resources = eqos_probe_resources_jh7110,
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.eqos_remove_resources = eqos_remove_resources_jh7110,
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.eqos_stop_resets = eqos_stop_resets_jh7110,
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.eqos_start_resets = eqos_start_resets_jh7110,
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.eqos_stop_clks = eqos_stop_clks_jh7110,
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.eqos_start_clks = eqos_start_clks_jh7110,
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.eqos_calibrate_pads = eqos_null_ops,
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.eqos_disable_calibration = eqos_null_ops,
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.eqos_set_tx_clk_speed = eqos_set_tx_clk_speed_jh7110,
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.eqos_get_enetaddr = eqos_null_ops,
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.eqos_get_tick_clk_rate = eqos_get_tick_clk_rate_jh7110
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};
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/* mdio_wait: There is no need to wait after setting the MAC_MDIO_Address register
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* swr_wait: Software reset bit must be read at least 4 CSR clock cycles
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* after it is written to 1.
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* config_mac: Enable rx queue to DCB mode.
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* config_mac_mdio: CSR clock range is 250-300 Mhz.
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* axi_bus_width: The width of the data bus is 64 bit.
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*/
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struct eqos_config __maybe_unused eqos_jh7110_config = {
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.reg_access_always_ok = false,
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.mdio_wait = 0,
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.swr_wait = 4,
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.config_mac = EQOS_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_DCB,
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.config_mac_mdio = EQOS_MAC_MDIO_ADDRESS_CR_250_300,
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.axi_bus_width = EQOS_AXI_WIDTH_64,
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.interface = dev_read_phy_mode,
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.ops = &eqos_jh7110_ops
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};
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