u-boot/drivers/clk/altera/Makefile

# SPDX-License-Identifier: GPL-2.0+
#
# Copyright (C) 2018-2021 Marek Vasut <marex@denx.de>
#

obj-$(CONFIG_TARGET_SOCFPGA_AGILEX) += clk-agilex.o
obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += clk-arria10.o
obj-$(CONFIG_TARGET_SOCFPGA_N5X) += clk-n5x.o
obj-$(CONFIG_TARGET_SOCFPGA_N5X) += clk-mem-n5x.o
drivers: cosmetic: Convert SPDX license tags to Linux Kernel style Complete in the drivers directory the work started with commit 83d290c56fab ("SPDX: Convert all of our single license tags to Linux Kernel style"). Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> 2018-10-26 07:02:52 +00:00			`# SPDX-License-Identifier: GPL-2.0+`
clk: socfpga: Add initial Arria10 clock driver Add clock driver for the Arria10, which allows reading the clock frequency from all the clock described in the DT. The driver also allows enabling and disabling the clock. Reconfiguring frequency is not supported thus far. Since the DT bindings for the SoCFPGA clock are massively misdesigned and the handoff DT adds additional incorrectly described entries to the DT, the driver contains workarounds which attempt to rectify all of those problems. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Ley Foon Tan <ley.foon.tan@intel.com> 2018-07-31 15:58:07 +00:00			`#`
drivers: clk: Add clock driver for Intel N5X device Add clock manager driver for N5X. Provides clock initialization and get_rate functions. Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com> 2021-08-10 03:26:30 +00:00			`# Copyright (C) 2018-2021 Marek Vasut <marex@denx.de>`
clk: socfpga: Add initial Arria10 clock driver Add clock driver for the Arria10, which allows reading the clock frequency from all the clock described in the DT. The driver also allows enabling and disabling the clock. Reconfiguring frequency is not supported thus far. Since the DT bindings for the SoCFPGA clock are massively misdesigned and the handoff DT adds additional incorrectly described entries to the DT, the driver contains workarounds which attempt to rectify all of those problems. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Ley Foon Tan <ley.foon.tan@intel.com> 2018-07-31 15:58:07 +00:00			`#`

clk: agilex: Add clock driver for Agilex Add clock manager driver for Agilex. Provides clock initialization and get_rate functions. agilex-clock.h is from Linux commit ID cd2e1ad12247. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> 2019-11-27 07:55:22 +00:00			`obj-$(CONFIG_TARGET_SOCFPGA_AGILEX) += clk-agilex.o`
clk: socfpga: Add initial Arria10 clock driver Add clock driver for the Arria10, which allows reading the clock frequency from all the clock described in the DT. The driver also allows enabling and disabling the clock. Reconfiguring frequency is not supported thus far. Since the DT bindings for the SoCFPGA clock are massively misdesigned and the handoff DT adds additional incorrectly described entries to the DT, the driver contains workarounds which attempt to rectify all of those problems. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Ley Foon Tan <ley.foon.tan@intel.com> 2018-07-31 15:58:07 +00:00			`obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += clk-arria10.o`
drivers: clk: Add clock driver for Intel N5X device Add clock manager driver for N5X. Provides clock initialization and get_rate functions. Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com> 2021-08-10 03:26:30 +00:00			`obj-$(CONFIG_TARGET_SOCFPGA_N5X) += clk-n5x.o`
drivers: clk: Add memory clock driver for Intel N5X device Add memory clock manager driver for N5X. Provides memory clock initialization and enable functions. Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com> 2021-08-10 03:26:32 +00:00			`obj-$(CONFIG_TARGET_SOCFPGA_N5X) += clk-mem-n5x.o`