u-boot/arch/arm/mach-uniphier/late_lowlevel_init.S

/*
 * Copyright (C) 2015 Socionext Inc.
 *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <linux/linkage.h>
#include <mach/ssc-regs.h>

ENTRY(lowlevel_init)
	ldr	r1, = SSCC
	ldr	r0, [r1]
	bic	r0, r0, #SSCC_ON	@ L2 disable
	str	r0, [r1]
	mov	pc, lr
ENDPROC(lowlevel_init)
ARM: UniPhier: add empty lowlevel_init to U-boot proper To remove the ifdef conditional of CONFIG_SKIP_LOWLEVEL_INIT, add late_lowlevel_init.S to U-Boot proper. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> 2015-03-22 15:07:29 +00:00			`/*`
			`* Copyright (C) 2015 Socionext Inc.`
			`* Author: Masahiro Yamada <yamada.masahiro@socionext.com>`
			`*`
			`* SPDX-License-Identifier: GPL-2.0+`
			`*/`

			`#include <linux/linkage.h>`
ARM: UniPhier: disable L2 cache by lowlevel_init of U-Boot proper The L2 cache is used as a temporary SRAM on SPL. Now the secondary CPUs store the necessary code for jumping to Linux on their L1 I-caches. So, the L2 cache can be disabled much earlier, at the very entry of U-Boot proper (lowlevel_init). This makes the boot sequence clearer. Also, as the L1 cache has been disabled by the start.S, enable_caches() does not need to do it again. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> 2015-03-22 15:07:32 +00:00			`#include <mach/ssc-regs.h>`
ARM: UniPhier: add empty lowlevel_init to U-boot proper To remove the ifdef conditional of CONFIG_SKIP_LOWLEVEL_INIT, add late_lowlevel_init.S to U-Boot proper. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> 2015-03-22 15:07:29 +00:00
			`ENTRY(lowlevel_init)`
ARM: UniPhier: disable L2 cache by lowlevel_init of U-Boot proper The L2 cache is used as a temporary SRAM on SPL. Now the secondary CPUs store the necessary code for jumping to Linux on their L1 I-caches. So, the L2 cache can be disabled much earlier, at the very entry of U-Boot proper (lowlevel_init). This makes the boot sequence clearer. Also, as the L1 cache has been disabled by the start.S, enable_caches() does not need to do it again. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> 2015-03-22 15:07:32 +00:00			`ldr r1, = SSCC`
			`ldr r0, [r1]`
			`bic r0, r0, #SSCC_ON @ L2 disable`
			`str r0, [r1]`
ARM: UniPhier: add empty lowlevel_init to U-boot proper To remove the ifdef conditional of CONFIG_SKIP_LOWLEVEL_INIT, add late_lowlevel_init.S to U-Boot proper. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> 2015-03-22 15:07:29 +00:00			`mov pc, lr`
			`ENDPROC(lowlevel_init)`