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69 lines
2.2 KiB
Text
69 lines
2.2 KiB
Text
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Marvell COMPHY SerDes lane bindings
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=====================================
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The COMPHY node includes a description of the COMPHY SerDes lane configuration.
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The COMPHY driver initializes the MUX of the SerDes lanes, and powers up the SerDes
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by dependencies on the FDT blob configurations
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Mandatory properties:
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SoC specific:
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- compatible:
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The compatible should include "marvell,mvebu-comphy"
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and the COMPHY per chip compatible:
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"marvell,comphy-cp110" for CP110 available in Aramda70x0/80x0.
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The COMPHY per chip used to set which MUX configuration to use, and COMPHY power-up revision.
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- reg: Base address and size of the COMPHY and hpipe units.
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- max-lanes: Maximum number of comphy lanes.
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- mux-bitcount: Number of bits that are allocated for every MUX in the COMPHY-selector register.
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Board specific:
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- PHY: Entry that include the configuration of the PHY.
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Every PHY should have the below parameters:
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- phy-type: the mode of the PHY
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Possible modes located in include/dt-bindings/comphy/comphy_data.h
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Optional properties:
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- phy-speed: the speed of the PHY
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Possible speeds values located in include/dt-bindings/comphy/comphy_data.h
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- phy-invert: Polarity invert (COMPHY_POLARITY_TXD_INVERT/COMPHY_POLARITY_RXD_INVERT)
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the possible bits under include/dt-bindings/comphy/comphy_data.h
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- clk-src: Set the clock source of PCIe, if configured to PCIe clock output
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This relevant for SerDes lane 5 only (by default, lane 4 is the clock source)
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for Armada-7040 boards.
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- endpoint: Optional boolean specifying this SerDes should be configured as PCIe endpoint.
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Example:
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cpm_comphy: comphy@441000 {
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compatible = "marvell,mvebu-comphy", "marvell,comphy-cp110";
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reg = <0x441000 0x8>, <0x120000 0x8>;
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mux-bitcount = <4>;
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max-lanes = <6>;
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/*
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* CP110 Serdes Configuration:
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* Lane 0: SGMII1
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* Lane 1: SATA 0
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* Lane 2: USB HOST 0
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* Lane 3: SATA1
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* Lane 4: SFI (10G)
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* Lane 5: SGMII2
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*/
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phy0 {
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phy-type = <COMPHY_TYPE_SGMII1>;
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phy-speed = <COMPHY_SPEED_1_25G>;
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};
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phy1 {
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phy-type = <COMPHY_TYPE_SATA0>;
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};
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phy2 {
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phy-type = <COMPHY_TYPE_USB3_HOST0>;
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};
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phy3 {
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phy-type = <COMPHY_TYPE_SATA1>;
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};
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phy4 {
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phy-type = <COMPHY_TYPE_SFI>;
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};
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phy5 {
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phy-type = <COMPHY_TYPE_SGMII2>;
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};
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};
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