2019-01-21 08:17:30 +00:00
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2006 Freescale Semiconductor, Inc.
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* Dave Liu <daveliu@freescale.com>
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*
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* Copyright (C) 2007 Logic Product Development, Inc.
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* Peter Barada <peterb@logicpd.com>
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*
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* Copyright (C) 2007 MontaVista Software, Inc.
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* Anton Vorontsov <avorontsov@ru.mvista.com>
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*
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* (C) Copyright 2010
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* Heiko Schocher, DENX Software Engineering, hs@denx.de.
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*
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* High Level Configuration Options
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*/
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2019-01-21 08:17:31 +00:00
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/* This needs to be set prior to including km83xx-common.h */
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2019-01-21 08:17:30 +00:00
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#define CONFIG_HOSTNAME "kmtegr1"
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#define CONFIG_KM_BOARD_NAME "kmtegr1"
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#define CONFIG_KM_UBI_PARTITION_NAME_BOOT "ubi0"
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#define CONFIG_KM_UBI_PARTITION_NAME_APP "ubi1"
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#define CONFIG_ENV_ADDR 0xF0100000
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#define CONFIG_ENV_OFFSET 0x100000
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#define CONFIG_NAND_ECC_BCH
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#define CONFIG_NAND_KMETER1
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#define CONFIG_SYS_MAX_NAND_DEVICE 1
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#define NAND_MAX_CHIPS 1
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/* include common defines/options for all 8309 Keymile boards */
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2019-01-21 08:17:31 +00:00
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#include "km8309-common.h"
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2019-01-21 08:17:30 +00:00
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/* must be after the include because KMBEC_FPGA is otherwise undefined */
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#define CONFIG_SYS_NAND_BASE CONFIG_SYS_KMBEC_FPGA_BASE /* PRIO_BASE_ADDRESS */
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#define CONFIG_SYS_APP1_BASE 0xA0000000
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#define CONFIG_SYS_APP1_SIZE 256 /* Megabytes */
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#define CONFIG_SYS_APP2_BASE 0xB0000000
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#define CONFIG_SYS_APP2_SIZE 256 /* Megabytes */
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/* EEprom support */
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#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
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/*
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* Init Local Bus Memory Controller:
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*
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* Bank Bus Machine PortSz Size Device
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* ---- --- ------- ------ ----- ------
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* 2 Local UPMA 16 bit 256MB APP1
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* 3 Local GPCM 16 bit 256MB APP2
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*
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*/
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#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_APP2_BASE | \
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BR_PS_16 | \
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BR_MS_GPCM | \
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BR_V)
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#define CONFIG_SYS_OR3_PRELIM (MEG_TO_AM(CONFIG_SYS_APP2_SIZE) | \
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OR_GPCM_SCY_5 | \
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OR_GPCM_TRLX_CLEAR | \
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OR_GPCM_EHTR_CLEAR)
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#define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_APP2_BASE
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#define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_256MB)
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/*
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* MMU Setup
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*/
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#define CONFIG_SYS_IBAT5L (0)
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#define CONFIG_SYS_IBAT5U (0)
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#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
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#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
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#define CONFIG_SYS_IBAT6L (CONFIG_SYS_APP2_BASE | BATL_PP_RW | \
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BATL_MEMCOHERENCE)
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#define CONFIG_SYS_IBAT6U (CONFIG_SYS_APP2_BASE | BATU_BL_256M | \
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BATU_VS | BATU_VP)
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#define CONFIG_SYS_DBAT6L (CONFIG_SYS_APP2_BASE | BATL_PP_RW | \
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BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
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#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
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/* ethernet port connected to piggy (UEC2) */
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#define CONFIG_HAS_ETH1
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#define CONFIG_UEC_ETH2
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#define CONFIG_SYS_UEC2_UCC_NUM 2 /* UCC3 */
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#define CONFIG_SYS_UEC2_RX_CLK QE_CLK_NONE /* not used in RMII Mode */
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#define CONFIG_SYS_UEC2_TX_CLK QE_CLK12
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#define CONFIG_SYS_UEC2_ETH_TYPE FAST_ETH
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#define CONFIG_SYS_UEC2_PHY_ADDR 0
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#define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
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#define CONFIG_SYS_UEC2_INTERFACE_SPEED 100
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#endif /* __CONFIG_H */
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