2014-05-05 10:52:25 +00:00
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/*
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* (C) Copyright 2007-2012
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* Allwinner Technology Co., Ltd. <www.allwinnertech.com>
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* Berg Xing <bergxing@allwinnertech.com>
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* Tom Cubie <tangliang@allwinnertech.com>
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*
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* Sunxi platform dram register definition.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _SUNXI_DRAM_H
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#define _SUNXI_DRAM_H
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2014-12-08 12:38:21 +00:00
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#include <asm/io.h>
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2014-05-05 10:52:25 +00:00
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#include <linux/types.h>
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2014-11-02 19:31:16 +00:00
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/* dram regs definition */
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2014-10-25 18:27:23 +00:00
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#if defined(CONFIG_MACH_SUN6I)
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#include <asm/arch/dram_sun6i.h>
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2014-12-07 13:34:27 +00:00
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#elif defined(CONFIG_MACH_SUN8I)
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#include <asm/arch/dram_sun8i.h>
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2014-10-25 18:27:23 +00:00
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#else
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2014-11-02 19:31:16 +00:00
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#include <asm/arch/dram_sun4i.h>
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2014-10-25 18:27:23 +00:00
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#endif
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2014-05-05 10:52:25 +00:00
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2014-12-08 12:58:53 +00:00
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#define MCTL_MEM_FILL_MATCH_COUNT 64
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2014-05-05 10:52:25 +00:00
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unsigned long sunxi_dram_init(void);
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2014-12-08 12:38:21 +00:00
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/*
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* Wait up to 1s for value to be set in given part of reg.
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*/
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static inline void mctl_await_completion(u32 *reg, u32 mask, u32 val)
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{
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unsigned long tmo = timer_get_us() + 1000000;
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while ((readl(reg) & mask) != val) {
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if (timer_get_us() > tmo)
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panic("Timeout initialising DRAM\n");
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}
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}
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2014-12-08 12:58:53 +00:00
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/*
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* Fill beginning of DRAM with "random" data for mctl_mem_matches()
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*/
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static inline void mctl_mem_fill(void)
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{
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int i;
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for (i = 0; i < MCTL_MEM_FILL_MATCH_COUNT; i++)
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writel(0xaa55aa55 + i, CONFIG_SYS_SDRAM_BASE + i * 4);
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}
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/*
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* Test if memory at offset offset matches memory at begin of DRAM
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*/
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static inline bool mctl_mem_matches(u32 offset)
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{
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2014-12-08 13:17:08 +00:00
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return memcmp((u32 *)CONFIG_SYS_SDRAM_BASE,
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(u32 *)(CONFIG_SYS_SDRAM_BASE + offset),
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MCTL_MEM_FILL_MATCH_COUNT * 4) == 0;
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2014-12-08 12:58:53 +00:00
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}
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2014-05-05 10:52:25 +00:00
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#endif /* _SUNXI_DRAM_H */
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