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u-boot/arch/arm/mach-uniphier/sc64-regs.h

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ARM: uniphier: add System Control register macros for ARMv8 SoCs The System Control block moved to a completely different register map for ARMv8 SoCs, so it cannot be shared with the ARM 32-bit ones. Define register macros in a new header file. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-03-18 07:41:51 +00:00
/*
* UniPhier SC (System Control) block registers for ARMv8 SoCs
*
ARM: uniphier: add PLL init code for LD20 SoC Initialize the DPLL (PLL for DRAM) in SPL, and others in U-Boot proper. Split the common code into pll-base-ld20.c for easier re-use. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-09-16 18:33:11 +00:00
* Copyright (C) 2016 Socionext Inc.
* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
ARM: uniphier: add System Control register macros for ARMv8 SoCs The System Control block moved to a completely different register map for ARMv8 SoCs, so it cannot be shared with the ARM 32-bit ones. Define register macros in a new header file. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-03-18 07:41:51 +00:00
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef SC64_REGS_H
#define SC64_REGS_H
#define SC_BASE_ADDR 0x61840000
#define SC_RSTCTRL (SC_BASE_ADDR | 0x2000)
#define SC_RSTCTRL3 (SC_BASE_ADDR | 0x2008)
#define SC_RSTCTRL4 (SC_BASE_ADDR | 0x200c)
#define SC_RSTCTRL4_ETHER (1 << 6)
#define SC_RSTCTRL4_NAND (1 << 0)
#define SC_RSTCTRL5 (SC_BASE_ADDR | 0x2010)
#define SC_RSTCTRL6 (SC_BASE_ADDR | 0x2014)
#define SC_RSTCTRL7 (SC_BASE_ADDR | 0x2018)
#define SC_RSTCTRL7_UMCSB (1 << 16)
#define SC_RSTCTRL7_UMCA2 (1 << 10)
#define SC_RSTCTRL7_UMCA1 (1 << 9)
#define SC_RSTCTRL7_UMCA0 (1 << 8)
#define SC_RSTCTRL7_UMC32 (1 << 2)
#define SC_RSTCTRL7_UMC31 (1 << 1)
#define SC_RSTCTRL7_UMC30 (1 << 0)
#define SC_CLKCTRL (SC_BASE_ADDR | 0x2100)
#define SC_CLKCTRL3 (SC_BASE_ADDR | 0x2108)
#define SC_CLKCTRL4 (SC_BASE_ADDR | 0x210c)
ARM: uniphier: enable clocks to MIO/STDMAC on LD11 if USB is enabled At the moment, the clk driver is not clever enough to automatically enable parent clocks like Linux. Enable the STDMAC clock explicitly if USB is enabled. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-10-27 14:47:05 +00:00
#define SC_CLKCTRL4_MIO (1 << 10)
#define SC_CLKCTRL4_STDMAC (1 << 8)
ARM: uniphier: add System Control register macros for ARMv8 SoCs The System Control block moved to a completely different register map for ARMv8 SoCs, so it cannot be shared with the ARM 32-bit ones. Define register macros in a new header file. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-03-18 07:41:51 +00:00
#define SC_CLKCTRL4_PERI (1 << 7)
#define SC_CLKCTRL4_ETHER (1 << 6)
#define SC_CLKCTRL4_NAND (1 << 0)
#define SC_CLKCTRL5 (SC_BASE_ADDR | 0x2110)
#define SC_CLKCTRL6 (SC_BASE_ADDR | 0x2114)
#define SC_CLKCTRL7 (SC_BASE_ADDR | 0x2118)
#define SC_CLKCTRL7_UMCSB (1 << 16)
#define SC_CLKCTRL7_UMC32 (1 << 2)
#define SC_CLKCTRL7_UMC31 (1 << 1)
#define SC_CLKCTRL7_UMC30 (1 << 0)
ARM: uniphier: fix addresses of Cortex-A72 gear setting macros My mistake during copy-paste work. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-10-12 12:14:38 +00:00
#define SC_CA72_GEARST (SC_BASE_ADDR | 0x8000)
#define SC_CA72_GEARSET (SC_BASE_ADDR | 0x8004)
#define SC_CA72_GEARUPD (SC_BASE_ADDR | 0x8008)
ARM: uniphier: add PLL init code for LD11 SoC - Initialize PLLs (SPL initializes only DPLL to save the precious SPL memory footprint) - Adjust CPLL/MPLL to the final tape-out frequency - Set the Cortex-A53 clock to the maximum frequency since it is running at 500MHz (SPLL/4) on startup Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-09-21 22:42:19 +00:00
#define SC_CA53_GEARST (SC_BASE_ADDR | 0x8080)
#define SC_CA53_GEARSET (SC_BASE_ADDR | 0x8084)
#define SC_CA53_GEARUPD (SC_BASE_ADDR | 0x8088)
#define SC_CA_GEARUPD (1 << 0)
ARM: uniphier: add System Control register macros for ARMv8 SoCs The System Control block moved to a completely different register map for ARMv8 SoCs, so it cannot be shared with the ARM 32-bit ones. Define register macros in a new header file. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-03-18 07:41:51 +00:00
#endif /* SC64_REGS_H */
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