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u-boot/drivers/crypto/fsl/Kconfig

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DM: crypto/fsl - Add Freescale rsa DM driver Driver added for RSA Modular Exponentiation using Freescale Hardware Accelerator CAAM. The driver uses UCLASS_MOD_EXP Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> CC: Simon Glass <sjg@chromium.org> Acked-by: Simon Glass <sjg@chromium.org>
2015-01-23 10:31:55 +00:00
config FSL_CAAM
bool "Freescale Crypto Driver Support"
lib: move hash CONFIG options to Kconfig Commit 94e3c8c4fd7b ("crypto/fsl - Add progressive hashing support using hardware acceleration.") created entries for CONFIG_SHA1, CONFIG_SHA256, CONFIG_SHA_HW_ACCEL, and CONFIG_SHA_PROG_HW_ACCEL. However, no defconfig has migrated to it. Complete the move by first adding additional logic to various Kconfig files to select this when required and then use the moveconfig tool. In many cases we can select these because they are required to implement other drivers. We also correct how we include the various hashing algorithms in SPL. This commit was generated as follows (after Kconfig additions): [1] tools/moveconfig.py -y SHA1 SHA256 SHA_HW_ACCEL [2] tools/moveconfig.py -y SHA_PROG_HW_ACCEL Note: We cannot move SHA_HW_ACCEL and SHA_PROG_HW_ACCEL simultaneously because there is dependency between them. Cc: Poonam Aggrwal <poonam.aggrwal@freescale.com> Cc: Naveen Burmi <NaveenBurmi@freescale.com> Cc: Po Liu <po.liu@freescale.com> Cc: Shengzhou Liu <Shengzhou.Liu@freescale.com> Cc: Priyanka Jain <Priyanka.Jain@freescale.com> Cc: Shaohui Xie <Shaohui.Xie@freescale.com> Cc: Chunhe Lan <Chunhe.Lan@freescale.com> Cc: Chander Kashyap <k.chander@samsung.com> Cc: Steve Rae <steve.rae@raedomain.com> Cc: Dirk Eibach <eibach@gdsys.de> Cc: Feng Li <feng.li_2@nxp.com> Cc: Alison Wang <alison.wang@freescale.com> Cc: Sumit Garg <sumit.garg@nxp.com> Cc: Mingkai Hu <Mingkai.Hu@freescale.com> Cc: York Sun <york.sun@nxp.com> Cc: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Akshay Saraswat <akshay.s@samsung.com> Cc: Heiko Schocher <hs@denx.de> Cc: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@konsulko.com>
2017-05-15 16:17:49 +00:00
select SHA_HW_ACCEL
image: Drop if/elseif hash selection in calculate_hash() calculate_hash() would try to select the appropriate hashing function by a if/elseif contruct. But that is exactly why hash_lookup_algo() exists, so use it instead. This does mean that we now have to 'select HASH' to make sure we get the hash_lookup_algo() symbol. However, the change makes sense because even basic FITs will have to deal with "hash" nodes. My only concern is that the 'select SPL_HASH' might cause some platform to grow above its SPL size allowance Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> [trini: Make FSL_CAAM be implied only on ARM && SPL] Signed-off-by: Tom Rini <trini@konsulko.com>
2021-09-03 00:54:21 +00:00
# hw_sha1() under drivers/crypto, and needed with SHA_HW_ACCEL
crypto/fsl: Add support for CAAM Job ring driver model added device tree support for job ring driver. sec is initialized based on job ring information processed from device tree. Signed-off-by: Gaurav Jain <gaurav.jain@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2022-03-24 06:20:25 +00:00
select MISC if DM
image: Drop if/elseif hash selection in calculate_hash() calculate_hash() would try to select the appropriate hashing function by a if/elseif contruct. But that is exactly why hash_lookup_algo() exists, so use it instead. This does mean that we now have to 'select HASH' to make sure we get the hash_lookup_algo() symbol. However, the change makes sense because even basic FITs will have to deal with "hash" nodes. My only concern is that the 'select SPL_HASH' might cause some platform to grow above its SPL size allowance Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> [trini: Make FSL_CAAM be implied only on ARM && SPL] Signed-off-by: Tom Rini <trini@konsulko.com>
2021-09-03 00:54:21 +00:00
imply SPL_CRYPTO if (ARM && SPL)
Convert CONFIG_CMD_HASH to Kconfig This converts the following to Kconfig: CONFIG_CMD_HASH Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> [trini: Rework slightly, enable on some boards again] Signed-off-by: Tom Rini <trini@konsulko.com>
2017-05-17 09:25:25 +00:00
imply CMD_HASH
DM: crypto/fsl - Add Freescale rsa DM driver Driver added for RSA Modular Exponentiation using Freescale Hardware Accelerator CAAM. The driver uses UCLASS_MOD_EXP Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> CC: Simon Glass <sjg@chromium.org> Acked-by: Simon Glass <sjg@chromium.org>
2015-01-23 10:31:55 +00:00
help
Enables the Freescale's Cryptographic Accelerator and Assurance
Module (CAAM), also known as the SEC version 4 (SEC4). The driver uses
Job Ring as interface to communicate with CAAM.
crypto: Move SYS_FSL_SEC_COMPAT into driver Kconfig Instead of define CONFIG_SYS_FSL_SEC_COMPAT in header files for PowerPC and ARM SoCs, move it to Kconfig under the driver. Signed-off-by: York Sun <york.sun@nxp.com>
2016-12-28 16:43:30 +00:00
Convert CONFIG_SYS_FSL_MAX_NUM_OF_SEC to Kconfig This converts the following to Kconfig: CONFIG_SYS_FSL_MAX_NUM_OF_SEC Signed-off-by: Tom Rini <trini@konsulko.com>
2022-08-01 01:08:26 +00:00
config SYS_FSL_MAX_NUM_OF_SEC
int "Number of job rings in the CAAM"
depends on FSL_CAAM
default 1
crypto: fsl: refactor for 32 bit version CAAM support on ARM64 Previous patch "MLK-18044-4: crypto: caam: Fix pointer size to 32bit for i.MX8M" breaks the 64 bits CAAM. Since i.MX CAAM are all 32 bits no matter the ARM arch (32 or 64), to adapt and not break 64 bits CAAM support, add a new config CONFIG_CAAM_64BIT and new relevant type "caam_dma_addr_t". This config is default enabled when CONFIG_PHYS_64BIT is set except for iMX8M. Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Horia Geantă <horia.geanta@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2021-03-25 09:30:36 +00:00
config CAAM_64BIT
bool
crypto/fsl: i.MX8: Enable Job ring driver model. i.MX8(QM/QXP) - added support for JR driver model. sec is initialized based on job ring information processed from device tree. Signed-off-by: Gaurav Jain <gaurav.jain@nxp.com> Signed-off-by: Horia Geantă <horia.geanta@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
2022-03-24 06:20:33 +00:00
default y if PHYS_64BIT && !ARCH_IMX8M && !ARCH_IMX8
crypto: fsl: refactor for 32 bit version CAAM support on ARM64 Previous patch "MLK-18044-4: crypto: caam: Fix pointer size to 32bit for i.MX8M" breaks the 64 bits CAAM. Since i.MX CAAM are all 32 bits no matter the ARM arch (32 or 64), to adapt and not break 64 bits CAAM support, add a new config CONFIG_CAAM_64BIT and new relevant type "caam_dma_addr_t". This config is default enabled when CONFIG_PHYS_64BIT is set except for iMX8M. Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Horia Geantă <horia.geanta@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2021-03-25 09:30:36 +00:00
help
Select Crypto driver for 64 bits CAAM version
crypto: Move SYS_FSL_SEC_COMPAT into driver Kconfig Instead of define CONFIG_SYS_FSL_SEC_COMPAT in header files for PowerPC and ARM SoCs, move it to Kconfig under the driver. Signed-off-by: York Sun <york.sun@nxp.com>
2016-12-28 16:43:30 +00:00
config SYS_FSL_HAS_SEC
bool
help
Enable Freescale Secure Boot and Trusted Architecture
config SYS_FSL_SEC_COMPAT_2
bool
help
Secure boot and trust architecture compatible version 2
config SYS_FSL_SEC_COMPAT_4
bool
help
Secure boot and trust architecture compatible version 4
config SYS_FSL_SEC_COMPAT_5
bool
help
Secure boot and trust architecture compatible version 5
config SYS_FSL_SEC_COMPAT_6
bool
help
Secure boot and trust architecture compatible version 6
crypto: Move CONFIG_SYS_FSL_SEC_LE and _BE to Kconfig Use Kconfig option to set little- or big-endian access to secure boot and trust architecture. Signed-off-by: York Sun <york.sun@nxp.com>
2016-12-28 16:43:31 +00:00
config SYS_FSL_SEC_BE
bool "Big-endian access to Freescale Secure Boot"
crypto: Move SYS_FSL_SEC_COMPAT into driver Kconfig Instead of define CONFIG_SYS_FSL_SEC_COMPAT in header files for PowerPC and ARM SoCs, move it to Kconfig under the driver. Signed-off-by: York Sun <york.sun@nxp.com>
2016-12-28 16:43:30 +00:00
config SYS_FSL_SEC_COMPAT
int "Freescale Secure Boot compatibility"
depends on SYS_FSL_HAS_SEC
default 2 if SYS_FSL_SEC_COMPAT_2
default 4 if SYS_FSL_SEC_COMPAT_4
default 5 if SYS_FSL_SEC_COMPAT_5
default 6 if SYS_FSL_SEC_COMPAT_6
crypto: Move CONFIG_SYS_FSL_SEC_LE and _BE to Kconfig Use Kconfig option to set little- or big-endian access to secure boot and trust architecture. Signed-off-by: York Sun <york.sun@nxp.com>
2016-12-28 16:43:31 +00:00
config SYS_FSL_SEC_LE
bool "Little-endian access to Freescale Secure Boot"
crypto/fsl: add RNG support Register the random number generator with the rng subsystem in u-boot. This way it can be used by EFI as well as for the 'rng' command. Signed-off-by: Michael Walle <michael@walle.cc> Tested-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-06-27 20:58:53 +00:00
if FSL_CAAM
config FSL_CAAM_RNG
bool "Enable Random Number Generator support"
depends on DM_RNG
default y
help
Enable support for the hardware based random number generator
module of the CAAM. The random data is fetched from the DRGB
using the prediction resistance flag which means the DRGB is
reseeded from the TRNG every time random data is generated.
endif
Uboot RNG Driver using Data Co-processor This commit introduces Random number generator to uboot. It uses DCP driver for number generation. RNG driver can be invoked by using below command on uboot prompt:- rng <number of bytes> Signed-off-by: Kshitiz Varshney <kshitiz.varshney@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2022-12-22 08:50:27 +00:00
config FSL_DCP_RNG
bool "Enable Random Number Generator support"
depends on DM_RNG
default n
help
Enable support for the hardware based random number generator
module of the DCP. It uses the True Random Number Generator (TRNG)
and a Pseudo-Random Number Generator (PRNG) to achieve a true
randomness and cryptographic strength.
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