2020-12-11 16:05:24 +00:00
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2020 Marvell International Ltd.
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*
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* Fixes and workaround for Octeon chip errata. This file
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* contains functions called by cvmx-helper to workaround known
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* chip errata. For the most part, code doesn't need to call
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* these functions directly.
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*/
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#ifndef __CVMX_HELPER_ERRATA_H__
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#define __CVMX_HELPER_ERRATA_H__
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#include "cvmx-wqe.h"
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/**
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* @INTERNAL
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* Function to adjust internal IPD pointer alignments
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*
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2022-01-19 17:05:50 +00:00
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* Return: 0 on success
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2020-12-11 16:05:24 +00:00
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* !0 on failure
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*/
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int __cvmx_helper_errata_fix_ipd_ptr_alignment(void);
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/**
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* This function needs to be called on all Octeon chips with
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* errata PKI-100.
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*
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* The Size field is 8 too large in WQE and next pointers
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*
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* The Size field generated by IPD is 8 larger than it should
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* be. The Size field is <55:40> of both:
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* - WORD3 in the work queue entry, and
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* - the next buffer pointer (which precedes the packet data
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* in each buffer).
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*
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* @param work Work queue entry to fix
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2022-01-19 17:05:50 +00:00
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* Return: Zero on success. Negative on failure
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2020-12-11 16:05:24 +00:00
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*/
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int cvmx_helper_fix_ipd_packet_chain(cvmx_wqe_t *work);
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/**
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* Due to errata G-720, the 2nd order CDR circuit on CN52XX pass
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* 1 doesn't work properly. The following code disables 2nd order
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* CDR for the specified QLM.
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*
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* @param qlm QLM to disable 2nd order CDR for.
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*/
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void __cvmx_helper_errata_qlm_disable_2nd_order_cdr(int qlm);
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#endif
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