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100 lines
2.4 KiB
C
100 lines
2.4 KiB
C
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/*
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* (C) Copyright 2016 Google, Inc
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _ASM_ARCH_WDT_H
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#define _ASM_ARCH_WDT_H
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#define WDT_BASE 0x1e785000
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/*
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* Special value that needs to be written to counter_restart register to
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* (re)start the timer
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*/
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#define WDT_COUNTER_RESTART_VAL 0x4755
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/* Control register */
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#define WDT_CTRL_RESET_MODE_SHIFT 5
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#define WDT_CTRL_RESET_MODE_MASK 3
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#define WDT_CTRL_EN (1 << 0)
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#define WDT_CTRL_RESET (1 << 1)
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#define WDT_CTRL_CLK1MHZ (1 << 4)
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#define WDT_CTRL_2ND_BOOT (1 << 7)
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/* Values for Reset Mode */
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#define WDT_CTRL_RESET_SOC 0
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#define WDT_CTRL_RESET_CHIP 1
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#define WDT_CTRL_RESET_CPU 2
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#define WDT_CTRL_RESET_MASK 3
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/* Reset Mask register */
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#define WDT_RESET_ARM (1 << 0)
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#define WDT_RESET_COPROC (1 << 1)
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#define WDT_RESET_SDRAM (1 << 2)
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#define WDT_RESET_AHB (1 << 3)
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#define WDT_RESET_I2C (1 << 4)
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#define WDT_RESET_MAC1 (1 << 5)
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#define WDT_RESET_MAC2 (1 << 6)
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#define WDT_RESET_GCRT (1 << 7)
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#define WDT_RESET_USB20 (1 << 8)
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#define WDT_RESET_USB11_HOST (1 << 9)
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#define WDT_RESET_USB11_EHCI2 (1 << 10)
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#define WDT_RESET_VIDEO (1 << 11)
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#define WDT_RESET_HAC (1 << 12)
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#define WDT_RESET_LPC (1 << 13)
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#define WDT_RESET_SDSDIO (1 << 14)
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#define WDT_RESET_MIC (1 << 15)
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#define WDT_RESET_CRT2C (1 << 16)
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#define WDT_RESET_PWM (1 << 17)
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#define WDT_RESET_PECI (1 << 18)
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#define WDT_RESET_JTAG (1 << 19)
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#define WDT_RESET_ADC (1 << 20)
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#define WDT_RESET_GPIO (1 << 21)
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#define WDT_RESET_MCTP (1 << 22)
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#define WDT_RESET_XDMA (1 << 23)
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#define WDT_RESET_SPI (1 << 24)
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#define WDT_RESET_MISC (1 << 25)
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#ifndef __ASSEMBLY__
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struct ast_wdt {
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u32 counter_status;
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u32 counter_reload_val;
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u32 counter_restart;
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u32 ctrl;
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u32 timeout_status;
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u32 clr_timeout_status;
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u32 reset_width;
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#ifdef CONFIG_ASPEED_AST2500
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u32 reset_mask;
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#else
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u32 reserved0;
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#endif
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};
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void wdt_stop(struct ast_wdt *wdt);
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void wdt_start(struct ast_wdt *wdt, u32 timeout);
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/**
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* Reset peripherals specified by mask
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*
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* Note, that this is only supported by ast2500 SoC
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*
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* @wdt: watchdog to use for this reset
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* @mask: reset mask.
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*/
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int ast_wdt_reset_masked(struct ast_wdt *wdt, u32 mask);
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/**
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* ast_get_wdt() - get a pointer to watchdog registers
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*
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* @wdt_number: 0-based WDT peripheral number
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* @return pointer to registers or -ve error on error
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*/
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struct ast_wdt *ast_get_wdt(u8 wdt_number);
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#endif /* __ASSEMBLY__ */
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#endif /* _ASM_ARCH_WDT_H */
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