mirror of
https://github.com/AsahiLinux/u-boot
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97 lines
2.7 KiB
C
97 lines
2.7 KiB
C
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/*
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* (C) Copyright 2002
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef _CPC710_H_
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#define _CPC710_H_
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/* Revision */
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#define CPC710_TYPE_100 0x80
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#define CPC710_TYPE_100P 0x90
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/* System control area */
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#define HW_PHYS_SCA 0xff000000
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#define HW_SCA_CPC0 0x000000
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#define HW_SCA_SDRAM0 0x000000
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#define HW_SCA_DMA0 0x1C0000
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#define HW_PHYS_CPC0 (HW_PHYS_SCA + HW_SCA_CPC0)
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#define HW_PHYS_SDRAM0 (HW_PHYS_SCA + HW_SCA_SDRAM0)
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#define HW_CPC0_PCICNFR 0x000c
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#define HW_CPC0_RSTR 0x0010
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#define HW_CPC0_SPOR 0x00e8
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#define HW_CPC0_UCTL 0x1000
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#define HW_CPC0_SIOC0 0x1020
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#define HW_CPC0_ABCNTL 0x1030
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#define HW_CPC0_SESR 0x1060
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#define HW_CPC0_SEAR 0x1070
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#define HW_CPC0_PGCHP 0x1100
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#define HW_CPC0_RGBAN0 0x1110
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#define HW_CPC0_RGBAN1 0x1120
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#define HW_CPC0_GPDIR 0x1130
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#define HW_CPC0_GPIN 0x1140
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#define HW_CPC0_GPOUT 0x1150
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#define HW_CPC0_ATAS 0x1160
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#define HW_CPC0_PCIBAR 0x200018
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#define HW_CPC0_PCIENB 0x201000
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#define HW_SDRAM0_MCCR 0x1200
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#define HW_SDRAM0_MESR 0x1220
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#define HW_SDRAM0_MEAR 0x1230
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#define HW_SDRAM0_MCER0 0x1300
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#define HW_SDRAM0_MCER1 0x1310
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#define HW_SDRAM0_MCER2 0x1320
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#define HW_SDRAM0_MCER3 0x1330
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#define HW_SDRAM0_MCER4 0x1340
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#define HW_SDRAM0_MCER5 0x1350
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#define HW_SDRAM0_MCER6 0x1360
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#define HW_SDRAM0_MCER7 0x1370
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#define HW_BRIDGE_PCIDG 0xf6120
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#define HW_BRIDGE_INTACK 0xf7700
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#define HW_BRIDGE_PIBAR 0xf7800
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#define HW_BRIDGE_PMBAR 0xf7810
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#define HW_BRIDGE_CRR 0xf7ef0
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#define HW_BRIDGE_PR 0xf7f20
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#define HW_BRIDGE_ACR 0xf7f30
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#define HW_BRIDGE_MSIZE 0xf7f40
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#define HW_BRIDGE_IOSIZE 0xf7f60
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#define HW_BRIDGE_SMBAR 0xf7f80
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#define HW_BRIDGE_SIBAR 0xf7fc0
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#define HW_BRIDGE_CFGADDR 0xf8000
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#define HW_BRIDGE_CFGDATA 0xf8010
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#define HW_BRIDGE_PSSIZE 0xf8100
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#define HW_BRIDGE_BARPS 0xf8120
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#define HW_BRIDGE_PSBAR 0xf8140
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/* Configuration space registers */
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#define CPC710_BUS_NUMBER 0x40
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#define CPC710_SUB_BUS_NUMBER 0x41
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#endif
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