2018-05-06 22:27:01 +00:00
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// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
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2018-03-12 09:46:12 +00:00
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/*
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* Copyright (C) 2018, STMicroelectronics - All Rights Reserved
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*/
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#include <common.h>
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#include <dm.h>
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#include <errno.h>
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#include <i2c.h>
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2019-08-02 11:08:03 +00:00
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#include <misc.h>
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2019-02-04 10:26:19 +00:00
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#include <sysreset.h>
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#include <dm/device.h>
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#include <dm/lists.h>
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2018-03-12 09:46:12 +00:00
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#include <power/pmic.h>
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2019-02-04 10:26:16 +00:00
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#include <power/stpmic1.h>
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2018-03-12 09:46:12 +00:00
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2019-02-04 10:26:17 +00:00
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#define STPMIC1_NUM_OF_REGS 0x100
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2019-02-04 10:26:22 +00:00
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#define STPMIC1_NVM_SIZE 8
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#define STPMIC1_NVM_POLL_TIMEOUT 100000
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#define STPMIC1_NVM_START_ADDRESS 0xf8
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enum pmic_nvm_op {
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SHADOW_READ,
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SHADOW_WRITE,
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NVM_READ,
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NVM_WRITE,
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};
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2019-02-04 10:26:17 +00:00
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#if CONFIG_IS_ENABLED(DM_REGULATOR)
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static const struct pmic_child_info stpmic1_children_info[] = {
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{ .prefix = "ldo", .driver = "stpmic1_ldo" },
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{ .prefix = "buck", .driver = "stpmic1_buck" },
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{ .prefix = "vref_ddr", .driver = "stpmic1_vref_ddr" },
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{ .prefix = "pwr_sw", .driver = "stpmic1_pwr_sw" },
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{ .prefix = "boost", .driver = "stpmic1_boost" },
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2018-04-26 15:13:10 +00:00
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{ },
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};
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#endif /* DM_REGULATOR */
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2018-04-26 15:13:10 +00:00
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static int stpmic1_reg_count(struct udevice *dev)
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2018-03-12 09:46:12 +00:00
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{
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return STPMIC1_NUM_OF_REGS;
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2018-03-12 09:46:12 +00:00
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}
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2019-02-04 10:26:17 +00:00
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static int stpmic1_write(struct udevice *dev, uint reg, const uint8_t *buff,
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int len)
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2018-03-12 09:46:12 +00:00
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{
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int ret;
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ret = dm_i2c_write(dev, reg, buff, len);
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if (ret)
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dev_err(dev, "%s: failed to write register %#x :%d",
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__func__, reg, ret);
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return ret;
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}
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2019-02-04 10:26:17 +00:00
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static int stpmic1_read(struct udevice *dev, uint reg, uint8_t *buff, int len)
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2018-03-12 09:46:12 +00:00
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{
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int ret;
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ret = dm_i2c_read(dev, reg, buff, len);
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if (ret)
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dev_err(dev, "%s: failed to read register %#x : %d",
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__func__, reg, ret);
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return ret;
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}
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2019-02-04 10:26:17 +00:00
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static int stpmic1_bind(struct udevice *dev)
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2018-04-26 15:13:10 +00:00
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{
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2019-08-02 11:08:03 +00:00
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int ret;
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2019-02-04 10:26:17 +00:00
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#if CONFIG_IS_ENABLED(DM_REGULATOR)
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2018-04-26 15:13:10 +00:00
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ofnode regulators_node;
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int children;
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regulators_node = dev_read_subnode(dev, "regulators");
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if (!ofnode_valid(regulators_node)) {
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2019-02-04 10:26:17 +00:00
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dev_dbg(dev, "regulators subnode not found!");
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2018-04-26 15:13:10 +00:00
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return -ENXIO;
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}
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dev_dbg(dev, "found regulators subnode\n");
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children = pmic_bind_children(dev, regulators_node,
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stpmic1_children_info);
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if (!children)
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dev_dbg(dev, "no child found\n");
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#endif /* DM_REGULATOR */
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2018-04-26 15:13:10 +00:00
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2019-08-02 11:08:03 +00:00
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if (!IS_ENABLED(CONFIG_SPL_BUILD)) {
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ret = device_bind_driver(dev, "stpmic1-nvm",
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"stpmic1-nvm", NULL);
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if (ret)
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return ret;
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}
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2019-02-04 10:26:19 +00:00
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if (CONFIG_IS_ENABLED(SYSRESET))
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return device_bind_driver(dev, "stpmic1-sysreset",
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"stpmic1-sysreset", NULL);
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2018-04-26 15:13:10 +00:00
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return 0;
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}
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2019-02-04 10:26:17 +00:00
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static struct dm_pmic_ops stpmic1_ops = {
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.reg_count = stpmic1_reg_count,
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.read = stpmic1_read,
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.write = stpmic1_write,
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2018-03-12 09:46:12 +00:00
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};
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static const struct udevice_id stpmic1_ids[] = {
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{ .compatible = "st,stpmic1" },
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2018-03-12 09:46:12 +00:00
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{ }
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};
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2019-02-04 10:26:17 +00:00
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U_BOOT_DRIVER(pmic_stpmic1) = {
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.name = "stpmic1_pmic",
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2018-03-12 09:46:12 +00:00
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.id = UCLASS_PMIC,
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.of_match = stpmic1_ids,
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.bind = stpmic1_bind,
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.ops = &stpmic1_ops,
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2018-03-12 09:46:12 +00:00
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};
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2019-02-04 10:26:22 +00:00
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#ifndef CONFIG_SPL_BUILD
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static int stpmic1_nvm_rw(struct udevice *dev, u8 addr, u8 *buf, int buf_len,
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enum pmic_nvm_op op)
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{
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unsigned long timeout;
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u8 cmd = STPMIC1_NVM_CMD_READ;
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2019-08-02 11:08:03 +00:00
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int ret, len = buf_len;
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if (addr < STPMIC1_NVM_START_ADDRESS)
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return -EACCES;
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if (addr + buf_len > STPMIC1_NVM_START_ADDRESS + STPMIC1_NVM_SIZE)
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len = STPMIC1_NVM_START_ADDRESS + STPMIC1_NVM_SIZE - addr;
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2019-02-04 10:26:22 +00:00
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2019-08-02 11:08:03 +00:00
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if (op == SHADOW_READ) {
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ret = pmic_read(dev, addr, buf, len);
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if (ret < 0)
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return ret;
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else
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return len;
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}
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2019-02-04 10:26:22 +00:00
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2019-08-02 11:08:03 +00:00
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if (op == SHADOW_WRITE) {
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ret = pmic_write(dev, addr, buf, len);
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if (ret < 0)
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return ret;
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else
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return len;
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}
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2019-02-04 10:26:22 +00:00
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if (op == NVM_WRITE) {
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cmd = STPMIC1_NVM_CMD_PROGRAM;
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2019-08-02 11:08:03 +00:00
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ret = pmic_write(dev, addr, buf, len);
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if (ret < 0)
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return ret;
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}
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ret = pmic_reg_read(dev, STPMIC1_NVM_CR);
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if (ret < 0)
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return ret;
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ret = pmic_reg_write(dev, STPMIC1_NVM_CR, ret | cmd);
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if (ret < 0)
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return ret;
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timeout = timer_get_us() + STPMIC1_NVM_POLL_TIMEOUT;
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for (;;) {
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ret = pmic_reg_read(dev, STPMIC1_NVM_SR);
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if (ret < 0)
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return ret;
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if (!(ret & STPMIC1_NVM_BUSY))
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break;
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if (time_after(timer_get_us(), timeout))
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break;
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}
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if (ret & STPMIC1_NVM_BUSY)
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return -ETIMEDOUT;
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if (op == NVM_READ) {
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2019-08-02 11:08:03 +00:00
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ret = pmic_read(dev, addr, buf, len);
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2019-02-04 10:26:22 +00:00
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if (ret < 0)
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return ret;
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}
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2019-08-02 11:08:03 +00:00
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return len;
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2019-02-04 10:26:22 +00:00
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}
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2019-08-02 11:08:03 +00:00
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static int stpmic1_nvm_read(struct udevice *dev, int offset,
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void *buf, int size)
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{
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enum pmic_nvm_op op = NVM_READ;
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2019-02-04 10:26:22 +00:00
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2019-08-02 11:08:03 +00:00
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if (offset < 0) {
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op = SHADOW_READ;
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offset = -offset;
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}
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2019-02-04 10:26:22 +00:00
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2019-08-02 11:08:03 +00:00
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return stpmic1_nvm_rw(dev->parent, offset, buf, size, op);
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2019-02-04 10:26:22 +00:00
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}
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2019-08-02 11:08:03 +00:00
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static int stpmic1_nvm_write(struct udevice *dev, int offset,
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const void *buf, int size)
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{
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enum pmic_nvm_op op = NVM_WRITE;
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2019-02-04 10:26:22 +00:00
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2019-08-02 11:08:03 +00:00
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if (offset < 0) {
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op = SHADOW_WRITE;
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offset = -offset;
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}
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2019-02-04 10:26:22 +00:00
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2019-08-02 11:08:03 +00:00
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return stpmic1_nvm_rw(dev->parent, offset, (void *)buf, size, op);
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2019-02-04 10:26:22 +00:00
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}
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2019-08-02 11:08:03 +00:00
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static const struct misc_ops stpmic1_nvm_ops = {
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.read = stpmic1_nvm_read,
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.write = stpmic1_nvm_write,
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};
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2019-02-04 10:26:22 +00:00
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2019-08-02 11:08:03 +00:00
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U_BOOT_DRIVER(stpmic1_nvm) = {
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.name = "stpmic1-nvm",
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.id = UCLASS_MISC,
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.ops = &stpmic1_nvm_ops,
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};
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2019-02-04 10:26:22 +00:00
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#endif /* CONFIG_SPL_BUILD */
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2019-02-04 10:26:19 +00:00
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#ifdef CONFIG_SYSRESET
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static int stpmic1_sysreset_request(struct udevice *dev, enum sysreset_t type)
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{
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struct udevice *pmic_dev = dev->parent;
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int ret;
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2019-05-20 07:47:07 +00:00
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if (type != SYSRESET_POWER && type != SYSRESET_POWER_OFF)
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return -EPROTONOSUPPORT;
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ret = pmic_reg_read(pmic_dev, STPMIC1_MAIN_CR);
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if (ret < 0)
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return ret;
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2019-05-20 07:47:07 +00:00
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ret |= STPMIC1_SWOFF;
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ret &= ~STPMIC1_RREQ_EN;
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/* request Power Cycle */
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if (type == SYSRESET_POWER)
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ret |= STPMIC1_RREQ_EN;
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ret = pmic_reg_write(pmic_dev, STPMIC1_MAIN_CR, ret);
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2019-02-04 10:26:19 +00:00
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if (ret < 0)
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return ret;
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return -EINPROGRESS;
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}
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static struct sysreset_ops stpmic1_sysreset_ops = {
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.request = stpmic1_sysreset_request,
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};
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U_BOOT_DRIVER(stpmic1_sysreset) = {
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.name = "stpmic1-sysreset",
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.id = UCLASS_SYSRESET,
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.ops = &stpmic1_sysreset_ops,
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};
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#endif
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