2018-05-30 08:14:35 +00:00
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2010, 2018
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* Allied Telesis <www.alliedtelesis.com>
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*/
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#include <common.h>
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#include <linux/io.h>
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#include <miiphy.h>
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#include <netdev.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/soc.h>
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#include <asm/arch/mpp.h>
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#include <asm/arch/gpio.h>
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/* Note: GPIO differences between specific boards
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*
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* We're trying to avoid having multiple build targets for all the Kirkwood
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* based boards one area where things tend to differ is GPIO usage. For the
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* most part the GPIOs driven by the bootloader are similar enough in function
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* that there is no harm in driving them.
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*
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* XZ4 XS6 XS16 GS24A GT40 GP24A GT24A
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* GPIO39 - INT(<) NC MUX_RST_N(>) NC POE_DIS_N(>) NC
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*/
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#define SBX81LIFKW_OE_LOW ~(BIT(31) | BIT(30) | BIT(28) | BIT(27) | \
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BIT(18) | BIT(17) | BIT(13) | BIT(12) | \
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BIT(10))
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#define SBX81LIFKW_OE_HIGH ~(BIT(0) | BIT(1) | BIT(7))
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#define SBX81LIFKW_OE_VAL_LOW (BIT(31) | BIT(30) | BIT(28) | BIT(27))
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#define SBX81LIFKW_OE_VAL_HIGH (BIT(0) | BIT(1))
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#define MV88E6097_RESET 27
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DECLARE_GLOBAL_DATA_PTR;
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struct led {
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u32 reg;
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u32 value;
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u32 mask;
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};
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struct led amber_solid = {
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MVEBU_GPIO0_BASE,
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BIT(10),
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BIT(18) | BIT(10)
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};
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struct led green_solid = {
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MVEBU_GPIO0_BASE,
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BIT(18) | BIT(10),
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BIT(18) | BIT(10)
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};
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struct led amber_flash = {
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MVEBU_GPIO0_BASE,
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0,
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BIT(18) | BIT(10)
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};
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struct led green_flash = {
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MVEBU_GPIO0_BASE,
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BIT(18),
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BIT(18) | BIT(10)
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};
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static void status_led_set(struct led *led)
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{
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clrsetbits_le32(led->reg, led->mask, led->value);
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}
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int board_early_init_f(void)
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{
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/*
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* default gpio configuration
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* There are maximum 64 gpios controlled through 2 sets of registers
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* the below configuration configures mainly initial LED status
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*/
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mvebu_config_gpio(SBX81LIFKW_OE_VAL_LOW,
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SBX81LIFKW_OE_VAL_HIGH,
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SBX81LIFKW_OE_LOW, SBX81LIFKW_OE_HIGH);
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/* Multi-Purpose Pins Functionality configuration */
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static const u32 kwmpp_config[] = {
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MPP0_SPI_SCn,
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MPP1_SPI_MOSI,
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MPP2_SPI_SCK,
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MPP3_SPI_MISO,
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MPP4_UART0_RXD,
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MPP5_UART0_TXD,
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MPP6_SYSRST_OUTn,
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MPP7_PEX_RST_OUTn,
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MPP8_TW_SDA,
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MPP9_TW_SCK,
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MPP10_GPO,
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MPP11_GPIO,
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MPP12_GPO,
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MPP13_GPIO,
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MPP14_GPIO,
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MPP15_UART0_RTS,
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MPP16_UART0_CTS,
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MPP17_GPIO,
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MPP18_GPO,
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MPP19_GPO,
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MPP20_GPIO,
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MPP21_GPIO,
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MPP22_GPIO,
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MPP23_GPIO,
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MPP24_GPIO,
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MPP25_GPIO,
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MPP26_GPIO,
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MPP27_GPIO,
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MPP28_GPIO,
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MPP29_GPIO,
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MPP30_GPIO,
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MPP31_GPIO,
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MPP32_GPIO,
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MPP33_GPIO,
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MPP34_GPIO,
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MPP35_GPIO,
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MPP36_GPIO,
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MPP37_GPIO,
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MPP38_GPIO,
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MPP39_GPIO,
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MPP40_GPIO,
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MPP41_GPIO,
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MPP42_GPIO,
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MPP43_GPIO,
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MPP44_GPIO,
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MPP45_GPIO,
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MPP46_GPIO,
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MPP47_GPIO,
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MPP48_GPIO,
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MPP49_GPIO,
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0
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};
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kirkwood_mpp_conf(kwmpp_config, NULL);
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return 0;
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}
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int board_init(void)
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{
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/* Power-down unused subsystems. The required
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* subsystems are:
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*
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* GE0 b0
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* PEX0 PHY b1
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* PEX0.0 b2
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* TSU b5
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* SDRAM b6
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* RUNIT b7
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*/
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writel((BIT(0) | BIT(1) | BIT(2) |
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BIT(5) | BIT(6) | BIT(7)),
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KW_CPU_REG_BASE + 0x1c);
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/* address of boot parameters */
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gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
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status_led_set(&amber_solid);
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return 0;
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}
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2018-06-03 04:21:27 +00:00
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#ifdef CONFIG_RESET_PHY_R
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/* automatically defined by kirkwood config.h */
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2018-05-30 08:14:35 +00:00
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void reset_phy(void)
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2018-06-03 04:21:27 +00:00
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{
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}
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#endif
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#ifdef CONFIG_MV88E61XX_SWITCH
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int mv88e61xx_hw_reset(struct phy_device *phydev)
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2018-05-30 08:14:35 +00:00
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{
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/* Ensure the 88e6097 gets at least 10ms Reset
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*/
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kw_gpio_set_value(MV88E6097_RESET, 0);
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mdelay(20);
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kw_gpio_set_value(MV88E6097_RESET, 1);
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mdelay(20);
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2018-06-03 04:21:27 +00:00
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phydev->advertising = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full;
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return 0;
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2018-05-30 08:14:35 +00:00
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}
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#endif
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#ifdef CONFIG_MISC_INIT_R
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int misc_init_r(void)
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{
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status_led_set(&green_flash);
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return 0;
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}
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#endif
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