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u-boot/arch/powerpc/lib/ppccache.S

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ppc: Refactor cache routines, so there is only one common set. Signed-off-by: Rafal Jaworowski <raj@semihalf.com>
2008-01-15 11:52:31 +00:00
/*
* Copyright (C) 1998 Dan Malek <dmalek@jlc.net>
* Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
* Copyright (C) 2000, 2001,2002 Wolfgang Denk <wd@denx.de>
Update Freescale copyrights to remove "All Rights Reserved" "All Rights Reserved" conflicts with the GPL. Signed-off-by: Kumar Gala <kumar.gala@freescale.com>
2009-07-29 02:49:52 +00:00
* Copyright Freescale Semiconductor, Inc. 2004, 2006.
ppc: Refactor cache routines, so there is only one common set. Signed-off-by: Rafal Jaworowski <raj@semihalf.com>
2008-01-15 11:52:31 +00:00
*
Add GPL-2.0+ SPDX-License-Identifier to source files Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com>
2013-07-08 07:37:19 +00:00
* SPDX-License-Identifier: GPL-2.0+
ppc: Refactor cache routines, so there is only one common set. Signed-off-by: Rafal Jaworowski <raj@semihalf.com>
2008-01-15 11:52:31 +00:00
*/
#include <config.h>
#include <ppc_asm.tmpl>
powerpc: add 2 common dcache assembly functions This patch defines the 2 flush_dcache_range and invalidate_dcache_range functions for all the powerpc architecture. Their implementation is borrowed from the kernel's misc_32.S file and replace the ones from mpc86xx and ppc4xx since they were equivalent. This is a fix for the problem introduced by this patch: http://patchwork.ozlabs.org/patch/448849/ Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: York Sun <yorksun@freescale.com>
2015-03-27 15:07:32 +00:00
#include <ppc_defs.h>
#include <asm/cache.h>
ppc: Refactor cache routines, so there is only one common set. Signed-off-by: Rafal Jaworowski <raj@semihalf.com>
2008-01-15 11:52:31 +00:00
/*------------------------------------------------------------------------------- */
/* Function: ppcDcbf */
/* Description: Data Cache block flush */
/* Input: r3 = effective address */
/* Output: none. */
/*------------------------------------------------------------------------------- */
.globl ppcDcbf
ppcDcbf:
dcbf r0,r3
blr
/*------------------------------------------------------------------------------- */
/* Function: ppcDcbi */
/* Description: Data Cache block Invalidate */
/* Input: r3 = effective address */
/* Output: none. */
/*------------------------------------------------------------------------------- */
.globl ppcDcbi
ppcDcbi:
dcbi r0,r3
blr
/*--------------------------------------------------------------------------
* Function: ppcDcbz
* Description: Data Cache block zero.
* Input: r3 = effective address
* Output: none.
*-------------------------------------------------------------------------- */
.globl ppcDcbz
ppcDcbz:
dcbz r0,r3
blr
/*------------------------------------------------------------------------------- */
/* Function: ppcSync */
/* Description: Processor Synchronize */
/* Input: none. */
/* Output: none. */
/*------------------------------------------------------------------------------- */
.globl ppcSync
ppcSync:
sync
blr
powerpc: add 2 common dcache assembly functions This patch defines the 2 flush_dcache_range and invalidate_dcache_range functions for all the powerpc architecture. Their implementation is borrowed from the kernel's misc_32.S file and replace the ones from mpc86xx and ppc4xx since they were equivalent. This is a fix for the problem introduced by this patch: http://patchwork.ozlabs.org/patch/448849/ Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: York Sun <yorksun@freescale.com>
2015-03-27 15:07:32 +00:00
/*
* Write any modified data cache blocks out to memory and invalidate them.
* Does not invalidate the corresponding instruction cache blocks.
*
* flush_dcache_range(unsigned long start, unsigned long stop)
*/
_GLOBAL(flush_dcache_range)
powerpc: Enable flush and invalidate dcache by range for MPC85xx Commit ac337168a unified functions to flush and invalidate dcache by range. These two functions were no-ops for SoCs other than 4xx and MPC86xx. Adding these functions seemed to be correct but introduced issues in some drivers when the dcache was flushed. While the root cause was under investigation, these functions were disabled in Commit cb1629f91a for affected SoCs, including the MPC85xx, to make the various drivers work. On the T208x USB stopped working after v2016.07 was pulled. After re-enabling the dcache functions for the MPC85xx it started working again. The USB and DPPA Ethernet drivers have been seen as operational after this change but other drivers cannot be tested. Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tony O'Brien <tony.obrien@alliedtelesis.co.nz> Cc: Marek Vasut <marex@denx.de> Cc: York Sun <york.sun@nxp.com> Reviewed-by: York Sun <york.sun>
2017-01-06 04:29:45 +00:00
#if defined(CONFIG_4xx) || defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)
powerpc: add 2 common dcache assembly functions This patch defines the 2 flush_dcache_range and invalidate_dcache_range functions for all the powerpc architecture. Their implementation is borrowed from the kernel's misc_32.S file and replace the ones from mpc86xx and ppc4xx since they were equivalent. This is a fix for the problem introduced by this patch: http://patchwork.ozlabs.org/patch/448849/ Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: York Sun <yorksun@freescale.com>
2015-03-27 15:07:32 +00:00
li r5,L1_CACHE_BYTES-1
andc r3,r3,r5
subf r4,r3,r4
add r4,r4,r5
srwi. r4,r4,L1_CACHE_SHIFT
beqlr
mtctr r4
1: dcbf 0,r3
addi r3,r3,L1_CACHE_BYTES
bdnz 1b
sync /* wait for dcbst's to get to ram */
powerpc: Disable flush or invalidate dcache by range for some SoCs Commit ac337168a unified functions to flush and invalidate dcache by range. These two functions were no-op for SoCs other than 4xx and MPC86xx. Adding these functions seemed to be correct but introduced issues when the dcache is flushed. While the root cause is under investigation, disable these functions for affected SoCs so various drivers can work. Signed-off-by: York Sun <york.sun@nxp.com>
2016-04-07 16:56:48 +00:00
#endif
powerpc: add 2 common dcache assembly functions This patch defines the 2 flush_dcache_range and invalidate_dcache_range functions for all the powerpc architecture. Their implementation is borrowed from the kernel's misc_32.S file and replace the ones from mpc86xx and ppc4xx since they were equivalent. This is a fix for the problem introduced by this patch: http://patchwork.ozlabs.org/patch/448849/ Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: York Sun <yorksun@freescale.com>
2015-03-27 15:07:32 +00:00
blr
/*
* Like above, but invalidate the D-cache. This is used by the 8xx
* to invalidate the cache so the PPC core doesn't get stale data
* from the CPM (no cache snooping here :-).
*
* invalidate_dcache_range(unsigned long start, unsigned long stop)
*/
_GLOBAL(invalidate_dcache_range)
powerpc: Enable flush and invalidate dcache by range for MPC85xx Commit ac337168a unified functions to flush and invalidate dcache by range. These two functions were no-ops for SoCs other than 4xx and MPC86xx. Adding these functions seemed to be correct but introduced issues in some drivers when the dcache was flushed. While the root cause was under investigation, these functions were disabled in Commit cb1629f91a for affected SoCs, including the MPC85xx, to make the various drivers work. On the T208x USB stopped working after v2016.07 was pulled. After re-enabling the dcache functions for the MPC85xx it started working again. The USB and DPPA Ethernet drivers have been seen as operational after this change but other drivers cannot be tested. Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tony O'Brien <tony.obrien@alliedtelesis.co.nz> Cc: Marek Vasut <marex@denx.de> Cc: York Sun <york.sun@nxp.com> Reviewed-by: York Sun <york.sun>
2017-01-06 04:29:45 +00:00
#if defined(CONFIG_4xx) || defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)
powerpc: add 2 common dcache assembly functions This patch defines the 2 flush_dcache_range and invalidate_dcache_range functions for all the powerpc architecture. Their implementation is borrowed from the kernel's misc_32.S file and replace the ones from mpc86xx and ppc4xx since they were equivalent. This is a fix for the problem introduced by this patch: http://patchwork.ozlabs.org/patch/448849/ Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: York Sun <yorksun@freescale.com>
2015-03-27 15:07:32 +00:00
li r5,L1_CACHE_BYTES-1
andc r3,r3,r5
subf r4,r3,r4
add r4,r4,r5
srwi. r4,r4,L1_CACHE_SHIFT
beqlr
mtctr r4
sync
1: dcbi 0,r3
addi r3,r3,L1_CACHE_BYTES
bdnz 1b
sync /* wait for dcbi's to get to ram */
powerpc: Disable flush or invalidate dcache by range for some SoCs Commit ac337168a unified functions to flush and invalidate dcache by range. These two functions were no-op for SoCs other than 4xx and MPC86xx. Adding these functions seemed to be correct but introduced issues when the dcache is flushed. While the root cause is under investigation, disable these functions for affected SoCs so various drivers can work. Signed-off-by: York Sun <york.sun@nxp.com>
2016-04-07 16:56:48 +00:00
#endif
powerpc: add 2 common dcache assembly functions This patch defines the 2 flush_dcache_range and invalidate_dcache_range functions for all the powerpc architecture. Their implementation is borrowed from the kernel's misc_32.S file and replace the ones from mpc86xx and ppc4xx since they were equivalent. This is a fix for the problem introduced by this patch: http://patchwork.ozlabs.org/patch/448849/ Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: York Sun <yorksun@freescale.com>
2015-03-27 15:07:32 +00:00
blr
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