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u-boot/include/configs/rk3036_common.h

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SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
2018-05-06 21:58:06 +00:00
/* SPDX-License-Identifier: GPL-2.0+ */
rockchip: rk3036: Add core Soc start-up code rk3036 only 4K size SRAM for SPL, so only support timer, uart, sdram driver in SPL stage, when finish initial sdram, back to bootrom.And in rk3036 sdmmc and debug uart use same iomux, so if you want to boot from sdmmc, you must disable debug uart. Signed-off-by: Lin Huang <hl@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org> Fixed build error for chromebook_jerry, firefly-rk3288: Signed-off-by: Simon Glass <sjg@chromium.org> Series-changes: 8 - Fix build error for chromebook_jerry, firefly-rk3288
2015-11-17 06:20:27 +00:00
/*
* (C) Copyright 2015 Rockchip Electronics Co., Ltd
*/
#ifndef __CONFIG_RK3036_COMMON_H
#define __CONFIG_RK3036_COMMON_H
rockchip: use 'arch-rockchip' as header file path Rockchip use 'arch-rockchip' instead of arch-$(SOC) as common header file path, so that we can get the correct path directly. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-03-28 03:01:23 +00:00
#include <asm/arch-rockchip/hardware.h>
rockchip: use rockchip linux partitions layout Unify the partitions of each chip then it will be more easy for us to write scripts, tools or guides for rockchip chips. Those extra partitions mostly are used to be compatible with our internal loaders (such as miniloader which was same as spl, or android loader then we can support dual boot) Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2016-10-08 05:47:41 +00:00
#include "rockchip-common.h"
rockchip: rk3036: Add core Soc start-up code rk3036 only 4K size SRAM for SPL, so only support timer, uart, sdram driver in SPL stage, when finish initial sdram, back to bootrom.And in rk3036 sdmmc and debug uart use same iomux, so if you want to boot from sdmmc, you must disable debug uart. Signed-off-by: Lin Huang <hl@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org> Fixed build error for chromebook_jerry, firefly-rk3288: Signed-off-by: Simon Glass <sjg@chromium.org> Series-changes: 8 - Fix build error for chromebook_jerry, firefly-rk3288
2015-11-17 06:20:27 +00:00
rockchip: rk3036: use ARM arch timer instead of rk_timer We prefer to use ARM arch timer instead of rockchip timer, so that we are using the same timer for SPL, U-Boot and Kernel, which will make things simple and easy to track the boot time. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-07-09 14:00:25 +00:00
#define CONFIG_SYS_HZ_CLOCK 24000000
rockchip: rk3036: Add core Soc start-up code rk3036 only 4K size SRAM for SPL, so only support timer, uart, sdram driver in SPL stage, when finish initial sdram, back to bootrom.And in rk3036 sdmmc and debug uart use same iomux, so if you want to boot from sdmmc, you must disable debug uart. Signed-off-by: Lin Huang <hl@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org> Fixed build error for chromebook_jerry, firefly-rk3288: Signed-off-by: Simon Glass <sjg@chromium.org> Series-changes: 8 - Fix build error for chromebook_jerry, firefly-rk3288
2015-11-17 06:20:27 +00:00
#define CONFIG_ROCKCHIP_MAX_INIT_SIZE (4 << 10)
#define CONFIG_ROCKCHIP_CHIP_TAG "RK30"
#define CONFIG_SYS_SDRAM_BASE 0x60000000
#define SDRAM_BANK_SIZE (512UL << 20UL)
rockchip: add sdram_common for common functions There are some functions like sdram_size_mb can be re-used for different rockchip SoCs, just put them into common file. Add board_get_usable_ram_top() for ram_top init base on SDRAM_MAX_SIZE. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Added SDRAM_MAX_SIZE definition for RK3036: Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> fixup: 3036 fix for sdram_common
2017-06-23 08:11:05 +00:00
#define SDRAM_MAX_SIZE (CONFIG_NR_DRAM_BANKS * SDRAM_BANK_SIZE)
rockchip: rk3036: Add core Soc start-up code rk3036 only 4K size SRAM for SPL, so only support timer, uart, sdram driver in SPL stage, when finish initial sdram, back to bootrom.And in rk3036 sdmmc and debug uart use same iomux, so if you want to boot from sdmmc, you must disable debug uart. Signed-off-by: Lin Huang <hl@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org> Fixed build error for chromebook_jerry, firefly-rk3288: Signed-off-by: Simon Glass <sjg@chromium.org> Series-changes: 8 - Fix build error for chromebook_jerry, firefly-rk3288
2015-11-17 06:20:27 +00:00
#ifndef CONFIG_SPL_BUILD
rockchip: add fastboot support for rk3036 board Enable fastboot feature on rk3036, please refer to doc/README.rockchip for more detailed usage. Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2016-07-28 03:42:34 +00:00
rockchip: rk3036: Add core Soc start-up code rk3036 only 4K size SRAM for SPL, so only support timer, uart, sdram driver in SPL stage, when finish initial sdram, back to bootrom.And in rk3036 sdmmc and debug uart use same iomux, so if you want to boot from sdmmc, you must disable debug uart. Signed-off-by: Lin Huang <hl@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org> Fixed build error for chromebook_jerry, firefly-rk3288: Signed-off-by: Simon Glass <sjg@chromium.org> Series-changes: 8 - Fix build error for chromebook_jerry, firefly-rk3288
2015-11-17 06:20:27 +00:00
#define ENV_MEM_LAYOUT_SETTINGS \
"scriptaddr=0x60000000\0" \
"pxefile_addr_r=0x60100000\0" \
"fdt_addr_r=0x61f00000\0" \
"kernel_addr_r=0x62000000\0" \
"ramdisk_addr_r=0x64000000\0"
#include <config_distro_bootcmd.h>
/* Linux fails to load the fdt if it's loaded above 512M on a evb-rk3036 board,
* so limit the fdt reallocation to that */
#define CONFIG_EXTRA_ENV_SETTINGS \
rockchip: utilize CONFIG_DEFAULT_FDT_FILE Currently the fdtfile environment variable is set to CONFIG_DEFAULT_DEVICE_TREE which is іnternally used as U-Boot devicetree source. The OS can use a different filename and Kconfig gives us the ability to select a default devicetree via CONFIG_DEFAULT_FDT_FILE. This also gives user configuring U-Boot via menuconfig the behaviour someone would expect. Signed-off-by: Klaus Goger <klaus.goger@theobroma-systems.com> Tested-By: Vagrant Cascadian <vagrant@debian.org> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-05-25 21:45:05 +00:00
"fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
rockchip: rk3036: Add core Soc start-up code rk3036 only 4K size SRAM for SPL, so only support timer, uart, sdram driver in SPL stage, when finish initial sdram, back to bootrom.And in rk3036 sdmmc and debug uart use same iomux, so if you want to boot from sdmmc, you must disable debug uart. Signed-off-by: Lin Huang <hl@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org> Fixed build error for chromebook_jerry, firefly-rk3288: Signed-off-by: Simon Glass <sjg@chromium.org> Series-changes: 8 - Fix build error for chromebook_jerry, firefly-rk3288
2015-11-17 06:20:27 +00:00
"fdt_high=0x7fffffff\0" \
rockchip: move partitons define from 3036-kylin to 3036-common To keep it same with 3288. Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
2016-09-19 10:46:25 +00:00
"partitions=" PARTS_DEFAULT \
rockchip: rk3036: Add core Soc start-up code rk3036 only 4K size SRAM for SPL, so only support timer, uart, sdram driver in SPL stage, when finish initial sdram, back to bootrom.And in rk3036 sdmmc and debug uart use same iomux, so if you want to boot from sdmmc, you must disable debug uart. Signed-off-by: Lin Huang <hl@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org> Fixed build error for chromebook_jerry, firefly-rk3288: Signed-off-by: Simon Glass <sjg@chromium.org> Series-changes: 8 - Fix build error for chromebook_jerry, firefly-rk3288
2015-11-17 06:20:27 +00:00
ENV_MEM_LAYOUT_SETTINGS \
BOOTENV
#endif
#endif
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