2020-08-26 12:37:42 +00:00
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/* SPDX-License-Identifier: GPL-2.0
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*
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* Copyright (C) 2018 Marvell International Ltd.
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*/
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#ifndef __CGX_H__
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#define __CGX_H__
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#include "cgx_intf.h"
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#define PCI_DEVICE_ID_OCTEONTX2_CGX 0xA059
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#define MAX_LMAC_PER_CGX 4
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#define CGX_PER_NODE 3
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enum lmac_type {
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LMAC_MODE_SGMII = 0,
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LMAC_MODE_XAUI = 1,
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LMAC_MODE_RXAUI = 2,
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LMAC_MODE_10G_R = 3,
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LMAC_MODE_40G_R = 4,
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LMAC_MODE_QSGMII = 6,
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LMAC_MODE_25G_R = 7,
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LMAC_MODE_50G_R = 8,
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LMAC_MODE_100G_R = 9,
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LMAC_MODE_USXGMII = 10,
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};
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extern char lmac_type_to_str[][8];
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extern char lmac_speed_to_str[][8];
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struct lmac_priv {
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u8 enable:1;
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u8 full_duplex:1;
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u8 speed:4;
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u8 mode:1;
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u8 rsvd:1;
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u8 mac_addr[6];
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};
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struct cgx;
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struct nix;
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struct nix_af;
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struct lmac {
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struct cgx *cgx;
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struct nix *nix;
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char name[16];
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enum lmac_type lmac_type;
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bool init_pend;
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u8 instance;
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u8 lmac_id;
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u8 pknd;
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u8 link_num;
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u32 chan_num;
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u8 mac_addr[6];
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};
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struct cgx {
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struct nix_af *nix_af;
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void __iomem *reg_base;
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struct udevice *dev;
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struct lmac *lmac[MAX_LMAC_PER_CGX];
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u8 cgx_id;
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u8 lmac_count;
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};
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static inline void cgx_write(struct cgx *cgx, u8 lmac, u64 offset, u64 val)
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{
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writeq(val, cgx->reg_base + CMR_SHIFT(lmac) + offset);
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}
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static inline u64 cgx_read(struct cgx *cgx, u8 lmac, u64 offset)
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{
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return readq(cgx->reg_base + CMR_SHIFT(lmac) + offset);
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}
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/**
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* Given an LMAC/PF instance number, return the lmac
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* Per design, each PF has only one LMAC mapped.
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*
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* @param instance instance to find
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*
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2022-01-19 17:05:50 +00:00
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* Return: pointer to lmac data structure or NULL if not found
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2020-08-26 12:37:42 +00:00
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*/
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struct lmac *nix_get_cgx_lmac(int lmac_instance);
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int cgx_lmac_set_pkind(struct lmac *lmac, u8 lmac_id, int pkind);
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int cgx_lmac_internal_loopback(struct lmac *lmac, int lmac_id, bool enable);
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int cgx_lmac_rx_tx_enable(struct lmac *lmac, int lmac_id, bool enable);
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int cgx_lmac_link_enable(struct lmac *lmac, int lmac_id, bool enable,
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u64 *status);
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int cgx_lmac_link_status(struct lmac *lmac, int lmac_id, u64 *status);
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void cgx_lmac_mac_filter_setup(struct lmac *lmac);
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int cgx_intf_get_link_sts(u8 cgx, u8 lmac, u64 *lnk_sts);
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int cgx_intf_link_up_dwn(u8 cgx, u8 lmac, u8 up_dwn, u64 *lnk_sts);
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int cgx_intf_get_mac_addr(u8 cgx, u8 lmac, u8 *mac);
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int cgx_intf_set_macaddr(struct udevice *dev);
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int cgx_intf_prbs(u8 qlm, u8 mode, u32 time, u8 lane);
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int cgx_intf_display_eye(u8 qlm, u8 lane);
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int cgx_intf_display_serdes(u8 qlm, u8 lane);
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#endif /* __CGX_H__ */
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