2011-05-24 20:02:56 +00:00
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/*
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* Copyright (C) 2011 Samsung Electronics
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*
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2013-07-08 07:37:19 +00:00
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* SPDX-License-Identifier: GPL-2.0+
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2011-05-24 20:02:56 +00:00
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <netdev.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/gpio.h>
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#include <asm/arch/mmc.h>
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2013-07-04 06:59:16 +00:00
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#include <asm/arch/periph.h>
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#include <asm/arch/pinmux.h>
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2011-05-24 20:02:56 +00:00
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#include <asm/arch/sromc.h>
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DECLARE_GLOBAL_DATA_PTR;
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static void smc9115_pre_init(void)
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{
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u32 smc_bw_conf, smc_bc_conf;
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/* gpio configuration GPK0CON */
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2014-05-13 05:00:14 +00:00
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gpio_cfg_pin(EXYNOS4_GPIO_Y00 + CONFIG_ENV_SROM_BANK, S5P_GPIO_FUNC(2));
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2011-05-24 20:02:56 +00:00
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/* Ethernet needs bus width of 16 bits */
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smc_bw_conf = SROMC_DATA16_WIDTH(CONFIG_ENV_SROM_BANK);
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smc_bc_conf = SROMC_BC_TACS(0x0F) | SROMC_BC_TCOS(0x0F)
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| SROMC_BC_TACC(0x0F) | SROMC_BC_TCOH(0x0F)
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| SROMC_BC_TAH(0x0F) | SROMC_BC_TACP(0x0F)
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| SROMC_BC_PMC(0x0F);
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/* Select and configure the SROMC bank */
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s5p_config_sromc(CONFIG_ENV_SROM_BANK, smc_bw_conf, smc_bc_conf);
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}
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int board_init(void)
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{
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smc9115_pre_init();
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gd->bd->bi_boot_params = (PHYS_SDRAM_1 + 0x100UL);
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return 0;
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}
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int dram_init(void)
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{
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gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE)
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+ get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE)
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+ get_ram_size((long *)PHYS_SDRAM_3, PHYS_SDRAM_3_SIZE)
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+ get_ram_size((long *)PHYS_SDRAM_4, PHYS_SDRAM_4_SIZE);
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return 0;
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}
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void dram_init_banksize(void)
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{
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gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
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2011-09-20 21:25:02 +00:00
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gd->bd->bi_dram[0].size = get_ram_size((long *)PHYS_SDRAM_1, \
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PHYS_SDRAM_1_SIZE);
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2011-05-24 20:02:56 +00:00
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gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
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2011-09-20 21:25:02 +00:00
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gd->bd->bi_dram[1].size = get_ram_size((long *)PHYS_SDRAM_2, \
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PHYS_SDRAM_2_SIZE);
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2011-05-24 20:02:56 +00:00
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gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
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2011-09-20 21:25:02 +00:00
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gd->bd->bi_dram[2].size = get_ram_size((long *)PHYS_SDRAM_3, \
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PHYS_SDRAM_3_SIZE);
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2011-05-24 20:02:56 +00:00
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gd->bd->bi_dram[3].start = PHYS_SDRAM_4;
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2011-09-20 21:25:02 +00:00
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gd->bd->bi_dram[3].size = get_ram_size((long *)PHYS_SDRAM_4, \
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PHYS_SDRAM_4_SIZE);
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2011-05-24 20:02:56 +00:00
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}
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int board_eth_init(bd_t *bis)
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{
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int rc = 0;
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#ifdef CONFIG_SMC911X
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rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
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#endif
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return rc;
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}
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#ifdef CONFIG_DISPLAY_BOARDINFO
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int checkboard(void)
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{
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printf("\nBoard: SMDKV310\n");
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return 0;
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}
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#endif
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#ifdef CONFIG_GENERIC_MMC
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int board_mmc_init(bd_t *bis)
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{
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int i, err;
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/*
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* MMC2 SD card GPIO:
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*
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* GPK2[0] SD_2_CLK(2)
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* GPK2[1] SD_2_CMD(2)
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* GPK2[2] SD_2_CDn
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* GPK2[3:6] SD_2_DATA[0:3](2)
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*/
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2014-05-13 05:00:14 +00:00
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for (i = EXYNOS4_GPIO_K20; i < EXYNOS4_GPIO_K27; i++) {
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2011-05-24 20:02:56 +00:00
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/* GPK2[0:6] special function 2 */
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2014-05-13 05:00:14 +00:00
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gpio_cfg_pin(i, S5P_GPIO_FUNC(0x2));
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2011-05-24 20:02:56 +00:00
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/* GPK2[0:6] drv 4x */
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2014-05-13 05:00:14 +00:00
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gpio_set_drv(i, S5P_GPIO_DRV_4X);
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2011-05-24 20:02:56 +00:00
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/* GPK2[0:1] pull disable */
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2014-05-13 05:00:14 +00:00
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if (i == EXYNOS4_GPIO_K20 || i == EXYNOS4_GPIO_K21) {
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gpio_set_pull(i, S5P_GPIO_PULL_NONE);
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2011-05-24 20:02:56 +00:00
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continue;
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}
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/* GPK2[2:6] pull up */
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2014-05-13 05:00:14 +00:00
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gpio_set_pull(i, S5P_GPIO_PULL_UP);
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2011-05-24 20:02:56 +00:00
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}
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err = s5p_mmc_init(2, 4);
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return err;
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}
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#endif
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2013-07-04 06:59:16 +00:00
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static int board_uart_init(void)
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{
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int err;
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err = exynos_pinmux_config(PERIPH_ID_UART0, PINMUX_FLAG_NONE);
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if (err) {
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debug("UART0 not configured\n");
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return err;
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}
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err = exynos_pinmux_config(PERIPH_ID_UART1, PINMUX_FLAG_NONE);
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if (err) {
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debug("UART1 not configured\n");
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return err;
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}
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err = exynos_pinmux_config(PERIPH_ID_UART2, PINMUX_FLAG_NONE);
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if (err) {
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debug("UART2 not configured\n");
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return err;
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}
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err = exynos_pinmux_config(PERIPH_ID_UART3, PINMUX_FLAG_NONE);
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if (err) {
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debug("UART3 not configured\n");
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return err;
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}
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return 0;
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}
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#ifdef CONFIG_BOARD_EARLY_INIT_F
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int board_early_init_f(void)
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{
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int err;
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err = board_uart_init();
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if (err) {
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debug("UART init failed\n");
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return err;
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}
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return err;
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}
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#endif
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